SDO CDH Subsystem Mission PDR

C&DH SDO Preliminary Design Review (PDR) – March 9 - 12, 2004

SDO CDH SubsystemMission PDR

Jack McCabe, Code 561SDO CDH PDL

SDO CDH PDTSchumacher, Pack, Culver, Dailey, Haghani, Folk, Li,

Hovmand, Ballou, Hawkins, Winkert, Hestnes, Calderwood, Nearhoof, Luers, Smith, Younger & Padgett


MRD v5.0 Level 2 – Driving Requirements

• 2.2.2 Fault Tolerance– Design shall be either

• Single fault tolerant and meet minimum success criteria. Or• Employ sufficient testing/analysis to ensure system reliability where fault tolerance & graceful degradation does not exist.

– Interpretation of this requirement (graceful degradation ) leads to cross strapping, redundancy, robust system design.

• 2.3.2 Radiation– TID 400 Krad – 100Mils, 40 Krad – 200Mils– SEE – Destructive LET > 100 Mev– SEE – Non Destructive LET <37 Mev

• 4.4.2.2 Ka Band– 150 Mbps continuous I & Q science data to the ground.– ATMEL device TSS901E– Autonomous HSB link re-sync.

• 4.4.3.1 Data System– Distributed Architecture– Common nodal power supply, power switching, and backplane protocol.

• 4.4.3.6.3.2 Stored telemetry– 90 Mbytes minimum of Recorder Space.

• 4.4.3.7.2 Bit error– HSB Bit Error Rate < than 1x10-10

• (CDH portion, Instrument output to RF conversion, of 99.99% completeness budget)


CDH Subsystem Top Level Design

• Primary Subsystem Responsibilities– Serve as the S-Band uplink & downlink interface between the ground and the observatory.– Serve as the Ka-Band downlink interface between the instruments and the ground.– High Speed Bus (HSB) End To End oversight.– Serve as spacecraft 1553 Bus controller.– Provide the main computing power for the spacecraft.– Provide spacecraft Bulk Memory. – Provide for limited 28V power distribution.– Provide for limited spacecraft telemetry gathering and processing.

• Subsystem Components– S_Comm Card S-Band uplink & downlink interface, 28V power distribution control,

telemetry gathering and processing.– Ka_Comm Card Ka-Band downlink interface.– SBC & BMC Cards Main computing power, 1553 Bus controller, Bulk Memory.– DCDC Cards Local Subsystem power.– Backplane Local Subsystem data transfer.– PCC & LPSC Provided by 563 for primary power and service switching

• Subsystem Redundancy– The CDH Subsystem is fully redundant and its components are housed in two identical boxes.– Each box is comprised of three independent functional entities, coupled by a local Subsystem Backplane– Data busses and switched & un-switched power are cross strapped.


Implementation & Architecture

• Three independent functional units enclosed in the same box– Single Board Computer, DC/DC and BMC card function as the main Spacecraft Processor

and bus controller.– SDN-based S Comm Uplink/Downlink card, provides command and housekeeping telemetry

interface to S-band Transponders.– Ka Comm card, receives science data from instruments via ATMEL 1355 interface, Formats,

encodes and transmits I&Q serial data to Ka Transmitter for downlink.

• S Comm card controls a separately powered LPSC which is used to provide power to remaining C&DH components

– Allows for power switching to SBC’s without reliance on 1553 bus or hardware decoded commands

– Hardware commands exist to reset S Comm card, reset PSE, and power cycle PSE services– S Comm card receives un-switched power, but LPSC switch card power is switched by PSE,

providing fault isolation in the event of S Comm card failure

• Both Ka Comm and S Comm cards provide cross-strapped interfaces to their respective RF systems

– S Comm receives real time telemetry over 1553 bus, and playback over Serial Port. Serial port is cross strapped from Bulk Memory Card

– Ka Comm provides for two 100Mbit links to each of the three instruments. Instruments have option to spread data over both links or just one link (baseline is two links).


Changes since SCR

• Added Bulk Memory Card to subsystem architecture– MRD (4.4.3.6.3.2) requirement for 90 Mbytes of storage.

• SPN split into two card (PCC & LPSC) – MRD (4.3.3) Power Distribution

• Power sequence circuit to accommodate ACTEL FPGA inrush GIDEP alert. – ACTEL guide up alert for possible In-rush problems.

• Added 2.5V voltage to CDH backplane design to accommodate ACTEL FPGA inrush guide up alert

– ACTEL guide up alert for possible In-rush problems.

• Ka Card DL ASIC to generate serialized I & Q instead of previous baseline to use commercial serializer

– Radiation issues made previous part unreliable for baselined BER & clock distribution.

• Clock circuit redesign to Ka card.– Radiation issues made previous part unreliable for baselined clock distribution. And MRD (4.4.2.2) for 150

Mbps downlink

• Added HSB Link resync capability • Backplane bus protocol changed from “Simple Bus” to cPCI.

– MRD (4.4.3.1) & program decision to use a standard bus protocol over non-standard bus protocol.


SDO Electrical Architecture

ACE SDNBC

RT

1553 Bus

28V Power to ACS sensors, actuators &heaters

Thermistors, HGA sensors

to S- Band

IRU

Propulsion

RT

28V Power to ACS sensors, actuators & heaters

DC-DC Converter

RT

Battery

PSE

SDN

Bat

tery

Mod

ule

3 O

utpu

t Mod

ules

PSE

SDN

DC

-DC

Con

vert

er

RT

Dep

loy

Circ

uits

28V power 28V power

ST #1

ST #2

RT

RT

RT

RT RT

RT

CSS

CSS

Engine Valve Driver boards

RWA I/O

ACE SDN

RWA I/O

Prop Pyro board

Engine Valve Driver boards

DC-DC Converter

DC

-DC

Con

vert

er

Gimbal Interface

DC-DC Converter

28V powerPwr Switching

DC/DC Converter

Bulk Memory &DC/DC Converter

S/C Processor

RT

Pwr Switching

3 O

utpu

t Mod

ules

Sola

r Arr

ay M

odul

e

SolarArray

Sola

r Arr

ay M

odul

e

SolarArray

PSE

ACE A

ACE B

GCECDH A

RW #1

RW #3RW #2RW #4

AIA

AEB4 Optics

& CEB

GT’s

HMI Inst Electronics

HMIHMI Optics

& CEB

EVE IEM (incl. SDN)

EVE

MEGS

ESP

DC-DC Converter

Power Switching

Uplink/DownlinkS Band SDN

High SpeedData Ka Band

H/W decoded cmds

28V Power to Gimbal drives,

Instrument Module thermal control

Ka XMTR A

Ka XMTR B

from Ka Comm B

Waveguide Switch

to HighGain

Antennae

SynchronousSerial Bus

to Up/Down B

RT

toKa- Band

from Instruments

DC-DC Converter

Housekeeping SDN

Gimbal InterfaceRT

BC

RTH/W decoded cmdsUplink/Downlink

S Band SDN

28V power to SBC, Ka Comm, S XMTR

DC-DC Converter

DC/DC Converter

High SpeedData Ka Band

Bulk Memory &DC/DC Converter

S/C Processor

RT

Pwr Switching

Housekeeping SDN

CDH B

Pwr Switching

SXPNDR A

S XPNDR B

3 dB Hybrid

to Omnisfrom S

Comm A

SynchronousSerial Bus

to Up/DownA

Power Switching

Prop Pyro board


CDH Subsystem Architecture – Box 1

LPSC PCC

SDN S COMM

DCDC/ BMC

SBC

DCDC Ka Comm

RT BC RT

S/C 1553 BusA&B

S BandUplink IFA&B

S BandDownlink IFA&B

Ka BandLVDSHSB IFA&B

Instruments13553 x 2 portHSB IF

Dual PSE A&BUnSwitched 28 V

PlaybackSerial IF - A

PlaybackSerial IF - B

TelemetryCollection &DiscreteCommandingA&B

Local CDH BackplaneRegion - 1



Switched 28 V

Switched 28 V

Switched 28 VS Band TX A&B

Dual PSE A&BSwitched 28 V

Switched 28 VHeater Control

Data

PowerDiscrete

Switched 28 VCDH Region 2-BSwitched 28 VCDH Region 3-B

PlaybackSerial IF - B

(2.5V, 3.3V, 5V)(2.5V, 3.3V, 5V)(2.5V, 3.3V, 5V, +/- 15V)


Heritage

• Level of heritage in the SDO CDH Subsystem– Region One (S Band Comm, Power, Switching)

• SDN based S_Comm cardo Functional Concept has MAP/EO-1 heritageo Processor however is new (Cold fire rather than UT69R000)

• Backplaneo Backplane Interface is cPCI (standard used on SWIFT). Flight applications that comply with standard have been

imposed on interface.

• Powero PCC and LPSC have functional heritage with MAP/EO-1

– Region Two (Processor/Recorder/cPCI Backplane)• Functional capabilities have standard flight heritage.• Requirements for SBC can be met with commercially available designs• Bulk Memory has functional heritage with DRAM and serial playback capabilities.• cPCI interface is to be commercial standard.

– Region Three (HSB/Ka_Comm)• ATMEL 1355 device has limited heritage from STEREO• Data rate (150Mbps) with no storage and continuous playback has no heritage

– Subsystem Enclosure and card design• Will have maximum manufacturing heritage with MAP/EO-1.


Technical Resources

Description Detail Units Project Allocation/Estimate Subsystem Estimate Status Comment

Mass Kgs(Lbs) 28 26 (58) Applies to Boxes 1 & 2

Launch Watts 73 50 to 63 Appropriate section of each box is powered

Nominal/Eclipse Watts 95 66 to 83 Appropriate section of each box is powered

Height Meters (inches) - .254 (10.0) Applies to a single box. Two boxes in Subsystem

Length Meters (inches) - .251 (9.9) Applies to a single box. Two boxes in Subsystem

Width Meters (inches) - .343 (13.5) Applies to a single box. Two boxes in Subsystem

Power

Volume


S-Band Telemetry Functional Flow

S Band Telemetry Allocations (As of System PDR 12-02-03)

TLM Mode TDRS (LEO) Emergency @ GEO Contingency Normal (w ith

Ranging)Prop Manuever (with Ranging)

LEO, Launch, Recorder Dump

Real Time TLM Rate (bps) 2000 2000 8000 32000 32000 32000Effective TLM Rate (bps) 1700 1700 6800 27220 27220 27220Filter Table 1 2 3 4 5 6Reserve PDR (~15% of effective) 255 255 1020 4083 4083 4083Allocated (~83 to 85% of effective) 1408 1445 5780 23072 22548 22864Used (bps) 1663 1700 6800 27155 26631 26947Used (%bps) 98% 100% 100% 100% 98% 99%

(From SDO Systems PDR)

PrimaryS-Comm

Hybrid

RedundantS-Comm

Serial I/Fs PrimaryX-Ponder

RedundantX-Ponder

PrimaryCDH

ProcessingElement

RedundantCDH

ProcessingElement

1553Bus

RedundantKa-Comm

PrimaryKa-Comm


S_Comm Hardware Commands

Hardware Commands# Description Side0 S-Comm Processor /ASD A1 PSE Processor /ASD A2 PSE POR A3 SBC A4 S_Comm POR A5 CDH BC Mode A6 Spare A7 Spare A8 S-Comm Processor /ASD B9 PSE Processor /ASD B10 PSE POR B11 SBC B12 S_Comm POR B13 CDH BC Mode B14 Spare B15 Spare B


Processing Element Development Strategy

Single Board Computer (SBC)• The Single Board Computer (SBC) will be

procured as a commercial item (i.e.. An item that is available for sale in the commercial marketplace)

• SBC requirements are captured in the following SDO documents based on numerous meetings with SDO subsystem engineers and limited market research of known vendors:

– Performance Specification - 464-CDH-SPEC-0012

– Statement of Work (SOW) - 464-CDH-LEGL-0008

• Spec and SOW incorporated into a Request-for-Offer (RFO) package to industry.

Bulk Memory Card (BMC)• Interface to SBC via cPCI bus (32-Bit,

33MHz)• SBC ICD/Specification

• Provide a minimum 90 Mbytes of data storage• MRD Level 2 Directed

• Allow playback of stored telemetry directly to S-COMM card with a maximum clock rate of 2 MHz• S-COMM Card ICD/Specification

• Provide throughput for power from DC/DC card to SBC• DC/DC Card ICD/Specification

• Support Reset interface to SBC• SBC procurement

• Support 1553 BC Interface• SBC procurement


Time

• What is the Scope of Observatory Time– Relative Accuracy

•0.010 Sec over period of 1Sec

– Absolute Accuracy•Observatory to ground to within 0.1 Sec

– Time Adjustment•<= 100 uSec over period of 1 Sec

o HMI requires smooth time adjustment

– Ground time correlation– Time distribution– Time verification

• Who is responsible for Time– The CDH is “Master Clock Keeper”– Reference documents

•464-SYS-REQ-0004•464_CDH-SPEC-0042

• Where is it used in the Subsystem– The CDH maintains, adjusts and distributes

time to instruments, S/C subsystems and ground systems.

• How is time maintained– CDH maintains time using both hardware and

software.– FSW uses the hardware counters, the MET,

the UTCF and the leap seconds to represent one single value – S/C UT.

– Adjustment capabilities include:•Course adjustment of S/C UT•Fine adjustment of S/C UT•Constant adjustment to reduce S/C UT drift with respect to UTC.

– Hardware supports the S/C UT to UTC correlation method that will meet the mission time accuracy requirements.


Ka-Band Telemetry Functional Flow

PrimaryKa XMTR

RedundantKa XMTR

1234

1234

1234

142536

142536

AIA

4 Ports2 Active

HMI

4 Ports2 Active

EVE

4 Ports2 Active

PrimaryKa Comm

RedundantKa Comm

Note: While the arrows do not show it, there is flow control back to the instruments from the Ka Comm Card.

Ka Band Telemetry Allocations (per 464-CDH-ICD-0012)Instrument Slots (1300 Max.) Bandwidth - Mbps

(150 Mbps Max.)HMI 550 55EVE 20 (70) 7AIA 580 (670) 67

Unused (TDM Table) 150 (10) 15 (129)Total (TDM Table) 1300 130

Waveguide switch

to HGA A

to HGA B


HSB Requirements/Specification Overview

REQUIREMENTSTransfer science data from Instr. to Ka Comm• 3 instruments : rates

– AIA : 67 Mbps – EVE : 7 Mbps – HMI : 55 Mbps

• Fault tolerance– Primary/redundant Ka Comm boards, cold-spared– Paired links from each instrument to each Ka Comm– Implement a Link resync method

• Data flow management– Perform data rate quota enforcement via TDM table

• Utilize– Atmel TSS901E (SMCS332)– Atmel T7906E (SMCS116)

SPECIFICATIONSProtocol layers (bottom to top)• Physical

– Spacewire cable/connector compliant

• Signal– Cold-spare LVDS and/or LVDM transmitters (TBR)– Cold-spare LVDS receivers– Data/Strobe

• Character– IEEE 1355 compliant– Spacewire compliant without Time codes

• Exchange– Atmel 1355 compliant

• Packet– IM_PDUs from instruments to Ka Comm– No packets from Ka Comm to instruments– Just null & flow control characters

• Network– Paired point to point IEEE 1355/Spacewire links– No routers


Data Flow Management

• Basic Ka Comm function is a 6:1 mux– Receive IM_PDUs simultaneously on up to 6 input ports– Build CADUs from IM_PDUs– Multiplex CADUs onto 1 output port to RF modulator

• Ka Comm also ensures instrument rates are not exceeded via 1300 slot TDM table

– Each slot holds 3-bit value of IM_PDU port to output next

– Default slots values copied from PROM to RAM after reset

– Each slot’s value can be changed by ground command– 1300 slots provides for data rate limit selection with 0.1

Mbps resolution for 150 Mbps CADU output rate

• HSB performs data rate quota enforcement per Ka Comm TDM table direction

1300 slot TDM table• A-1 : AIA channel 1• A-2 : AIA channel 2• E-1 : EVE channel 1• E-2 : EVE channel 2 (Not used nominally)• H-1 : HMI channel 1• H-2 : HMI channel 2• fill : Fill CADU

Each slot represents 1 CADU• 109 usec per slot

– 16,352 bits @150 Mbps

• 1 IM_PDU per CADU• Slot assignments are configurable

1300 slots provides 0.1 Mbps per slot– CADUs @ 150 Mbps = IM_PDUs @ 130 Mbps– 130 Mbps / 1300 slots = 0.1 Mbps per slot


Testing

• Ka Downlink Card NTGSE, FEPS, Instrument Data

Simulator (Limited functionality for BB)

• S-Comm SDN CDH Test Rack, FEDS, Flight Software

GSE, NTGSE

• Single Board Computer NTGSE, Flight Software GSE, possible

timing interface to CDH Test Rack

• Bulk Memory Card CDH Test Rack (for playback test)

• Ka DC:DC card None

Power Converter Card & Low Power Switch Card CDH test rack (resistive loads for

LPSC)

• CDH Subsystem Testability– The Subsystem is required to verify built to

requirements and validate that function works, but it must also be able to perform functional testing through out development and mitigate hardware, cost & schedule risk.

– The approach that the Subsystem plans to employ to facilitate appropriate testing at all phases of development and to eliminate retro activities. Such as:

•Detailed test procedures that encompass testing at BB, ETU and FLT designs, both at the card and box level.•PDT designs cards from the start to employ testing at various stages of development.•Inter subsystem communication for demands of test at spacecraft I&T stage.•Appropriate test points at the card level for testing.•Sufficient test points at front panel to allow FPGA test/analysis, before opening the box.•Branch level configuration software for card and FPGA designs to mitigate incorrect version loads. This ensures that test protocols are kept updated.


GSE Block DiagramSDO C&DH Test Rack Interfaces

C&DH

Counter Timer

C&DH TR PC (NTGSE based)

FEDS

ASIST

User Interface

S-Band RS422

BC R

BC R

BCR

BCR

1553

RS-232 (GSE)

GPIB

Switch 100Mbps

Instrument DataSimulator

Instrument 1355

6

H/L RS422 3

BC

BC

BC

BC

Digital I/O

Analog O/P

Power Supply0-40Vdc 10A

Digital I/O

Data FromEVE

HMI

AIA

(2) to SBC(2) to SDN(2) to Ka

2

1

RS-422 (GSE & Hardware Commands)

Digital

Digital

Digital 28V (21-35V Pulse 50ms)

82

18

8

16

2

5V TTL

5V(0-5V Pulse 31ms)

FEPKa LVDS 4

GSE/Test 1355 2

Thermistors 8

222222

2

2

2

PotentiometerBox

SwitchedPower

RS-232 2

Power ReadAnalog I/P 16

Analog I/P 20


Status (1/3)

• The CDH Subsystem is presently at the end stages of Breadboard design for most cards and subsystem development.

– Identified RFAs still require closure.– Some Interfaces still require clarification, plan in place and expect satisfactory closeout.– Peer review for CDH Backplane still requires completion– Certain documents still require project review and approval

• When these items are satisfactorily closed out the CDH Subsystem will be ready to proceed to Breadboard layout.

• All Bread Board parts have been selected by Subsystem PDT and confirmed by Parts Team, to have a path to migrate to flight acceptable parts.

• Devices/parts used in CDH designs have been reviewed by parts team and have received initial approval.

• Subsystem will work closely with Parts team to ensure completion of parts testing and screening.

• No parts issues are present to date.– No Breadboard part is delivered later than 6/7/04 (Kit Date)


Status (2/3)

• CDH Subsystem Doc DOC # Status– ICD 464CDH-ICD-0029 Preliminary– REQUIREMENTS 464-CDH-REQ-0038 Submitted for formal

review with CCR– GSE REQUIREMENTS 464-CDH-REQ-0030 Preliminary– Development Plan 464-CDH-PLAN-0028 Preliminary– HSB ICD 464-CDH-ICD-0012 Preliminary

• Single Board Computer (SBC)– SBC SOW 464-CDH-LEGL-0008 Baselined

– SBC Specification 464-CDH-SPEC-0012 Baselined

• cPCI Backplane– cPCI ICD (J1 & J2) 464-CDH-ICD-0032 Review – cPCI REQ 464-CDH-REQ-0044 Review


Status (3/3)

• Status to date– Boards designs have had Peer level Reviews– Subsystem has had Subsystem level PDR– Board circuit designs for Layout are complete

pending RFA (Peer and PDR) completion.– Major RFAs still in an open status are:

•C&DH system: RFA 15 MDM connector & Harnessing Issues •Ka (and HSB):

oRFA's 8 & 34 Atmel Radiation concerns, oRFA's 23,14,33,5,12 Resync issues (effect on BER)

•SBC: RFA's 4,25, 43 & 52 EEprom boot area lockout (may require change to RFP)•DC DC Card: RFA 17 & 31 Backplane capacitance and effect on in-rush •Comm Card: RFA 12- 3.3V differential signal vs. 5V for 422 •BMC: RFA 18 (radiation susceptibility of SDRAM not known)

CDH Subsystem PDR RFAsStatus

Tota

l

Resp

onse

Pro

vide

d

Ope

n/Re

view

Clos

ed

57 57 35 22100% 100% 61% 39%

Subsystem 25 25 14 11High Speed Bus (HSB) 6 6 3 3Single Board Computer (SBC) 4 4 2 2S_Comm ASD 4 4 2 2DCDC 4 4 1 3Bulk Memory Card (BMC) 4 4 4 0Ka 6 6 5 1BKPLN 4 4 4 0PSE ASD - - - -DL ASIC - - - -

Subsystem Component Comments

CDH Card Level Peer Review RFAsStatus

Tota

l

Resp

onse

Pro

vide

d

Ope

n/Re

view

Clos

ed

116 116 33 83100% 100% 28% 72%

S_Comm ASD 20 20 4 16DCDC 20 20 4 16Bulk Memory Card (BMC) 25 25 10 15Ka 13 13 6 7BKPLN - - - - Peer Review PendingPSE ASD 20 20 8 12DL ASIC 18 18 1 17

Subsystem Component Comments


Development Flow

Flight Dev.Phase

ETU Dev.Phase

Design Fab Test

Concept/Reqs. Review Design

Peer Review

Latest S/W Load & GSE

Design Fab Test

Updated S/W Load

Design Peer Review

BB mods. folded into ETU design

Design Fab Test

Systems Eng. Pre-Fab Review

ETU mods. Folded into Flight design Updated S/W Load

(sufficient to test/verify all H/W interfaces & functions)

BB Dev.Phase

PDR

Systems Eng.Pre-Fab Review

Thermal Test

Environmental TestPhase EMI/EMC Vibration Thermal Vac

EMI/EMCResults Review

Deliver toSpacecraft

VibrationResults Review

Thermal VacResults Review

CDR

PhaseB

PhaseC

PhaseD


C&DH Schedule

Q4

CY 2003 CY 2004 CY 2005 CY 2006 CY 2007Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

CY 2008

MISSION MILESTONES

C&DH Milestones

Backplane (cPCI)

Subsystem & Element

C&DH Module

PDR1/8/04

CDR10/04

Ka-Band CardS-Band CardDC/DC CardSDN BackplaneBulk Memory

PSE SDNBB

Cards

ETUFLT

Environmental Test

Spacecraft I&T

ICRSRR/SCR

PDR

5/04

CR CDR

2/05

PSR

2/088/03LAUNCH

4/08

PER

5/074/8

Launch1 2 3 4

S-Band Comm SDN 1 = Spacecraft Integration= Schedule Reserve

2 = Instrument Integration3 = Environmental Testing4 = Launch Site Operations

BB

BB

BB

ETU

ETU

ETU

FLT

FLT

FLT

SBC

Assembly, Test & Closeout

Award

3/04


Conclusion - Program Assessment

• The CDH Subsystem has a viable implementation plan.• The Requirements and Documentation are in place and pending review

completion• The CDH Subsystem is adequately staffed and has sufficient resources to

successfully proceed.• Major milestones have been worked into Subsystem schedule and adequate

“slack” before delivery to spacecraft has been integrated.• Issues have been clearly itemized and identified.


SDO CDH MISSION PDRBACKUP SLIDES


Processing Element Resets

Reset Action BC/RT Register SDRAM FSW IMAGE Register

Power-On (POR) Resets All on BMC and SBC

Cleared (RT mode)

Initialize to zeros Cleared (EEPROM Image)

HW Cmd #3 Resets All on BMC and SBC

Cleared (RT mode)

Initialize to zeros Cleared (EEPROM Image)

HW Cmd #5 Resets SBC and partial BMC

Set (BC mode) No Change No Change from last state

S/W Commanded Cold Start

(via WD timer?)

SBC: Vendor specificBMC: partial

No Change from last state

No Change No Change from last state

Watchdog Timer Reset

SBC: Vendor specific.BMC partial



S/W Commanded Warm Start

Does not reset hardware. Restarts FSW



HW Cmd #TBD Resets SBC and partial BMC


No Change Set (PROM Image)

Note: BMC functions reset during “partial” reset: 1. cPCI target FPGA, 2. MIL-STD-1553 protocol chip, 3. SRAM/Sync Serial Port (SSP)/1553 Control FPGA,

= desirement??


Atmel 1355 Usage

AIA Instrument Electronics200 Mbps Link Rate

< 160 Mbps Data Rate1355 Type: 1-port

Mode: ProtocolManaged: Remotely

Active Qty: 4Inactive Qty: 0

Redundancy: None

AIA Interface Electronics

1355 Type: 1-portMode: Protocol

Managed: LocallyActive Qty: 4

Inactive Qty: 0Redundancy: None

Ka Comm

1355 Type: 3-portMode: TransparentManaged: Locally


Redundancy: per HSB ICD




HMI Instrument Electronics


Managed: RemotelyActive Qty: 2


HMI Interface Electronics


Managed: LocallyActive Qty: 2





EVE Instrument Electronics

not 1355

EVE Interface Electronics

not 1355




10 Mbps Link Rate0 Mbps Data Rate

NoteData Rate does not include

1335 control characters(EOP1, EOP2, FCT, NULL)

200 Mbps Link Rate< 160 Mbps Data Rate


100 Mbps Link Rate< 55 Mbps Data Rate


10 M

bps L

ink R

ate

2 or 7

(TBR) M

bps D

ata R

ate

10 M

bps L

ink R

ate

0 Mbp

s Data

Rate

100 Mbps Link Rate

< 65 Mbps Data Rate

10 Mbps Link Rate

0 Mbps Data Rate


HSB IM_PDU Context in CCSDSIM_PDU is VCDU Insert Zone + M_PDU

IM_PDU Header

IM_PDUID(6)

IM_PDU Counter(42)

M_PDU Header

Spare(5)

First Header Pointer(11)

M_PDU Packet Zone

Source Packet Data1 or more packets

1768 Octets

Sync Marker

1ACFFC1D(32)

VCDU (1784 Octets) RS Check Symbols

Interleave Depth = 8256 Octets

(2,048)

CADU(Interleave 8, 2044 Octets, 16352 bits)

VCDU Primary Header

VersionAOS=1

(2)

VCDU Identifier

S/C ID(8)

VC ID(6)

VCDUCounter

(24)

ReplayFlagRT=0

(1)

Spare(7)

IM_PDU1,776 Octets

(14,208)

VCDUTrailerCRC(16)

IM_PDU

IM_PDU Header

IM_PDUID(6)

IM_PDU Counter(42)

M_PDU Header

Spare(5)

First Header Pointer(11)

M_PDU Packet Zone

Source Packet Data1 or more packets

1768 Octets

EOP

4 bitsInserted andRemoved byAtmel chips

1,776 Octets1355 compliant encoded to 17,760 bits

(10 bit bytes)

IM_PDU(Based on CCSDS VCDU Insert Zone & M_PDU Packet)

RF Ka

Ka Instr


Functional Signal Distribution

DGNDAGND

3.3V5V

2.5V+/-15V

PAT

Not

Used

Not

Used

DGNDAATPAT

DGND

TBD

DGNDAATPAT

DGNDPAT

DGNDPAT

J5

NotUsed

NotUsed

DGND

DGND TBD

DGND

DGND

DGND J4

NotUsed

NotUsed

DGND TBD

2.5V3.3V,5VDGND

2.5V3.3V,5VDGND

J3

DGND,AGND2.5V,

+/-15VPATcPCI

Signals

DGNDAGND2.5V

+/-15VPATcPCI

Signals

DGNDAGND+/-15V

DGNDcPCI

Signals TBD

DGND

DGND

DGND

J2

3.3V5V

DGNDcPCI

Signals

3.3V5V

DGNDcPCI

Signals

3.3V5V

DGND

3.3V,5VDGNDcPCI

Signals TBD

3.3V5V

DGNDcPCI

Signals

3.3V5V

DGND

3.3V5V

DGND

J1

PCC

SDN

LPSC

SCOMM

SBC

BMC

DCDC

KACOMM

DCDC

AirBorn Connector

PAT = Passive Analog TLM AAT = Active Analog TLMAGND = Analog GroundDGND = Digital Ground

DGND DGND

SDO CDH Subsystem Mission PDR

Documents

Transcript of SDO CDH Subsystem Mission PDR