Scientific CCD characterisation at Universidad Complutense LICA Laboratory
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Scientific CCD characterisation at Universidad Complutense LICA Laboratory We are developing a new CCD controller intended for high time- resolution observations using both conventional and electron- multiplying CCDs. We have tried to incorporate as many features as possible into our design, such as an integrated data-acquisition PC, a 1GB image store, a microcontroller-based temperature servo able to directly power Peltier coolers, a shutter controller, a high-voltage clock generator for EMCCDs and an integrated power supply. Read-out sequencing and ADC control is performed using a Xilinx Spartan-3 FPGA. This allows high-speed data acquisition and buffering across several parallel channels. The FPGA communicates with the DAS PC over a USB link, the PC then links to the outside world via gigabit-Ethernet. Our prototype contains just two data acquisition channels that can run at up to 3Mpix/s but we intend to expand this to eight 10Mpix/s channels for our final design. We also intend to integrate the functions of the DAS PC and FPGA sequencer into a single device such as the Xilinx Zynq processor. This will also implement a server allowing users to operate the controller via a series of web pages. We have recently completed the prototype hardware for this controller and are now looking for partners to allow us to continue the development. Astronomical Detectors Dr. Simon Tulloch Dr. Jure www.qucam.com [email protected] +34 663604482 QUCAM “Dragonfly” : A new detector controller for high time-resolution observations Analogue board Digital interface board Controller backplane Digital interface mounted on base of the analogue board Spartan-3E FPGA module implementing clock sequencer and ADC/DAC interface 32-channel 14-bit DACs Two channels 16-bit 6MHz ADCs 40W Power supply 1.6GHz Intel Atom based Linux PC 2GB RAM, 8GB Flash disc. EMCCD-based test camera attached to controller The backplane not only mounts the DAS PC and the power-supply but also contains a shutter driver, power-conditioning circuitry, a high-voltage generator, a programmable temperature controller and a Peltier driver. The test camera is cooled by an 8W 2-stage Peltier cooler. A specially machined detector PCB is used to allow cooling to 50 o C below ambient. The camera is hermetically sealed but operated at ambient pressure. It contains an E2V CCD97 which allows us to evaluate controller performance with both its conventional low noise output and also its high-speed electron- multiplying output. Underside of detector head-board PCB E2V CCD97 2-stage Peltier Video preamplifiers window Gold-plated centre section CCD Thermal-isolation slots bridged by Nichrome wire. The head-board video preamplifiers produce a differential output i.e. consisting of two versions of the video signal of opposing phase. When received in the controller, these signals are then recombined in a way that removes any common-mode noise. This suppresses pattern-noise in the images. An FPGA is a programable logic device whose hardware can be configured to implement any digital function, from a simple ADC interface to a complete CPU. The FPGA logic is described using ether the VHDL or Verilog languages. Data is acquired and buffered from the ADCs by the FPGA module. This is then transmitted to the backplane-mounted PC via a USB2 interface. Data can be stored locally within the controller, in Flash or SSD memory, or sent over a Gigabit Ethernet interface. The readout waveforms and other FPGA parameters are loaded into the FPGA through the USB port. The waveforms consist of clocking units which are combined and iterated through a sequencer. Each clocking unit defines a meaningful action of the waveform generator, such as parallel image shift, serial shift, etc. The clocking unit can define up to 64 digital signals within the FPGA, half of which are available to the CCD clocks and the rest are used for internal FPGA controls, such as triggering the ADC conversion. 24MB/s USB interface from FPGA board to PC mounted on backplane Backpla ne CCD Clock generators EMCCD HV clock Voltage monitor Bias generators Dual-slope video processor Clamp and sample video processor EMCCDs are able to give very high pixel rates with very low noise. They are easily capable of detecting single photons at multi-MHz pixel rates. controller has been built to evaluate our concept of an integrated controller/DAS PC combiation. It will vestigate potential noise issues, gain experience with FPGA programming and serve as a test bed for high- . We also hope to use the controller for GRB observations at the Črni Vrh observatory. Voltage regulators “stay-alive” power reserve for orderly shutdown in event of power failure. VP1-8=Video processor analogue circuitry VP1 VP2 VP3 VP4 VP5 VP6 VP7 VP8 Bias circuitry Bias circuitry Clock circuitry Clock circuitry Clock circuitry Voltage Regulator Voltage monitor micro-controller 12-bit 16 channel DAC Front-panel connectors to CCD head Backplane 12-bit 16 channel DAC PSU Voltage regulators High Time Resolution Optical Astrophysics, Royal Astronomical Society, London April 12, 2013 Analogue board Backplane connector Flex-ribbons Front-panel Mil-style connector Temperature controller Top view of future controller Side view of future controller Digital board on lower side Analogue board “CCD engine” digital board. Mounted below the analogue board Our next controller will have up to 8 video processor channels and a target pixel rate of 10MHz/Channe acquisition PC will be incorporated into a “system-on-a-chip” (SOC ) device such as the Xilinx Zync. conventional CCDs will be supported. The same two-level board geometry will probably be used, with a s analogue board implementing clock and bias generation with a smaller mezzanine-mounted digital board the SOC and data converters. CCD “Engine” Boot Media Sequencer outputs (CCD clock outputs) 16 bit ADCs > 20MHz with 8-bit parallel interface Ethernet interface USB2 Low-speed DAC interface Power 2GB RAM module socketed on under-side Clock Gen. PHY FPGA heatsink SOC SD card ADC ADC ADC ADC Differential analogue inputs 1 2 3 4 ADC ADC ADC ADC Differential analogue inputs 8 7 6 5 Jam-nut connector soldered directly onto back of the internal PCB. Peltier power/temperature servo connector. Inter-PCB connectors The Xilinx Zynq is a powerful example of an SOC device. It contains built-in memory controllers , ethernet and USB interfaces and a huge number of user I/O pins that can be dedicated to CCD clocks and the control of video processors. SOC or “system on a chip” devices are a logical choice for a high speed CCD controller.They conisist of one or more CPUs surrounded by a matrix of programmable logic. This logic can be flexibly configured to implement the readout sequencer and ADC/DAC interfaces whilst leaving the CPU to implement the high- level software and control-GUI web servers. Peltier access hole The controller will provide a high-level communication interface with the observing system. Because of the fully capable Linux computer serving as a front end to the clocking circuit, the user programs do not need to worry about any hardware-specific details of the electronics. The default communication interface will be provided provided by CORBA in addition to the HTTP interface. The front-end computer contains a web server which serves the pages for camera- status monitoring and the setting of the working parameters through a customised GUI. The user does not need to know any implementation details of the FPGA design. Instead the clocking units are defined using a custom controller definition language which allows setting of the clocking levels and other analog outputs, definition of clocking units and definition of the readout sequences which define the readout waveform and data readout. The definition language is very minimalistic so it is easy learn and understand. Before uploading the clocking units to the controller they can be simulated and verified by a waveform viewer. The new controller therefore provides a level of abstraction which shields the CCD engineer from learning FPGA programming yet provides full control over the clocking sequences and the sensor configuration. Another abstraction exists at the application level where standard communication protocols are used to command the controller and retrieve images. It is hoped that this approach will simplify usage of the CCD yet preserve full flexibility for the interfacing and tuning of different imaging sensors. The CCD engine could find many additional applications in the field of high-speed data acquisition. It could be piggyback mounted onto other analogue boards, for example one optimised for the control of CMOS image sensors. Development of this engine will comprise the major part of our proposed future controller. Waveform definition file Waveform viewer tool Download configuration/waveform file into controller HV clock Prototype Future Parameter controller controller Video channels 2 8 Pixel rate /channel 3 MHz 10MHz CCD clocks 12 24 CCD biases 12 20 Maximum clock rate 3 MHz 10 MHz EMCCD compatible ? yes yes Integrated DAS ? yes yes Integrated temperature controller? yes yes Controller performance parameters
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Transcript of Scientific CCD characterisation at Universidad Complutense LICA Laboratory
Scientific CCD characterisation at Universidad Complutense LICA Laboratory
We are developing a new CCD controller intended for high time-resolution observations using both conventional and electron-multiplying CCDs. We have tried to incorporate as many features as possible into our design, such as an integrated data-acquisition PC, a 1GB image store, a microcontroller-based temperature servo able to directly power Peltier coolers, a shutter controller, a high-voltage clock generator for EMCCDs and an integrated power supply. Read-out sequencing and ADC control is performed using a Xilinx Spartan-3 FPGA. This allows high-speed data acquisition and buffering across several parallel channels.
The FPGA communicates with the DAS PC over a USB link, the PC then links to the outside world via gigabit-Ethernet. Our prototype contains just two data acquisition channels that can run at up to 3Mpix/s but we intend to expand this to eight 10Mpix/s channels for our final design. We also intend to integrate the functions of the DAS PC and FPGA sequencer into a single device such as the Xilinx Zynq processor. This will also implement a server allowing users to operate the controller via a series of web pages. We have recently completed the prototype hardware for this controller and are now looking for partners to allow us to continue the development.
Astronomical DetectorsDr. Simon TullochDr. Jure Skvarč
www.qucam.com
+34 663604482
QUCAM
“Dragonfly” : A new detector controller for high time-resolution observations
Analogue board Digital interface board
Controller backplane
Digital interface mounted on baseof the analogue board
Spartan-3E FPGA module implementingclock sequencer and ADC/DAC interface
32-channel14-bit DACs
Two channels16-bit 6MHz ADCs
40W Power supply
1.6GHz Intel Atom based Linux PC2GB RAM, 8GB Flash disc.
EMCCD-based test camera attached to controller
The backplane not only mounts the DAS PC and the power-supply but also contains a shutter driver, power-conditioning circuitry, a high-voltage generator, a programmable temperature controller and a Peltier driver.
The test camera is cooled by an 8W 2-stage Peltier cooler. A specially machined detector PCB is used to allow cooling to 50oC below ambient. The camera is hermetically sealed but operated at ambient pressure. It contains an E2V CCD97 which allows us to evaluate controller performancewith both its conventional low noise output and also its high-speed electron-multiplying output.
Underside of detector head-board PCB
E2V CCD972-stage Peltier
Video preamplifiers
window
Gold-plated centresection
CCD
Thermal-isolationslots bridged byNichrome wire.
The head-board video preamplifiers produce a differential output i.e. consisting of two versions of the video signal of opposing phase. When received in the controller, these signals are then recombined in a way that removes any common-mode noise. This suppresses pattern-noise in the images.
An FPGA is a programable logic device whose hardware can be configured to implement any digital function, from a simple ADC interface to a complete CPU. The FPGA logic is described using ether the VHDL or Verilog languages.
Data is acquired and buffered from the ADCs by the FPGA module. This is then transmitted to the backplane-mounted PC via a USB2 interface.
Data can be stored locally within the controller, in Flash or SSD memory, or sent over a Gigabit Ethernet interface.
The readout waveforms and other FPGA parameters are loaded into the FPGA through the USB port. The waveforms consist of clocking units which are combined and iterated through a sequencer. Each clocking unit defines a meaningful action of the waveform generator, such as parallel image shift, serial shift, etc. The clocking unit can defineup to 64 digital signals within the FPGA, half of which are available to the CCD clocks and the rest are used for internal FPGA controls, such as triggering the ADC conversion.
24MB/s USBinterface fromFPGA board to PCmounted on backplane
Backplane
CCD
Clock generators
EMCCD HVclock
Voltage monitor
Bias generators
Dual-slope video processor
Clamp and sample video processor
EMCCDs are able to give very highpixel rates with very low noise. They are easily capable of detecting single photons at multi-MHz pixel rates.
The prototype controller has been built to evaluate our concept of an integrated controller/DAS PC combiation. It will allow us to investigate potential noise issues, gain experience with FPGA programming and serve as a test bed for high-level sofware. We also hope to use the controller for GRB observations at the Črni Vrh observatory.
Voltage regulators
“stay-alive” powerreserve for orderlyshutdown in eventof power failure.
VP1-8=Video processor analogue circuitry
VP1
VP2
VP3
VP4
VP5
VP6
VP7
VP8
Bias circuitry Bias circuitry
Cloc
k ci
rcui
try
Cloc
k ci
rcui
try
Cloc
k ci
rcui
try
Voltage Regulator
Volta
ge m
onito
rm
icro
-con
trol
ler
12-bit16 channel DAC
Front-panelconnectors to CCD head
Backplane
12-bit16 channel DAC
PSU Voltage regulators
High Time Resolution Optical Astrophysics, Royal Astronomical Society, London April 12, 2013
Analogue board Backplane connector
Flex-ribbons
Front-panelMil-styleconnector
Temperature controller
Top view of future controller
Side view of future controller
Digital board on lower side
Analogue board
“CCD engine”digital board.Mounted belowthe analogue board
Our next controller will have up to 8 video processor channels and a target pixel rate of 10MHz/Channel. The data acquisition PC will be incorporated into a “system-on-a-chip” (SOC ) device such as the Xilinx Zync. Both EMCCD and conventional CCDs will be supported. The same two-level board geometry will probably be used, with a single large analogue board implementing clock and bias generation with a smaller mezzanine-mounted digital board containing the SOC and data converters.
CCD “Engine”Boot Media
Sequencer outputs(CCD clock outputs)
16 bit ADCs > 20MHzwith 8-bit
parallel interface Ethernet interfaceUSB2
Low-speedDAC interface
Power
2GB RAM module socketed on under-side
ClockGen.
PHY
FPGA
hea
tsin
k
SOC
SD cardADC
ADC
ADC
ADCDiffe
renti
al a
nalo
gue
inpu
ts 1
2
3
4
ADC
ADC
ADC
ADC Diffe
renti
al a
nalo
gue
inpu
ts8
7
6
5
Jam-nut connectorsoldered directly ontoback of the internal PCB.
Peltier power/temperatureservo connector.
Inter-PCB connectors
The Xilinx Zynq is a powerful example of an SOC device. It contains built-in memory controllers , ethernet and USB interfaces and a huge number of user I/O pins that can be dedicated to CCD clocks and the control of video processors.
SOC or “system on a chip”devices are a logical choice for a high speed CCD controller.They conisist of one or more CPUs surrounded by a matrix of programmable logic. This logic can be flexibly configured to implement the readout sequencer and ADC/DAC interfaces whilst leaving the CPU to implement the high-level software and control-GUI web servers.
Peltier access hole
The controller will provide a high-level communication interface with the observing system. Because of the fully capable Linux computer serving as a front end to the clocking circuit, the user programs do not need to worry about any hardware-specific details of the electronics. The default communication interface will be provided provided by CORBA in addition to the HTTP interface. The front-end computer contains a web server which serves the pages for camera-status monitoring and the setting of the working parameters through a customised GUI.
The user does not need to know any implementation details of the FPGA design. Instead the clocking units are defined using a custom controller definition language which allows setting of the clocking levels and other analog outputs, definition of clocking units and definition of the readout sequences which define the readout waveform and data readout. The definition language is very minimalistic so it is easy learn and understand. Before uploading the clocking units to the controller they can be simulated and verified by a waveform viewer.
The new controller therefore provides a level of abstraction which shields the CCD engineer from learning FPGA programming yet provides full control over the clocking sequences and the sensor configuration. Another abstraction exists at the application level where standard communication protocols are used to command the controller and retrieve images. It is hoped that this approach will simplify usage of the CCD yet preserve full flexibility for the interfacing and tuning of different imaging sensors.
The CCD engine could find many additional applications in the field of high-speed data acquisition. It could be piggyback mounted onto other analogue boards, for example one optimised for the control of CMOS image sensors. Development of this engine will comprise the major part of our proposed future controller.
Waveform definition file Waveform viewer tool
Download configuration/waveform file into controller
HV clock
Prototype Future
Parameter controller controller
Video channels 2 8
Pixel rate /channel 3 MHz 10MHz
CCD clocks 12 24
CCD biases 12 20
Maximum clock rate 3 MHz 10 MHz
EMCCD compatible ? yes yes
Integrated DAS ? yes yes
Integrated temperature controller?
yes yes
Controller performance parameters
