scheme-acer-aspire-as5220-5520-7520-7220-icw50 la-3581p

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A A B B C C D D E E 1 1 2 2 3 3 4 4 Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date ICW50 / ICY70 LA-3581P Cover Sheet Custom 1 42 Friday, April 20, 2007 2006/08/18 2007/8/18 1.0 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date ICW50 / ICY70 LA-3581P Cover Sheet Custom 1 42 Friday, April 20, 2007 2006/08/18 2007/8/18 1.0 Compal Electronics, Inc. Title Size Document Number Rev Date: Sheet of Security Classification Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Issued Date Deciphered Date ICW50 / ICY70 LA-3581P Cover Sheet Custom 1 42 Friday, April 20, 2007 2006/08/18 2007/8/18 1.0 Compal Electronics, Inc. ICW50 Schematics Document AMD Turion/Sempron + Nvidia MCP67-MV Rev:1.0 Compal Confidential 2007 / 04 / 20 FOR Pre-MP

Transcript of scheme-acer-aspire-as5220-5520-7520-7220-icw50 la-3581p

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Compal ConfidentialICW50 Schematics DocumentAMD Turion/Sempron + Nvidia MCP67-MV 2007 / 04 / 20 Rev:1.0 FOR Pre-MP

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Security ClassificationIssued Date

Compal Secret Data2006/08/18Deciphered Date

Compal Electronics, Inc.

2007/8/18

Title

Cover SheetSize Document Number Custom ICW50 / ICY70 Date:

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C D

LA-3581PSheetE

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Compal confidentialProject Code: ICW50 File Name : LA-3581PD

Thermal Sensor ADM1032ARMpage 6

AMD Turion/Sempron CPU Socket S1 638P HT LINK200-800MHz

DDRII

533/667/800

DDRII-SO-DIMM X2page 08,09

page 4,5,6,7

Dual ChannelD

DVI-D Conn.page 20

LCD Conn.page 20

CRT & TV-outpage 19

LVDS DVI LVDS PCI-Express

Nvidia MCP67-MV836 BGAUSB 2.0 BUS HD Audio IDE BUS SATA BUS

USB conn x4page 25,26

Bluetooth Conn page

29

CMOS Camera page

20

3.3V 24.576MHz/48Mhz 3.3V ATA-100

MXM II VGA/Bpage 18C

PCI-Express PCI BUS New Card Socket MINI Card x2WLAN, TV-Tuner

port 1

CDROM Conn. 21 page

MDC 1.5 Conn 29 page

HDA CodecALC268page 31C

PHY(GbE)RTL8211Bpage 22

IDSEL:AD20 (PIRQE#, GNT#0, REQ#0)

3.3V 33 MHz page 10,11,12,13,14,15,16,17

S-ATA HDD Conn. page 21

Audio AMPpage 32

Card ReaderRICOH R5C833

RJ45page 22

page 23

LPC BUS

Phone Jack x3page 32

B

1394 Conn.page 23

6 in 1 socketpage 24

ENE KB926page 27,28

B

Power On/Off CKT / LID switch / Power OK CKTpage 30

Touch Pad

page 29

Int.KBDpage 29

DC/DC Interface CKT.page 33

CIR/LEDpage 29

RTC CKT.page 16

EC I/O Bufferpage 29

BIOSpage 29

Power Circuit DC/DCpage 35~41

CIRpage 30A A

Security Classification Issued Date

Compal Secret Data2006/08/18Deciphered Date

2007/8/18

Title

BLOCK DIAGRAMSize Document Number Custom ICW50 / ICY70 Date:

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

LA-3581PSheet1

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STATE

SIGNAL

SLP_S1# SLP_S3# SLP_S5# HIGH LOW LOW LOW LOW HIGH HIGH LOW LOW LOW HIGH HIGH HIGH HIGH LOW

+VALW ON ON ON ON ON

+V ON ON ON OFF OFF

+VS ON ON OFF OFF OFF

Clock ON LOW OFFD

Voltage RailsPower Plane VIND

Full ONDescription Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU 0.9V switched power rail for DDR terminator 1.5V switched power rail 1.2V always on power rail 1.2V switched power rail 1.2V switched power rail 1.8V power rail for DDR 1.8V switched power rail 2.5V switched power rail 3.3V always on power rail 3.3V switched power rail 5V always on power rail 5V switched power rail VSB always on power rail RTC power S1 N/A N/A ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON S3 N/A N/A OFF ON OFF ON OFF OFF ON OFF OFF ON OFF ON OFF ON ON S5 N/A N/A OFF OFF OFF ON* OFF OFF OFF OFF OFF ON* OFF ON* OFF ON* ON

S1(Power On Suspend) S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF)

B+ +CPU_CORE +0.9V +1.5VS +1.2VALW +1.2VS +1.2V_HT +1.8V +1.8VS +2.5VS +3VALW/+3V/+3VAUX +3VS +5VALW +5VS +VSB

OFF OFF

Board ID / SKU ID Table for AD channelVcc Ra/Rc/ReBoard ID

C

+RTCVCC

0 1 2 3 4 5 6 7

3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC

V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V

V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V

V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V

C

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

BOARD ID TableBoard ID 0 1 2 3 4 5 6 7 PCB Revision UMA (0V) DISCRETE (3.3V)

BTO Option TableBTO Item BOM Structure DIP CAP & RTC 45@ UMA UMA@ VGA VGA@ UMA & TV-OUT UMA&TV@ 2 SATA HDD SATA2@ CAMERA CMOS@ BLUETOOTH BT@ MINI CARD 1(TV) MINI1@ MINI CARD 2(WLAN) MINI2@ NEW CARD EXPRESS@ TV-OUT TV@ DVI DVI@ 1394 1394@ CARD READER 5IN1@ HT Debug Port HT@

External PCI DevicesDevice 1394 IDSEL#AD20

REQ#/GNT#0

Interrupts PIRQE

B

B

EC SM Bus1 addressDeviceSmart Battery

EC SM Bus2 addressDeviceADM1032

SKU ID TableSKU ID 0 1 2 3 4 5 6 7 SKU B - PHASE C - PHASE

Address0001 011X b

Address1001 100X b

MCP67 SM Bus addressDeviceDDR DIMM0 DDR DIMM2A

Address1001 000Xb 1001 001XbA

Security Classification Issued Date

Compal Secret Data2006/08/18Deciphered Date

2007/8/18

Title

TABLE OF CONTENTSSize Document Number Custom ICW50 / ICY70 Date:

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

LA-3581PSheet1

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PROCESSOR HYPERTRANSPORT INTERFACED

VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

D

+1.2V_HT JP22A D4 D3 D2 D1 H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H_CADIN9 H_CADIP8 H_CADIN8 H_CADIP7 H_CADIN7 H_CADIP6 H_CADIN6 H_CADIP5 H_CADIN5 H_CADIP4 H_CADIN4 H_CADIP3 H_CADIN3 H_CADIP2 H_CADIN2 H_CADIP1 H_CADIN1 H_CADIP0 H_CADIN0 H_CLKIP1 H_CLKIN1 H_CLKIP0 H_CLKIN0 H_CTLIP1 H_CTLIN1 H_CTLIP0 H_CTLIN0 N5 P5 M3 M4 L5 M5 K3 K4 H3 H4 G5 H5 F3 F4 E5 F5 N3 N2 L1 M1 L3 L2 J1 K1 G1 H1 G3 G2 E1 F1 E3 E2 J5 K5 J3 J2 P3 P4 N1 P1 VLDT_A3 VLDT_A2 VLDT_A1 VLDT_A0 L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0 L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKIN_H0 L0_CLKIN_L0 L0_CTLIN_H1 L0_CTLIN_L1 VLDT_B3 VLDT_B2 VLDT_B1 VLDT_B0 L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1 AE5 AE4 AE3 AE2 T4 T3 V5 U5 V4 V3 Y5 W5 AB5 AA5 AB4 AB3 AD5 AC5 AD4 AD3 T1 R1 U2 U3 V1 U1 W2 W3 AA2 AA3 AB1 AA1 AC2 AC3 AD1 AC1 Y4 Y3 Y1 W1 T5 R5 R2 R3 H_CTLOP0 H_CTLON0 H_CTLOP0 (10) H_CTLON0 (10) 1 2 C533 4.7U_0805_10V4Z

FAN Conn+5VS 1 H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8 H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0 H_CLKOP1 H_CLKON1 H_CLKOP0 H_CLKON0 (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10)

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HTT Interface

(10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10) (10)

H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H_CADIN9 H_CADIP8 H_CADIN8 H_CADIP7 H_CADIN7 H_CADIP6 H_CADIN6 H_CADIP5 H_CADIN5 H_CADIP4 H_CADIN4 H_CADIP3 H_CADIN3 H_CADIP2 H_CADIN2 H_CADIP1 H_CADIN1 H_CADIP0 H_CADIN0 H_CLKIP1 H_CLKIN1 H_CLKIP0 H_CLKIN0 2 51_0402_1% 2 51_0402_1%

H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8 H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0 H_CLKOP1 H_CLKON1 H_CLKOP0 H_CLKON0

D20 1SS355_SOD323-2

W=40mils2 +VCC_FAN1 FAN1 1 D21 BAS16_SOT23-3 1 C509 2 1000P_0402_50V7K JP16 1 2 3 1 C52 1000P_0402_50V7K ACES_85205-03001C

+3VS 1

1 C510

2 10U_0805_10V4Z

(27,28) FAN_SPEED1

2

2

R88 10K_0402_5%

Update Footprint

2

U11 +5VS +VCC_FAN1 (27,28) EN_DFAN1 1 2 3 4 VEN VIN VO VSET GND GND GND GND 8 7 6 5

+1.2V_HT R143 1 R142 1

(10) (10) (10) (10)

EN_DFAN1 1 C310 10U_0805_10V4Z

G993P1UF_SOP8

2

(10) H_CTLIP0 (10) H_CTLIN0B

L0_CTLIN_H0 L0_CTLOUT_H0 L0_CTLIN_L0 L0_CTLOUT_L0 FOX_PZ63823-284S-41FAthlon 64 S1 Processor Socket

FAN1 ConnB

+1.2V_HT

C541 4.7U_0805_10V4Z 1 1

C536 0.22U_0402_10V4Z 1 1

C539 180P_0402_50V8J 1

1

2 C542 4.7U_0805_10V4Z

2

2 C540 0.22U_0402_10V4Z

2

2 2 C538 180P_0402_50V8J

LAYOUT: Place bypass cap on topside of boardNEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY TO OTHER HT POWER PINS PLACE CLOSE TO VLDT0 POWER PINS

A

A

Security Classification Issued Date

Compal Secret Data2006/08/18Deciphered Date

2007/8/18

Title

AMD CPU HT I/FSize Document Number Custom ICW50 / ICY70 Date:

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

LA-3581PSheet1

Rev 1.0 4 of 42

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Processor DDR2 Memory InterfaceVDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE(9) DDR_B_D[63..0] DDR_B_D63 DDR_B_D62 DDR_B_D61 DDR_B_D60 DDR_B_D59 DDR_B_D58 DDR_B_D57 DDR_B_D56 DDR_B_D55 DDR_B_D54 DDR_B_D53 DDR_B_D52 DDR_B_D51 DDR_B_D50 DDR_B_D49 DDR_B_D48 DDR_B_D47 DDR_B_D46 DDR_B_D45 DDR_B_D44 DDR_B_D43 DDR_B_D42 DDR_B_D41 DDR_B_D40 DDR_B_D39 DDR_B_D38 DDR_B_D37 DDR_B_D36 DDR_B_D35 DDR_B_D34 DDR_B_D33 DDR_B_D32 DDR_B_D31 DDR_B_D30 DDR_B_D29 DDR_B_D28 DDR_B_D27 DDR_B_D26 DDR_B_D25 DDR_B_D24 DDR_B_D23 DDR_B_D22 DDR_B_D21 DDR_B_D20 DDR_B_D19 DDR_B_D18 DDR_B_D17 DDR_B_D16 DDR_B_D15 DDR_B_D14 DDR_B_D13 DDR_B_D12 DDR_B_D11 DDR_B_D10 DDR_B_D9 DDR_B_D8 DDR_B_D7 DDR_B_D6 DDR_B_D5 DDR_B_D4 DDR_B_D3 DDR_B_D2 DDR_B_D1 DDR_B_D0 DDR_B_DM7 DDR_B_DM6 DDR_B_DM5 DDR_B_DM4 DDR_B_DM3 DDR_B_DM2 DDR_B_DM1 DDR_B_DM0 DDR_B_DQS7 DDR_B_DQS#7 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS0 DDR_B_DQS#0 AD11 AF11 AF14 AE14 Y11 AB11 AC12 AF13 AF15 AF16 AC18 AF19 AD14 AC14 AE18 AD18 AD20 AC20 AF23 AF24 AF20 AE20 AD22 AC22 AE25 AD26 AA25 AA26 AE24 AD24 AA23 AA24 G24 G23 D26 C26 G26 G25 E24 E23 C24 B24 C20 B20 C25 D24 A21 D20 D18 C18 D14 C14 A20 A19 A16 A15 A13 D12 E11 G11 B14 A14 A11 C11 AD12 AC16 AE22 AB26 E25 A22 B16 A12 AF12 AE12 AE16 AD16 AF21 AF22 AC25 AC26 F26 E26 A24 A23 D16 C16 C12 B12 JP22C MB_DATA63 MB_DATA62 MB_DATA61 MB_DATA60 MB_DATA59 MB_DATA58 MB_DATA57 MB_DATA56 MB_DATA55 MB_DATA54 MB_DATA53 MB_DATA52 MB_DATA51 MB_DATA50 MB_DATA49 MB_DATA48 MB_DATA47 MB_DATA46 MB_DATA45 MB_DATA44 MB_DATA43 MB_DATA42 MB_DATA41 MB_DATA40 MB_DATA39 MB_DATA38 MB_DATA37 MB_DATA36 MB_DATA35 MB_DATA34 MB_DATA33 MB_DATA32 MB_DATA31 MB_DATA30 MB_DATA29 MB_DATA28 MB_DATA27 MB_DATA26 MB_DATA25 MB_DATA24 MB_DATA23 MB_DATA22 MB_DATA21 MB_DATA20 MB_DATA19 MB_DATA18 MB_DATA17 MB_DATA16 MB_DATA15 MB_DATA14 MB_DATA13 MB_DATA12 MB_DATA11 MB_DATA10 MB_DATA9 MB_DATA8 MB_DATA7 MB_DATA6 MB_DATA5 MB_DATA4 MB_DATA3 MB_DATA2 MB_DATA1 MB_DATA0 MB_DM7 MB_DM6 MB_DM5 MB_DM4 MB_DM3 MB_DM2 MB_DM1 MB_DM0 MB_DQS_H7 MB_DQS_L7 MB_DQS_H6 MB_DQS_L6 MB_DQS_H5 MB_DQS_L5 MB_DQS_H4 MB_DQS_L4 MB_DQS_H3 MB_DQS_L3 MB_DQS_H2 MB_DQS_L2 MB_DQS_H1 MB_DQS_L1 MB_DQS_H0 MB_DQS_L0 FOX_PZ63823-284S-41FAthlon 64 S1 Processor Socket

+1.8V +0.9VREF_CPU4

JP22B 1 W17 R386 39.2_0402_1%~D 2 PAD TP2 M_ZN M_ZP R388 39.2_0402_1%~D (8) (8) (8) (8) (9) (9) (9) (9) DDR_CS3_DIMMA# DDR_CS2_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMA# DDR_CS3_DIMMB# DDR_CS2_DIMMB# DDR_CS1_DIMMB# DDR_CS0_DIMMB# VTT_SENSE Y10 AE10 AF10 M_VREF VTT_SENSE M_ZN M_ZP VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 D10 C10 B10 AD10 W10 AC10 AB10 AA10 A10 Y16 AA16 E16 F16

+0.9V

1

10:8:10:8:10DDR_CS3_DIMMA# DDR_CS2_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMA# DDR_CS3_DIMMB# DDR_CS2_DIMMB# DDR_CS1_DIMMB# DDR_CS0_DIMMB# DDR_CKE1_DIMMB DDR_CKE0_DIMMB DDR_CKE1_DIMMA DDR_CKE0_DIMMA DDR_A_MA15 DDR_A_MA14 DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0 DDR_A_BS#2 DDR_A_BS#1 DDR_A_BS#0 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# V19 J22 V22 T19 Y26 J24 W24 U23 H26 J23 J20 J21 K19 K20 V24 K24 L20 R19 L19 L22 L21 M19 M20 M24 M22 N22 N21 R21 K22 R20 T22 T20 U20 U21

DDRII Cmd/Ctrl//Clk

MA0_CS_L3 MA0_CS_L2 MA0_CS_L1 MA0_CS_L0 MB0_CS_L3 MB0_CS_L2 MB0_CS_L1 MB0_CS_L0 MB_CKE1 MB_CKE0 MA_CKE1 MA_CKE0 MA_ADD15 MA_ADD14 MA_ADD13 MA_ADD12 MA_ADD11 MA_ADD10 MA_ADD9 MA_ADD8 MA_ADD7 MA_ADD6 MA_ADD5 MA_ADD4 MA_ADD3 MA_ADD2 MA_ADD1 MA_ADD0 MA_BANK2 MA_BANK1 MA_BANK0

MA0_CLK_H2 MA0_CLK_L2 MA0_CLK_H1 MA0_CLK_L1 MB0_CLK_H2 MB0_CLK_L2 MB0_CLK_H1 MB0_CLK_L1 MB0_ODT1 MB0_ODT0 MA0_ODT1 MA0_ODT0 MB_ADD15 MB_ADD14 MB_ADD13 MB_ADD12 MB_ADD11 MB_ADD10 MB_ADD9 MB_ADD8 MB_ADD7 MB_ADD6 MB_ADD5 MB_ADD4 MB_ADD3 MB_ADD2 MB_ADD1 MB_ADD0 MB_BANK2 MB_BANK1 MB_BANK0 MB_RAS_L MB_CAS_L MB_WE_L

2

DDR_A_CLK2 DDR_A_CLK#2 DDR_A_CLK1 DDR_A_CLK#1

DDR_A_CLK2 DDR_A_CLK#2 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK1 DDR_B_CLK#1

(8) (8) (8) (8) (9) (9) (9) (9)

PLACE THEM CLOSE TO CPU WITHIN 1"

AF18 DDR_B_CLK2 AF17 DDR_B_CLK#2 A17 DDR_B_CLK1 A18 DDR_B_CLK#1 W23 W26 V20 U19 J25 J26 W25 L23 L25 U25 L24 M26 L26 N23 N24 N25 N26 P24 P26 T24 DDR_B_ODT1 DDR_B_ODT0 DDR_A_ODT1 DDR_A_ODT0 DDR_B_MA15 DDR_B_MA14 DDR_B_MA13 DDR_B_MA12 DDR_B_MA11 DDR_B_MA10 DDR_B_MA9 DDR_B_MA8 DDR_B_MA7 DDR_B_MA6 DDR_B_MA5 DDR_B_MA4 DDR_B_MA3 DDR_B_MA2 DDR_B_MA1 DDR_B_MA0

(9) DDR_CKE1_DIMMB (9) DDR_CKE0_DIMMB (8) DDR_CKE1_DIMMA (8) DDR_CKE0_DIMMA (8) DDR_A_MA[15..0]

DDR_B_ODT1 (9) DDR_B_ODT0 (9) DDR_A_ODT1 (8) DDR_A_ODT0 (8) DDR_B_MA[15..0]

(9)

3

(8) DDR_A_BS#2 (8) DDR_A_BS#1 (8) DDR_A_BS#0 (8) DDR_A_RAS# (8) DDR_A_CAS# (8) DDR_A_WE#

K26 DDR_B_BS#2 T26 DDR_B_BS#1 U26 DDR_B_BS#0 U24 DDR_B_RAS# V26 DDR_B_CAS# U22 DDR_B_WE#

DDR_B_BS#2 (9) DDR_B_BS#1 (9) DDR_B_BS#0 (9) DDR_B_RAS# (9) DDR_B_CAS# (9) DDR_B_WE# (9)

MA_RAS_L MA_CAS_L MA_WE_L FOX_PZ63823-284S-41F Athlon 64 S1 Processor Socket

MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10 MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA5 MA_DATA4 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0 MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0 MA_DQS_H7 MA_DQS_L7 MA_DQS_H6 MA_DQS_L6 MA_DQS_H5 MA_DQS_L5 MA_DQS_H4 MA_DQS_L4 MA_DQS_H3 MA_DQS_L3 MA_DQS_H2 MA_DQS_L2 MA_DQS_H1 MA_DQS_L1 MA_DQS_H0 MA_DQS_L0

AA12 AB12 AA14 AB14 W11 Y12 AD13 AB13 AD15 AB15 AB17 Y17 Y14 W14 W16 AD17 Y18 AD19 AD21 AB21 AB18 AA18 AA20 Y20 AA22 Y22 W21 W22 AA21 AB22 AB24 Y24 H22 H20 E22 E21 J19 H24 F22 F20 C23 B22 F18 E18 E20 D22 C19 G18 G17 C17 F14 E14 H17 E17 E15 H15 E13 C13 H12 H11 G14 H14 F12 G12 Y13 AB16 Y19 AC24 F24 E19 C15 E12 W12 W13 Y15 W15 AB19 AB20 AD23 AC23 G22 G21 C22 C21 G16 G15 G13 H13

DDR_A_D63 DDR_A_D62 DDR_A_D61 DDR_A_D60 DDR_A_D59 DDR_A_D58 DDR_A_D57 DDR_A_D56 DDR_A_D55 DDR_A_D54 DDR_A_D53 DDR_A_D52 DDR_A_D51 DDR_A_D50 DDR_A_D49 DDR_A_D48 DDR_A_D47 DDR_A_D46 DDR_A_D45 DDR_A_D44 DDR_A_D43 DDR_A_D42 DDR_A_D41 DDR_A_D40 DDR_A_D39 DDR_A_D38 DDR_A_D37 DDR_A_D36 DDR_A_D35 DDR_A_D34 DDR_A_D33 DDR_A_D32 DDR_A_D31 DDR_A_D30 DDR_A_D29 DDR_A_D28 DDR_A_D27 DDR_A_D26 DDR_A_D25 DDR_A_D24 DDR_A_D23 DDR_A_D22 DDR_A_D21 DDR_A_D20 DDR_A_D19 DDR_A_D18 DDR_A_D17 DDR_A_D16 DDR_A_D15 DDR_A_D14 DDR_A_D13 DDR_A_D12 DDR_A_D11 DDR_A_D10 DDR_A_D9 DDR_A_D8 DDR_A_D7 DDR_A_D6 DDR_A_D5 DDR_A_D4 DDR_A_D3 DDR_A_D2 DDR_A_D1 DDR_A_D0 DDR_A_DM7 DDR_A_DM6 DDR_A_DM5 DDR_A_DM4 DDR_A_DM3 DDR_A_DM2 DDR_A_DM1 DDR_A_DM0 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS0 DDR_A_DQS#0

DDR_A_D[63..0]

(8)

4

To reverse SODIMM socket

To normal SODIMM socket

DDRII Data

3

(9) DDR_B_DM[7..0]

DDR_A_DM[7..0]

(8)

DDR_A_CLK2 1 C336 1.5P_0402_50V8C

DDR_B_CLK2 1 C349 1.5P_0402_50V8C (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) (9) DDR_B_DQS7 DDR_B_DQS#7 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS0 DDR_B_DQS#0

DDR_A_CLK#2 DDR_A_CLK1

2

DDR_B_CLK#2 DDR_B_CLK1

2

1 C344 1.5P_0402_50V8C DDR_B_CLK#1

1 C348 1.5P_0402_50V8C

DDR_A_CLK#1

2

2

2

PLACE CLOSE TO PROCESSOR WITHIN 1.2 INCH

PLACE CLOSE TO PROCESSOR WITHIN 1.2 INCH

DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS0 DDR_A_DQS#0

(8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8) (8)

2

+1.8V

R228 1K_0402_1% 2 CPU_VREF_REF 1 1 C358 1 C363 1000P_0402_50V7K C345 0.1U_0402_16V4Z 1 1 C357 1 C350 1U_0402_6.3V4Z +0.9VREF_CPU

1

A12 2 2

A26

R222 1K_0402_1% 2 2 2

Athlon 64 S1g11000P_0402_50V7K

1000P_0402_50V7K

uPGA638 Top View

VDD_VREF_SUS_CPU LAYOUT:PLACE CLOSE TO CPU1

AF1

1

Security Classification

Compal Secret Data2006/08/18Deciphered Date

Issued Date

2007/8/18

Title

AMD CPU DDRII MEMORY I/FSize Document Number Custom ICW50 / ICY70 Date:

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C D

LA-3581PSheetE

Rev 1.0 5 of 42

Friday, April 20, 2007

5

4

3

2

1

ATHLON Control and DebugLAYOUT: ROUTE VDDA TRACE APPROX. 50 mils WIDE (USE 2x25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG.+2.5VS 1 1 C266 2 L28 1 C276 1 C271 1 C277 3300P_0402_50V7K R370 R371 R369 1 R368 1 1 1 2 2 R378 1 R376 1 2 2 300_0402_5% 300_0402_5% CPU_SIC_R CPU_SID_R CPU_HTREF1 CPU_HTREF0 CPU_HT_RESET# CPU_ALL_PWROK CPU_LDTSTOP#

+1.8V

1

R155 300_0402_5% 2 F8 F9 B7 A7 F10 AF4 AF5 P6 R6 CPU_VCC_SENSE CPU_VSS_SENSE PAD PAD TP3 TP1 F6 E6 W9 Y9 A9 A8 CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1 G10 AA9 AC9 AD9 AF9 E9 E8 G9 H10 AA7 C2 D7 E7 F7 C7 AC8 C3 AA6 W7 W8 Y6 AB6 P20 P19 N20 N19 VDDA2 VDDA1 RESET_L PWROK LDTSTOP_L SIC SID HTREF1 HTREF0 VDD_FB_H VDD_FB_L VDDIO_FB_H VDDIO_FB_L CLKIN_H CLKIN_L DBRDY TMS TCK TRST_L TDI TEST25_H TEST25_L TEST19 TEST18 TEST13 TEST9 TEST17 TEST16 TEST15 TEST14 TEST12 TEST7 TEST6 THERMDC THERMDA TEST3 TEST2 RSVD0 RSVD1 RSVD2 RSVD3 DBREQ_L TDO E10 CPU_DBREQ# VID5 VID4 VID3 VID2 VID1 VID0 CPU_PRESENT_L PSI_L THERMTRIP_L PROCHOT_L AF6 H_THERMTRIP_S# AC7 CPU_PROCHOT#_1.8 2 JP22D

1 R156 300_0402_5%

W=50mils

+2.5VS_VDDA

FCM2012C-800_0805

2D

22U_0805_6.3V6M

2 4.7U_0805_10V4Z

2

2 0.22U_0603_16V7K

+1.8V

(15) CPU_SIC (15) CPU_SID +1.2V_HT +1.8V +3VS 1 +1.8V

0_0402_5% 0_0402_5% 2 44.2_0603_1% 2 44.2_0603_1%

A5 C6 A6 A4 C5 B5 AC6 A3

VID5 VID4 VID3 VID2 VID1 VID0 CPU_PRESENT# PSI# PSI# (41)

5:10place them to CPU within 1"(41) CPU_VCC_SENSE (41) CPU_VSS_SENSE

VID5 VID4 VID3 VID2 VID1 VID0

(41) (41) (41) (41) (41) (41)

D

R381 C543 0.1U_0402_16V4Z 4.7K_0402_5% @ 1 2 5 U26 Y A G 3 2

1

2

R379 300_0402_5% B 2

(10) HTCPU_PWRGD

1

NC7SZ08P5X_NL_SC70-5 @ 2 0_0402_5% (10) CPUCLK#

3900P_0402_50V7K R382 169_0402_1% C544 1

1

4

1 R383

2 0_0402_5% @

CPU_ALL_PWROK

(10) CPUCLK

C545 1

2

CPU_CLKIN_SC_P CPU_CLKIN_SC_N

P

1 R380 +1.8V +1.8V 1 R184 300_0402_5% 2 2 (10) HTCPU_STOP# 1 B A

2

2

AE9 CPU_TDO R384 1 2 80.6_0402_1%

3900P_0402_50V7K

TEST29_H TEST29_L

C9 C8

CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N

5:5:5AE7 AD7 AE8 AB8 CPU_TEST21_SCANEN AF7 J7 H8 AF8 AE6 CPU_TEST26_BURNIN# K8 C4 H16 B18 B3 C1 H6 G6 D5 R24 W18 R23 AA8 H18 H19

ROUTE AS 80 Ohm DIFFERENTIAL PAIR PLACE IT CLOSE TO CPU WITHIN 1"

U9 Y 4 1 R189 2 0_0402_5% @ CPU_LDTSTOP#

MISC

P

5

NC7SZ08P5X_NL_SC70-5 @ 2 0_0402_5% CPU_THERMDC CPU_THERMDA

TEST24 TEST23 TEST22 TEST21 TEST20 TEST28_H TEST28_L TEST27 TEST26 TEST10 TEST8 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20

C

1 R183 +1.8V

3

G

C

10:10+1.8V +1.8V

1 R373 300_0402_5% 2 R375 0_0402_5% (15,18,27,28) MCP_PWRGD (10) HTCPU_RST# 1 @ 2

5

U25 Y 4 1 R377 2 0_0402_5% @ CPU_HT_RESET#

B A

G

1

P

MCP_PWRGD_R

2

CPU_TEST26_BURNIN# CPU_PRESENT# CPU_TEST25_H_BYPASSCLK_H CPU_TEST21_SCANEN CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1

R199 1 R198 1 R188 1 R197 R387 R385 R215 1 1 1 1

2 300_0402_5% 2 1K_0402_5% 2 510_0402_5% 2 2 2 2 300_0402_5% 510_0402_5% 300_0402_5% 300_0402_5%

NC7SZ08P5X_NL_SC70-5 @

3

1 R374

2 0_0402_5%

R26 R25 P22 R22

RSVD4 RSVD5 RSVD6 RSVD7 FOX_PZ63823-284S-41F

220_0402_5%HT@

220_0402_5%HT@

220_0402_5%HT@

220_0402_5%HT@

+1.8V 220_0402_5%

HT@

AMD NPT S1 SOCKET Processor Socket

HDT Connector+1.8V 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24 26 +3VS +3V JP7

+1.8V 1

+1.8V 1

+3V

+3V

R163 1

R162 1

R161 1

R160 1

R159 1

B

1

B

R114 300_0402_5% 2 2

R127 1K_0402_5%

R117 @ 1K_0402_5% 2 2 R116 10K_0402_5%

2

2

2

2

3V_LDT_RST#

2

CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO

2

2

1

R113 220_0402_5% HT@

Q16 H_THERMTRIP_S# 2 G 3 1H_THERMTRIP# MMBT3904_SOT23 1 R115 3 S CPU_HT_RESET# 2 0_0402_5% @

3

Q15 MMBT3904_SOT23 1 @ MAINPWON (35,36,37) H_THERMTRIP# (10)

1

1 R535

NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.

2 1 0_0402_5% @

D

SAMTEC_ASP-68200-07 @

Q14 2N7002_SOT23 HT@ +1.8V +3VS

PVT Modify 2007/03/221 +3VS R133 10K_0402_5% 2CPU_PH_G 2 2 1 R130 4.7K_0402_5%

C269 0.1U_0402_16V4Z

1

1

U4 2200P_0402_50V7KA

2

C275

1 CPU_THERMDA CPU_THERMDC 2 3 8 7

2

R186 @ 10K_0402_5% Q19 E (10) PROCHOT# 1 R141 CPU_PROCHOT#_1.8 2 0_0402_5% @

2

D+ DSCLK SDATA

VDD1 ALERT# THERM# GND

1 6 4 5

3 1 MMBT3904_SOT23 C

2 B

EC_THERM# (15,27,28)

A

(27,28) EC_SMB_CK2 (27,28) EC_SMB_DA2

EC_SMB_CK2 EC_SMB_DA2

Connect to MCP67Security Classification

ADM1032ARM_RM8

U2 CLOSE CPU, CPU_THERMDA&CPU_THERMDC PLACE CLOSE TO PROCESSOR WITHIN 1" INCH

Compal Secret Data2006/08/18Deciphered Date

Issued Date

2007/8/18

Title

AMD CPU CTRL & DEBUGSize C Date: Document Number

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.4 3 2

ICW50 / ICY70 LA-3581PFriday, April 20, 20071

Rev 1.0 Sheet 6 of 42

5

5

4

3

2

1

+CPU_CORE

1 + C548 2 470U_D2E_2VM_R9

1 + C550 2 470U_D2E_2VM_R9

1 + C546 2 470U_D2E_2VM_R9

1 + C547 2 330U_D2E_2.5VM_R9

D

D

+CPU_CORE C287 10U_0805_10V6M 1 1 C288 10U_0805_10V6M 1 1 C289 10U_0805_10V6M 1 1

+CPU_CORE

PROCESSOR POWER AND GROUNDJP22F +CPU_CORE JP22E AC4 VDD1 AD2 VDD2 G4 VDD3 H2 VDD4 J9 VDD5 J11 VDD6 J13 VDD7 K6 VDD8 K10 VDD9 K12 VDD10 K14 VDD11 L4 VDD12 L7 VDD13 L9 VDD14 L11 VDD15 L13 VDD16 M2 VDD17 M6 VDD18 M8 VDD19 M10 VDD20 N7 VDD21 N9 VDD22 N11 VDD23 P8 VDD24 P10 VDD25 R4 VDD26 R7 VDD27 R9 VDD28 R11 VDD29 T2 VDD30 T6 VDD31 T8 VDD32 T10 VDD33 T12 VDD34 T14 VDD35 U7 VDD36 U9 VDD37 U11 VDD38 U13 VDD39 V6 VDD40 V8 VDD41 V10 VDD42 +CPU_CORE VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 VDD54 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 V12 V14 W4 Y2 J15 K16 L15 M16 P16 T16 U15 V16 +1.8V H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17 P18 P21 P23 P25 R17 T18 T21 T23 T25 U17 V18 V21 V23 V25 Y25 AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17 D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4 VSS1 VSS66 VSS2 VSS67 VSS3 VSS68 VSS4 VSS69 VSS5 VSS70 VSS6 VSS71 VSS7 VSS72 VSS8 VSS73 VSS9 VSS74 VSS10 VSS75 VSS11 VSS76 VSS12 VSS77 VSS13 VSS78 VSS14 VSS79 VSS15 VSS80 VSS16 VSS81 VSS17 VSS82 VSS18 VSS83 VSS19 VSS84 VSS20 VSS85 VSS21 VSS86 VSS22 VSS87 VSS23 VSS88 VSS24 VSS89 VSS25 VSS90 VSS26 VSS91 VSS27 VSS92 VSS28 VSS93 VSS29 VSS94 VSS30 VSS95 VSS31 VSS96 VSS32 VSS97 VSS33 VSS98 VSS34 VSS99 VSS35 VSS100 VSS36 VSS101 VSS37 VSS102 VSS38 VSS103 VSS39 VSS104 VSS40 VSS105 VSS41 VSS106 VSS42 VSS107 VSS43 VSS108 VSS44 VSS109 VSS45 VSS110 VSS46 VSS111 VSS47 VSS112 VSS48 VSS113 VSS49 VSS114 VSS50 VSS115 VSS51 VSS116 VSS52 VSS117 VSS53 VSS118 VSS54 VSS119 VSS55 VSS120 VSS56 VSS121 VSS57 VSS122 VSS58 VSS123 VSS59 VSS124 VSS60 VSS125 VSS61 VSS126 VSS62 VSS127 VSS63 VSS128 VSS64 VSS129 VSS65 FOX_PZ63823-284S-41F J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 M11 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6

1

1 + C551 820U_E9_2.5V_M_R7 45@

2 2 C279 10U_0805_10V6M

2 2 C280 10U_0805_10V6M

2 2 C282 10U_0805_10V6M

2 C281 10U_0805_10V6M 2

10/2 Modify

CPU SOCKET S1 DECOUPLING+CPU_CORE

1

C315 22U_0805_6.3V6M

1

C326 22U_0805_6.3V6M

1

C332 10U_0805_10V6M

1

C333 22U_0805_6.3V6M

1

C327 10U_0805_10V6M

1

C328 10U_0805_10V6M

1

C324 10U_0805_10V6M

1

C316 10U_0805_10V6M

1

C334 22U_0805_6.3V6M

2

2

2

2

2

2

2

2

2

C

+CPU_CORE

+1.8V

C

Power

1

C318 0.22U_0402_10V4Z

1

C308 0.22U_0402_10V4Z

1

C319 180P_0402_50V8J

1

C309 0.01U_0402_16V7K

1

C353 10U_0805_10V6M

1

C343 10U_0805_10V6M

1

C361 0.22U_0402_10V4Z

1

C356 0.22U_0402_10V4Z

2

2

2

2

2

2

2

2

Ground

DECOUPLING BETWEEN PROCESSOR AND DIMMs PLACE CLOSE TO PROCESSOR AS POSSIBLE+1.8V 1 1 1 1 1 1 1

FOX_PZ63823-284S-41FAthlon 64 S1 Processor Socket

C352 4.7U_0805_10V4Z

C342 4.7U_0805_10V4Z

C351 4.7U_0805_10V4Z

C388 4.7U_0805_10V4Z

C362 0.22U_0402_10V4Z

C386 0.22U_0402_10V4Z

C383 0.22U_0402_10V4Z

2

2

2

2

2

2

2

B

A1

A26

B

1

C381 0.22U_0402_10V4Z

1

C385 0.01U_0402_16V7K

1

C382 0.01U_0402_16V7K

1

C340

1

C360 180P_0402_50V8J

2

2

2

2

180P_0402_50V8J 2

Athlon 64 S1g1 uPGA638 Top View

Athlon 64 S1 Processor Socket

+0.9V

1

C304 4.7U_0805_10V4Z

1

C320 4.7U_0805_10V4Z

1

C303 4.7U_0805_10V4Z

1

C302 4.7U_0805_10V4Z

1

C313 0.22U_0402_10V4Z

1

C312 0.22U_0402_10V4Z

1

C314 0.22U_0402_10V4Z

1

C298 0.22U_0402_10V4Z

AF12

2

2

2

2

2

2

2

1

C299 1000P_0402_50V7K

1

C300 1000P_0402_50V7K

1

C307 1000P_0402_50V7K

1

C306 1000P_0402_50V7K

1

C305

1

C297

1

C296

1

C295 180P_0402_50V8J

2

2

2

2

2

180P_0402_50V8J 2

180P_0402_50V8J 2

180P_0402_50V8J 2

A

A

Security Classification

Compal Secret Data2006/08/18Deciphered Date

Issued Date

2007/8/18

Title

AMD CPU PWR & GNDSize C Date: Document Number

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

ICW50 / ICY70 LA-3581PFriday, April 20, 20071

Rev 1.0 Sheet 7 of 42

5

4

3

2

1

+1.8V

+1.8V C579

+DIMM_VREF C428

+1.8V

+1.8V C399 C414 C427 C425 C577 C575 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.01U_0402_16V7K10P_0402_50V8K 0.22U_0603_16V7K0.22U_0603_16V7K 1 1 1 1 1 1 1 1 1 1 1 1 1

1

R275 1 1K_0402_1%

JP28 DDR_A_D0 DDR_A_D1D

1

DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199

VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

DDR_A_DM0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDR_A_DM1 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_D14 DDR_A_D15

2 4.7U_0805_10V4Z

2 0.1U_0402_16V4Z

2

DDR_A_D4 DDR_A_D5

1

1

C573 0.22U_0603_16V7K 2 2 2 2 2 2 2 2 2 2 2 2 2 2 C413 C398 C424 C426 C578 C576 C574 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.01U_0402_16V7K10P_0402_50V8K 0.22U_0603_16V7K0.22U_0603_16V7K0.22U_0603_16V7K

D

R274 1K_0402_1%

2

+1.8V

DDR_A_CLK1 (5) DDR_A_CLK#1 (5) 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 1 1 C418 + C628 220U_D2_4VM_R15 2

1 C407

1 C408

1 C409 C409

1 C410

1 C411

1 C412 C412

1 C415

1 C416

1 C417 C417

DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25C

DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3

2

2

2

2

2

2

2

2

2

2

(5) DDR_A_D[0..63] (5) DDR_A_DM[0..7] (5) DDR_A_DQS[0..7] (5) DDR_A_MA[0..15] (5) DDR_A_DQS#[0..7]

DDR_A_D[0..63] DDR_A_DM[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15] DDR_A_DQS#[0..7]

+0.9VC

DDR_A_DM3 DDR_A_D26 DDR_A_D27 (5) DDR_CKE0_DIMMA (5) DDR_CS2_DIMMA# (5) DDR_A_BS#2 DDR_CKE0_DIMMA DDR_CS2_DIMMA# DDR_A_BS#2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_MA10 DDR_A_BS#0 DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# DDR_A_ODT1 DDR_A_D32 DDR_A_D33

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z 0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z 0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z 0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_A_D30 DDR_A_D31 DDR_CKE1_DIMMA DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# DDR_A_ODT0 DDR_A_MA13 DDR_CS3_DIMMA# DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_CLK2 DDR_A_CLK#2 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 R281 R282 1 1 2 10K_0402_5% 2 10K_0402_5% DDR_A_CLK2 (5) DDR_A_CLK#2 (5) DDR_A_BS#1 (5) DDR_A_RAS# (5) DDR_CS0_DIMMA# (5) DDR_A_ODT0 (5) DDR_CS3_DIMMA# (5) DDR_CKE1_DIMMA (5)

1 1 + 2

1

1

1

1

1

1

1

1

1

1

1

1

1

C422 150U_D2_6.3VM

2 C437

2 C436 C436

2 C435

2 C434 C434

2 C433

2 C431

2 C432

2 C453

2 C452

2 C451

2 C450

2 C449

2 C448

2 C447

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V+0.9V DDR_CKE0_DIMMA DDR_CS2_DIMMA# DDR_A_BS#2 DDR_A_MA12

(5) DDR_A_BS#0 (5) DDR_A_WE# (5) DDR_A_CAS# (5) DDR_CS1_DIMMA# (5) DDR_A_ODT1

B

DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49

1 2 RP10 1 2 RP11 DDR_A_MA9 1 DDR_A_MA8 2 RP12 DDR_A_MA5 1 DDR_A_MA3 2 RP13 DDR_A_MA1 1 DDR_A_MA10 2 RP14 DDR_A_BS#0 1 DDR_A_WE# 2 RP9 DDR_A_CAS# 1 DDR_CS1_DIMMA# 2 RP8 DDR_A_ODT1 R277 1 DDR_CS3_DIMMA# R280 1

4 3 47_0404_4P2R_5% 4 3 47_0404_4P2R_5% 4 3 47_0404_4P2R_5% 4 3 47_0404_4P2R_5% 4 3 47_0404_4P2R_5% 4 3 47_0404_4P2R_5% 4 3 47_0404_4P2R_5% 2 47_0402_1% 2 47_0402_1%

1 2 RP15 1 2 RP16 1 2 RP17 1 2 RP20 1 2 RP18 1 2 RP19 1 2 RP21

DDR_A_MA14 4 DDR_A_MA15 3 47_0404_4P2R_5% DDR_A_MA7 4 DDR_CKE1_DIMMA 3 47_0404_4P2R_5% DDR_A_MA6 4 DDR_A_MA11 3 47_0404_4P2R_5% DDR_A_MA2 4 DDR_A_MA4 3 47_0404_4P2R_5% DDR_A_BS#1 4 DDR_A_MA0 3 47_0404_4P2R_5% DDR_CS0_DIMMA# 4 DDR_A_RAS# 3 47_0404_4P2R_5% DDR_A_MA13 4 DDR_A_ODT0 3 47_0404_4P2R_5%

B

+1.8V 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7A

1

1

1

1

1

1

1

1

1

2 C443

2 C438

2 C439

2 C445

2 C446 C446

2 C440

2 C441

2 C442

2 C444

+0.9V

A

DDR_A_D58 DDR_A_D59 (9,15) MEM_SMBDATA (9,15) MEM_SMBCLK MEM_SMBDATA MEM_SMBCLK +3VS 1 C429 0.1U_0402_16V4Z

Layout Note: Place one 0.1uF cap close to every 2 pullup resistors terminated to +0.9VSecurity ClassificationIssued Date

Compal Secret Data2006/08/18Deciphered Date

2007/8/18

Title

2

FOX_AS0A426-M2RN-7F

DDR2 SO-DIMM ISize Document Number Custom ICW50 / ICY70 Date:

DIMM1 REV H:5.2mm (BOT)4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.3 2

LA-3581PSheet1

Rev 1.0 8 of 42

Friday, April 20, 2007

5

5

4

3

2

1

+1.8V

+1.8V

+DIMM_VREF

(5) DDR_B_D[0..63] (5) DDR_B_DM[0..7] (5) DDR_B_DQS[0..7]

DDR_B_D[0..63] +1.8V DDR_B_DM[0..7] DDR_B_DQS[0..7] DDR_B_MA[0..15] DDR_B_DQS#[0..7] 1 1 1 1 C654 1000P_0402_50V7K C656 1000P_0402_50V7K

0.1U_0402_16V4Z

4.7U_0805_10V4Z

C455

C459

JP29 DDR_B_D0 DDR_B_D1D

DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199

VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

(5) DDR_B_MA[0..15] (5) DDR_B_DQS#[0..7]

DDR_B_D4 DDR_B_D5 DDR_B_DM0 DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13 DDR_B_DM1

1

1

2

2

2

2

2

2

C653 1000P_0402_50V7K +1.8V

C655 1000P_0402_50V7K

D

4.7U_0805_10V4Z

4.7U_0805_10V4Z 4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z 4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z 4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

DDR_B_CLK1 DDR_B_CLK#1 DDR_B_D14 DDR_B_D15

1 1 C631 + C629 220U_D2_4VM_R15 2

DDR_B_CLK1 (5) DDR_B_CLK#1 (5)

1 C625

1 C624

1 C623 C623

1 C622

1 C627

1 C626

1 C632

1 C633

1 C630

2

2

2

2

2

2

2

2

2

2

DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25C

DDR_B_D20 DDR_B_D21 +0.9V DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 DDR_CKE1_DIMMB DDR_B_MA15 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB# DDR_B_ODT0 DDR_B_MA13 DDR_CS3_DIMMB# DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_D38 DDR_B_D39 DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 R289 1 R288 1 2 10K_0402_5% 2 10K_0402_5% +3VS +0.9V +1.8V DDR_B_CLK2 (5) DDR_B_CLK#2 (5) 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C469 0.1U_0402_16V4Z C457 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_B_BS#1 (5) DDR_B_RAS# (5) DDR_CS0_DIMMB# (5) DDR_B_ODT0 (5) DDR_CS3_DIMMB# (5) DDR_CS2_DIMMB# DDR_CKE0_DIMMB DDR_B_MA12 DDR_B_BS#2 DDR_B_MA8 DDR_B_MA9 DDR_B_MA3 DDR_B_MA5 DDR_B_MA10 DDR_B_MA1 DDR_B_WE# DDR_B_BS#0 DDR_CS0_DIMMB# DDR_B_RAS# DDR_B_ODT1 DDR_CS3_DIMMB# 1 2 RP22 1 2 RP23 1 2 RP24 1 2 RP25 1 2 RP26 1 2 RP27 1 2 RP29 R286 1 R287 1 4 3 47_0404_4P2R_5% 4 3 47_0404_4P2R_5% 4 3 47_0404_4P2R_5% 4 3 47_0404_4P2R_5% 4 3 47_0404_4P2R_5% 4 3 47_0404_4P2R_5% 4 3 47_0404_4P2R_5% 2 47_0402_1% 2 47_0402_1% DDR_CKE1_DIMMB (5) 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1

1

1

1

1

1

1

1

1

1

1

1C

DDR_B_DM3 DDR_B_D26 DDR_B_D27 (5) DDR_CKE0_DIMMB (5) DDR_CS2_DIMMB# (5) DDR_B_BS#2 DDR_CKE0_DIMMB DDR_CS2_DIMMB# DDR_B_BS#2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 DDR_B_MA10 DDR_B_BS#0 DDR_B_WE# DDR_B_CAS# DDR_CS1_DIMMB# DDR_B_ODT1 DDR_B_D32 DDR_B_D33

2 C483

2 C482

2 C481

2 C480

2 C479

2 C478

2 C466

2 C464 C464

2 C465

2 C463 C463

2 C462

2 C461 C461

Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9V

+0.9V

(5) DDR_B_BS#0 (5) DDR_B_WE# (5) DDR_B_CAS# (5) DDR_CS1_DIMMB# (5) DDR_B_ODT1

B

DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49

1 2 RP30 1 2 RP31 1 2 RP32 1 2 RP33 1 2 RP34 1 2 RP28 1 2 RP35

DDR_CKE1_DIMMB 4 DDR_B_MA15 3 47_0404_4P2R_5% DDR_B_MA14 4 DDR_B_MA11 3 47_0404_4P2R_5% DDR_B_MA7 4 DDR_B_MA6 3 47_0404_4P2R_5% DDR_B_MA4 4 DDR_B_MA2 3 47_0404_4P2R_5% DDR_B_MA0 4 DDR_B_BS#1 3 47_0404_4P2R_5% DDR_B_CAS# 4 DDR_CS1_DIMMB# 3 47_0404_4P2R_5% DDR_B_ODT0 4 DDR_B_MA13 3 47_0404_4P2R_5%

B

DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_DM7A

1

1

1

1

1

1

1

1

1

1

1

2 C476 C476

2 C472

2 C471

2 C470

2

2

2 C458 C458

2 C477

2 C486

2 C485

2 C484

DDR_B_D58 DDR_B_D59 (8,15) MEM_SMBDATA (8,15) MEM_SMBCLK +3VS MEM_SMBDATA MEM_SMBCLK 1 C456

Layout Note: Place one 0.1uF cap close to every 2 pullup resistors terminated to +0.9VSecurity ClassificationIssued Date

A

Compal Secret Data2006/08/18Deciphered Date

2007/8/18

Title

FOX_AS0A426-MARG-7F 2 0.1U_0402_16V4Z

DDR2 SO-DIMM IISize Document Number Custom ICW50 / ICY70 Date:

Change PCB Footprint

DIMM0 REV H:9.2mm (BOT)5 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.3 2

LA-3581PSheet1

Rev 1.0 9 of 42

Friday, April 20, 2007

5

4

3

2

1

U23A H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15

D

(4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4)

H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15

AF16 AG16 AH16 AJ16 AJ15 AK15 AK16 AL16 AG17 AF17 AL17 AK17 AL18 AK18 AJ19 AK19 AD14 AE14 AF14 AG14 AH14 AJ14 AL13 AK13 AC15 AD15 AD16 AE16 AE17 AD17 AB17 AC17

MCP67 PART 1 OF 8HT_MCP_RXD0_P HT_MCP_RXD0_N HT_MCP_RXD1_P HT_MCP_RXD1_N HT_MCP_RXD2_P HT_MCP_RXD2_N HT_MCP_RXD3_P HT_MCP_RXD3_N HT_MCP_RXD4_P HT_MCP_RXD4_N HT_MCP_RXD5_P HT_MCP_RXD5_N HT_MCP_RXD6_P HT_MCP_RXD6_N HT_MCP_RXD7_P HT_MCP_RXD7_N HT_MCP_RXD8_P HT_MCP_RXD8_N HT_MCP_RXD9_P HT_MCP_RXD9_N HT_MCP_RXD10_P HT_MCP_RXD10_N HT_MCP_RXD11_P HT_MCP_RXD11_N HT_MCP_RXD12_P HT_MCP_RXD12_N HT_MCP_RXD13_P HT_MCP_RXD13_N HT_MCP_RXD14_P HT_MCP_RXD14_N HT_MCP_RXD15_P HT_MCP_RXD15_N HT_MCP_TXD0_P HT_MCP_TXD0_N HT_MCP_TXD1_P HT_MCP_TXD1_N HT_MCP_TXD2_P HT_MCP_TXD2_N HT_MCP_TXD3_P HT_MCP_TXD3_N HT_MCP_TXD4_P HT_MCP_TXD4_N HT_MCP_TXD5_P HT_MCP_TXD5_N HT_MCP_TXD6_P HT_MCP_TXD6_N HT_MCP_TXD7_P HT_MCP_TXD7_N HT_MCP_TXD8_P HT_MCP_TXD8_N HT_MCP_TXD9_P HT_MCP_TXD9_N HT_MCP_TXD10_P HT_MCP_TXD10_N HT_MCP_TXD11_P HT_MCP_TXD11_N HT_MCP_TXD12_P HT_MCP_TXD12_N HT_MCP_TXD13_P HT_MCP_TXD13_N HT_MCP_TXD14_P HT_MCP_TXD14_N HT_MCP_TXD15_P HT_MCP_TXD15_N

HT

AK27 AJ27 AK26 AL26 AK25 AL25 AL24 AK24 AK22 AL22 AK21 AL21 AH21 AJ21 AL20 AM20 AG27 AH27 AF25 AG25 AH25 AJ25 AE23 AF23 AD21 AE21 AF21 AG21 AC20 AD20 AE19 AF19

H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15

H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15

(4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4)

D

C

C

(4) (4) (4) (4)

H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1

H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1

AJ17 AH17 AL14 AK14

HT_MCP_RX_CLK0_P HT_MCP_RX_CLK0_N HT_MCP_RX_CLK1_P HT_MCP_RX_CLK1_N

HT_MCP_TX_CLK0_P HT_MCP_TX_CLK0_N HT_MCP_TX_CLK1_P HT_MCP_TX_CLK1_N

AK23 AJ23 AG23 AH23

H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1

H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1

(4) (4) (4) (4)

9/25 Modify TO +3VS+3VS

(4) H_CTLOP0 (4) H_CTLON0

H_CTLOP0 H_CTLON0

AH19 AG19 AC18 AD18 AC13 AB13

HT_MCP_RXCTL0_P HT_MCP_RXCTL0_N HT_MCP_RXCTL1_P/RESERVED HT_MCP_RXCTL1_N/RESERVED THERMTRIP#/GPIO_58 PROCHOT#/GPIO_20

HT_MCP_TXCTL0_P HT_MCP_TXCTL0_N RESERVED/HT_MCP_TXCTL1_P RESERVED/HT_MCP_TXCTL1_N HT_MCP_REQ# HT_MCP_STOP# HT_MCP_RST# HT_MCP_PWRGD CLKOUT_200MHZ_P CLKOUT_200MHZ_N

AK20 AJ20 AD19 AC19 AD23 AB20 AC21 AD22 AL28 AM28

H_CTLIP0 H_CTLIN0

H_CTLIP0 (4) H_CTLIN0 (4)

1 R164 22K_0402_5% 2 +1.2V_HT

(6) H_THERMTRIP# (6) PROCHOT# C46 4.7U_0805_10V4Z 1 C43 0.1U_0402_16V4Z 1

HTCPU_REQ# HTCPU_STOP# HTCPU_RST# HTCPU_PWRGD

HTCPU_STOP# (6) HTCPU_RST# (6) HTCPU_PWRGD (6) CPUCLK (6) CPUCLK# (6)

+3VS

L7 1 2 MBK1608121YZF_0603

+3.3V_PLL_CPU +1.2V_PLL_CPU_HT +1.2V_HT

AB16 AB15

+3.3V_PLL_CPU +1.2V_PLL_CPU_HT CLKOUT_25MHZ HT_MCP_COMP_VDD CPU_SBVREF CLK200_TERM_GND

2

2 1 R364 AM12 2 150_0402_1% 2

AK28 AG28 AJ28 1

TP4

PAD

B

+1.2V_HT

L13 1 2 MBK1608121YZF_0603

C141 10U_0805_10V4Z C101 1 1 0.1U_0402_16V4Z

1 R366

AL12 150_0402_1% HT_MCP_COMP_GND MCP67-MV_PBGA836

B

R123 2.37K_0402_1% 2

1 C136 0.1U_0402_16V4Z

2

2

2

A

A

Security Classification Issued Date

Compal Secret Data2006/08/18Deciphered Date

2007/8/18

Title

MCP67 HT LINKSize Document Number Custom ICW50 / ICY70 Date:

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

LA-3581PSheet1

Rev 1.0 10 of 42

Friday, April 20, 2007

5

4

3

2

1

(18) PCIE_GTX_C_MRX_P[0..15] (18) PCIE_GTX_C_MRX_N[0..15]

PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_N[0..15] U23B PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P15 PCIE_GTX_C_MRX_N15 MCP_PCIE_WAKE# 1 10K_0402_5% @ 1 10K_0402_5% @ 1 10K_0402_5% @

(18) PCIE_MTX_C_GRX_P[0..15] (18) PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15] PCIE_MTX_C_GRX_N[0..15]

D

+3V 1

R45 10K_0402_5% @ 2 (25,26,27) MCP_PCIE_WAKE#C

F23 G23 F24 F25 D25 D26 C28 D28 C29 C30 D29 D30 F26 F27 F28 F29 H23 H24 H25 H26 H27 H28 K24 K25 K27 K26 K28 K29 J31 J30 K31 K30 H17 U31 U30 U29 U28 L29 L30 W27 W28 M26 M27 U26 U27 N23 N22 U25 U24 N30 N31 R22 U23 P31 P30 T22 V31

MVP67 PART 2 OF 8PE0_RX0_P PE0_RX0_N PE0_RX1_P PE0_RX1_N PE0_RX2_P PE0_RX2_N PE0_RX3_P PE0_RX3_N PE0_RX4_P PE0_RX4_N PE0_RX5_P PE0_RX5_N PE0_RX6_P PE0_RX6_N PE0_RX7_P PE0_RX7_N PE0_RX8_P PE0_RX8_N PE0_RX9_P PE0_RX9_N PE0_RX10_P PE0_RX10_N PE0_RX11_P PE0_RX11_N PE0_RX12_P PE0_RX12_N PE0_RX13_P PE0_RX13_N PE0_RX14_P PE0_RX14_N PE0_RX15_P PE0_RX15_N PE0_TX0_P PE0_TX0_N PE0_TX1_P PE0_TX1_N PE0_TX2_P PE0_TX2_N PE0_TX3_P PE0_TX3_N PE0_TX4_P PE0_TX4_N PE0_TX5_P PE0_TX5_N PE0_TX6_P PE0_TX6_N PE0_TX7_P PE0_TX7_N PE0_TX8_P PE0_TX8_N PE0_TX9_P PE0_TX9_N PE0_TX10_P PE0_TX10_N PE0_TX11_P PE0_TX11_N PE0_TX12_P PE0_TX12_N PE0_TX13_P PE0_TX13_N PE0_TX14_P PE0_TX14_N PE0_TX15_P PE0_TX15_N PE0_REFCLK_P PE0_REFCLK_N

CLOSE TO CONNECTD24 C24 A24 B24 B25 C25 B26 C26 C27 D27 A28 B28 A29 B29 A30 B30 B31 B32 C31 C32 D31 D32 E31 E30 F31 F30 G29 G30 H29 H30 H32 H31 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_P15 PCIE_MTX_GRX_N15 C194 1 C167 1 C196 1 C169 1 C198 1 C171 1 C200 1 C173 1 C202 1 C175 1 C204 1 C177 1 C229 1 C238 1 C231 1 C240 1 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K VGA@ C193 VGA@ VGA@ C166 VGA@ VGA@ C195 VGA@ VGA@ C168 VGA@ VGA@ C197 VGA@ VGA@ C170 VGA@ VGA@ C199 VGA@ VGA@ C172 VGA@ VGA@ C201 VGA@ VGA@ C174 VGA@ VGA@ C203 VGA@ VGA@ C176 VGA@ VGA@ C228 VGA@ VGA@ C237 VGA@ VGA@ C230 VGA@ VGA@ C239 VGA@ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15

D

PCIE GFX I/F

R365 2 R367 2 R149 2 EXPRESS@ 2 0_0402_5% 2 0_0402_5% EXPRESS@ R152 2 PEA_PRSNT# 2 0_0402_5% MINI2@ 2 0_0402_5% MINI2@ R118 2 PEB_PRSNT# MINI1@ 0_0402_5% 2 2 0_0402_5% MINI1@ R148 2 PEC_PRSNT#

(18) PE_PRSNTX16# (26) PCIE_MRX_PTX_P1 (26) PCIE_MRX_PTX_N1 (26) EXP_CLKREQ# R146 1 R147 1 +3VS R139 1 R140 1 +3VS R134 1 R135 1 +3VS PCIE_MRX_PTX_P1_R PCIE_MRX_PTX_N1_R 1 10K_0402_5% EXPRESS@ PCIE_MRX_PTX_P2_R PCIE_MRX_PTX_N2_R 1 10K_0402_5% MINI2@ PCIE_MRX_PTX_P3_R PCIE_MRX_PTX_N3_R 1 10K_0402_5% MINI1@

PE_WAKE#/GPIO_21 PE0_PRSNTX1#/DDC_CLK1 PE0_PRSNTX4#/DDC_DATA1 PE0_PRSNTX8#/EXP_EN PE0_PRSNTX16# PE1_RX_P PE1_RX_N PEA_CLKREQ# PEA_PRSNT# PE2_RX_P PE2_RX_N PEB_CLKREQ# PEB_PRSNT# PE3_RX_P PE3_RX_N PEC_CLKREQ# PEC_PRSNT# PE4_RX_P PE4_RX_N PED_CLKREQ#/GPIO_16 PED_PRSNT# PE5_RX_P PE5_RX_N PEE_CLKREQ#/GPIO_17 PEE_PRSNT# PE6_RX_P PE6_RX_N PEF_CLKREQ#/GPIO_18 PEF_PRSNT# +1.2V_PLL_PE_SS1 +1.2V_PLL_PE_SS2

R29 CLK_PCIE_VGA R30 CLK_PCIE_VGA#

CLK_PCIE_VGA (18) CLK_PCIE_VGA# (18)

C

PE1_TX_P PE1_TX_N PE1_REFCLK_P PE1_REFCLK_N PE2_TX_P PE2_TX_N PE2_REFCLK_P PE2_REFCLK_N PE3_TX_P PE3_TX_N PE3_REFCLK_P PE3_REFCLK_N PE4_TX_P PE4_TX_N PE4_REFCLK_P PE4_REFCLK_N PE5_TX_P PE5_TX_N PE5_REFCLK_P PE5_REFCLK_N PE6_TX_P PE6_TX_N PE6_REFCLK_P PE6_REFCLK_N

M28 PCIE_MTX_PRX_P1 M29 PCIE_MTX_PRX_N1 T32 T31 M24 PCIE_MTX_PRX_P2 M25 PCIE_MTX_PRX_N2 T29 T30 M22 PCIE_MTX_PRX_P3 M23 PCIE_MTX_PRX_N3 T27 T28 M30 M31 T25 T26 P29 P28 T23 T24 P24 P25 P23 R23

EXPRESS@ C249 1 2 0.1U_0402_16V7K C248 1 2 0.1U_0402_16V7K EXPRESS@ MINI2@ C220 1 2 0.1U_0402_16V7K C219 1 2 0.1U_0402_16V7K MINI2@ MINI1@ C235 1 2 0.1U_0402_16V7K C234 1 2 0.1U_0402_16V7K MINI1@

PCIE_MTX_C_PRX_P1 PCIE_MTX_C_PRX_N1 CLK_PCIE_CARD CLK_PCIE_CARD# PCIE_MTX_C_PRX_P2 PCIE_MTX_C_PRX_N2 CLK_PCIE_MINI2 CLK_PCIE_MINI2# PCIE_MTX_C_PRX_P3 PCIE_MTX_C_PRX_N3 CLK_PCIE_MINI1 CLK_PCIE_MINI1#

PCIE_MTX_C_PRX_P1 (26) PCIE_MTX_C_PRX_N1 (26) CLK_PCIE_CARD (26) CLK_PCIE_CARD# (26) PCIE_MTX_C_PRX_P2 (25) PCIE_MTX_C_PRX_N2 (25) CLK_PCIE_MINI2 (25) CLK_PCIE_MINI2# (25) PCIE_MTX_C_PRX_P3 (25) PCIE_MTX_C_PRX_N3 (25) CLK_PCIE_MINI1 (25) CLK_PCIE_MINI1# (25)

NEW CARD

(25) PCIE_MRX_PTX_P2 (25) PCIE_MRX_PTX_N2 (25) MINI2_CLKREQ#

MINI_CARD(WLAN)

(25) PCIE_MRX_PTX_P3 (25) PCIE_MRX_PTX_N3 (25) MINI1_CLKREQ#

MINI_CARD(TV)

B

B

+3V 1

+1.2VS

L19 1 2 MBK1608121YZF_0603

C115 4.7U_0805_10V4Z 1

C105 0.1U_0402_16V4Z 1

P26 P27 U22 V30 +1.2V_PLL_PE_SS1 U19 U20

C267 0.1U_0402_16V4Z

2 B A P (15,31) HT_VLD HT_VLD PE_RST0# 2 1 5 U5 Y G 3 4 PCIE_RST# PCIE_RST# (18,26)

2

2

NC7SZ08P5X_NL_SC70-5 @

FOR VGA,LAN,NEW CARD

+1.2VS

L5 1 2 MBK1608121YZF_0603 C18 C104 L6 1 2 4.7U_0805_10V4Z 0.1U_0402_16V4Z MBK1608121YZF_0603 1 1 1 PEA_PRSNT# 2 PEB_PRSNT# PEC_PRSNT# C25 4.7U_0805_10V4Z 2 2 2

+1.2V_PLL_PE1

R20 R19

+1.2V_PLL_PE1 +1.2V_PLL_PE2

PEX_RST#

W30

PE_RST0# R170 1 2 0_0402_5%

MP 2007/4/12 AddedR550 R551A

+3VS

+3.3V_PLL_PE_SS1 1

P19 P20

+3.3V_PLL_PE_SS1 +3.3V_PLL_PE_SS2

PEX_RST1#

W29

R165 1

2 0_0402_5% PCIE_RST1#

PCIE_RST1# (25)

FOR MINI CARD

2 2 2

1 @ 1K_0402_1% 1 MINI2@ 1K_0402_1% 1 MINI1@ 1K_0402_1%

V24 1

PE_CLK_COMP MCP67-MV_PBGA836 @ R169 PCIE_RST1# 1 0_0402_5% 2 PCIE_RST#

C26 0.1U_0402_16V4Z 2

R552

R145 2.37K_0402_1% @

A

PEA_PRSNT# R553 PEB_PRSNT# R554 PEC_PRSNT# R555

1 1 1

EXP_CLKREQ# 0_0402_5% @ MINI2_CLKREQ# 0_0402_5% @ MINI1_CLKREQ# 2 0_0402_5% @ 2 2

Security Classification(14,26) CP_PE# 1 2 PEA_PRSNT# 0_0402_5% EXPRESS@

Compal Secret Data2006/08/18Deciphered Date

Issued Date

2007/8/18

Title

R563

MCP67 PCIE LINKSize Document Number Custom ICW50 / ICY70 Date:

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.3 2

LA-3581PSheet1

Rev 1.0 11 of 42

Friday, April 20, 2007

5

4

5

4

3

2

1

+3V

+3VMAC +3VMAC U23C RXD0 RXD1 RXD2 RXD3 RXCLK RXCTL 1 @ 1 C44 0.1U_0402_16V4Z RGMII_PWRDWN# 2 +3VMAC 2 R472 10K_0402_5% @ 2D

+1.2VALW

+3VMAC

1 R556 +3VAUX

2 @ 0_0805_5% +3VMAC +3VMAC (22) (22) (22) (22) (22) (22) R479 2 R321 2 RXD0 RXD1 RXD2 RXD3 RXCLK RXCTL B20 C20 E19 F19 G19 J20 C19 J18 D19 2 RGMII_INTR_R 0_0402_5% B18 N13 B17 C17 RGMII_RXD0/MII_RXD0 RGMII_RXD1/MII_RXD1 RGMII_RXD2/MII_RXD2 RGMII_RXD3/MII_RXD3 RGMII_RXC/MII_RXCLK RGMII_RXCTL/MII_RXDV MII_RXER/GPIO_36 MII_COL/MI2C_DATA MII_CRS/MI2C_CLK RGMII/MII_INTR/GPIO35 +3.3V_PLL_MAC_DUAL MII_COMP_3P3V MII_COMP_GND

MCP67 PART 3 OF 8

+3.3V_DUAL_RMGT +1.2V_DUAL_RMGT RGMII_TXD0/MII_TXD0 RGMII_TXD1/MII_TXD1 RGMII_TXD2/MII_TXD2 RGMII_TXD3/MII_TXD3 RGMII_TXCLK/MII_TXCLK RGMII_TXCTL/MII_TXEN RGMII/MII_MDC RGMII/MII_MDIO

L14 N18 J19 K19 L19 L18 H19 K18 K20 L20 D17 RGMII_PWRDWN# G17 C18 H20 R94 1 @ 2 +1.2VALW_MAC TXD0_R TXD1_R TXD2_R TXD3_R TXCLK_R TXCTL_R

R52 1 R79 1 R473 R471 R474 R475 R476 R477 1 1 1 1 1 1

0_0603_5% 2 0_0603_5% 2 2 2 2 2 2 2

LAN

1

1 R557D

2 0_0805_5%

1

40 mil

L9 MBK1608121YZF_0603 2 2

1 10K_0402_5% @ 10K_0402_5% @ RGMII_INTR_R 1 RGMII_INTR 1 R514

1 R478 10K_0402_5% 1 R69 1.47K_0402_1% 1 2 R61 1.47K_0402_1% 2 TXCLK_R 1 +3VS C658 33P_0402_50V8K @ L8 1 2 MBK2012121YZF_0805 TXCLK 1C C681 33P_0402_50V8K @

+3VMAC

22_0402_5% 22_0402_5% 22_0402_5% 22_0402_5% 33_0402_5% 22_0402_5%

TXD0 (22) TXD1 (22) TXD2 (22) TXD3 (22) TXCLK TXCTL (22) RGMII_MDC (22) RGMII_MDIO (22)

MP Modify 2007/04/13

C51 4.7U_0805_10V4Z 1 1

(22) RGMII_INTR R349 49.9_0402_1%

RGMII/MII_PWRDWN#/GPIO_37 BUF_25MHZ MII_RESET# MII_VREF

10K_0402_5% MII_RST (22) C40 0.1U_0402_16V4Z

2

1

1

1 R68 49.9_0402_1% R67 124_0402_1% 2 2

1

2 C53 0.1U_0402_16V4Z

MP Modify 2007/04/191 K21 D21 2 C55 0.01U_0402_16V7K 2 C103 R66 E23 124_0402_1% 0.01U_0402_16V7K H22 N15 E17 F17 1 1 2 RGB_DAC_RSET RGB_DAC_VREF TV_DAC_RSET TV_DAC_VREF +3.3V_PLL_DISP TV_XTALIN TV_XTALOUT

1

DACS

RGB_DAC_RED RGB_DAC_GREEN RGB_DAC_BLUE RGB_DAC_HSYNC RGB_DAC_VSYNC DDC_CLK0 DDC_DATA0 +3.3V_RGB_DAC

B21 C21 B22 G21 H21 G8 H8 E21

UMA_CRT_R UMA_CRT_G UMA_CRT_B

UMA_CRT_R (19) UMA_CRT_G (19) UMA_CRT_B (19) UMA_CRT_HSYNC UMA_CRT_VSYNC (19) (19)

2

+3.3V_PLL +3VC

+3V 1

+3V 1 R525 10K_0402_5% 1

NB_XTALIN NB_XTALOUT Y3 2 27MHZ_20P_7A27000010 1 UMA&TV@ C508 22P_0402_50V8J 2 UMA&TV@

C42 0.1U_0402_16V4Z 1

UMA_CRT_CLK (19) UMA_CRT_DATA (19) C36 1 4.7U_0805_10V4Z

1

2

R526 10K_0402_5% @ TXCLK

2

2 U40 1 2 3 CLKIN SS% GND NC NC VDD 8 7 6 5 1 C682

2 C61 C507 C66 2 22P_0402_50V8J 4.7U_0805_10V4Z 0.1U_0402_16V4Z UMA&TV@ U11 T11 +3.3V_TV_DAC GPIO_6/FERR//SYS_SERR/IGPU_GPIO_6* GPIO_7/NFERR//SYS_PERR/IGPU_GPIO_7* LCD_BKL_CTL LCD_BKL_ON LCD_PANEL_PWR HDMI_TXC_P HDMI_TXC_N HDMI_TXD0_P HDMI_TXD0_N HDMI_TXD1_P HDMI_TXD1_N HDMI_TXD2_P HDMI_TXD2_N HPLUG_DET3 HPLUG_DET2 HDCP_ROM_SCLK HDCP_ROM_SDATA +1.8V_IFPA +1.8V_IFPB +3.3V_IFPAB_HVDD +3.3V_HDMI_PLL_HVDD +3.3V_HDMI HDMI_RSET HDMI_VPROBE TV_DAC_RED TV_DAC_GREEN TV_DAC_BLUE IFPA_TXC_P IFPA_TXC_N IFPA_TXD0_P IFPA_TXD0_N IFPA_TXD1_P IFPA_TXD1_N IFPA_TXD2_P IFPA_TXD2_N IFPA_TXD3_P IFPA_TXD3_N IFPB_TXC_P IFPB_TXC_N IFPB_TXD4_P IFPB_TXD4_N IFPB_TXD5_P IFPB_TXD5_N IFPB_TXD6_P IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N DDC_CLK2 DDC_DATA2 DDC_CLK3 DDC_DATA3 F21 C23 C22 D23 AE30 AE31 AC30 AC29 AC27 AC28 AD30 AD29 AD31 AD32 AJ31 AJ32 AE28 AE29 AF30 AF31 AG30 AG29 AH31 AH30 L21 J22 L22 K22

C38 1 C58 1 0.1U_0402_16V4Z 4.7U_0805_10V4Z 2 2

2

2

UMA_TV_CRMA UMA_TV_LUMA UMA_TV_COMPS UMA_TXCLK+ UMA_TXCLKUMA_TXOUT0+ UMA_TXOUT0UMA_TXOUT1+ UMA_TXOUT1UMA_TXOUT2+ UMA_TXOUT2-

R527 10K_0402_5% 2

4

SSON CLKOUT

(20,27,28) DPST_PWM (18,27,28) ENBKL (20) UMA_ENVDD 0.1U_0402_16V4Z 2 TXCLK_PHY 22_0402_5%

2

1 R121

2 LCD_BKLT_EN 0_0402_5% UMA@

AD24 AE25 AE27 AL29 AM29 AK29 AJ29 AM30 AL30 AK30 AJ30 AE26 AL32 AD25 AC26 AC24 AC25 AC23 AC22 AH29 AK31 AK32

UMA_TV_CRMA (19) UMA_TV_LUMA (19) UMA_TV_COMPS (19) UMA_TXCLK+ (20) UMA_TXCLK- (20) UMA_TXOUT0+ UMA_TXOUT0UMA_TXOUT1+ UMA_TXOUT1UMA_TXOUT2+ UMA_TXOUT2(20) (20) (20) (20) (20) (20)

UMA_CRT_R UMA_CRT_G UMA_CRT_B

R63 1 R62 1 R64 1

1

UMA@ 2 150_0402_1% UMA@ 2 150_0402_1% UMA@ 150_0402_1% 2

S IC PCS3P23Z01DG-08-TR TSSOP 8P TXCLK_PHY_R 1 R528

TXCLK_PHY (22)

UMA_TV_CRMA UMA_TV_LUMA

R332 1 R324 1

TXCLK

1 R529

2 TXCLK_PHY_R 0_0402_5% @ +3VS +3VS

PVT Modify 2007/03/12

FLAT PANEL

UMA_TV_COMPS R325 1

UMA&TV@ 2 150_0402_1% UMA&TV@ 2 150_0402_1% UMA&TV@ 150_0402_1% 2

+1.8VS

+3VS

UMA_TZCLK+ UMA_TZCLKUMA_TZOUT0+ UMA_TZOUT0UMA_TZOUT1+ UMA_TZOUT1UMA_TZOUT2+ UMA_TZOUT2-

B

L25 MBK1608121YZF_0603 1 L24 MBK1608121YZF_0603 @ C210 4.7U_0805_10V4Z 1 1

L20 MBK1608121YZF_0603 L22 MBK1608121YZF_0603 2

R24 1 R138 1 R136 1

2 2 2

22K_0402_5% 6.2K_0402_5% 10K_0402_5%

UMA_TZCLK+ (20) UMA_TZCLK- (20) UMA_TZOUT0+ UMA_TZOUT0UMA_TZOUT1+ UMA_TZOUT1UMA_TZOUT2+ UMA_TZOUT2(20) (20) (20) (20) (20) (20)B

1

1

1

+3VS UMA@ R361 1 R359 1

+3VS

2

C190 1U_0402_6.3V4Z 1

2

2

2 2.7K_0402_5%

UMA_LCD_CLK

+1.8V_IFP_MCP C221 0.1U_0402_16V4Z 1 1 1 +3.3V_PLL_IFPP

2 2.7K_0402_5% UMA_LCD_DATA

UMA_LCD_CLK UMA_LCD_DATA DDC_DATA3

UMA_LCD_CLK (20) UMA_LCD_DATA (20) 1 2 10K_0402_5% DDC_DATA3

2

2

2

+3.3V_HDMI

R57 IFPAB_RSET IFPAB_PROBE 1 R372 1K_0402_1% 2 C528 @ 0.01U_0402_16V7K @ 2 1

C148 0.1U_0402_16V4Z

2 2 C211 4.7U_0805_10V4Z

2 C212 0.01U_0402_16V7K 1

IFPAB_RSET IFPAB_VPROBE

AB31 AB30

C178 4.7U_0805_10V4Z +3V +3V 1 +1.2VALW 2 1 R558 10K_0402_5% 2 3 S 1 1 2

1 MCP67-MV_PBGA836 R144 C160 1K_0402_1% 0.1U_0402_16V4Z 2 @ @

MP Modify 2007/04/13

2 C163 0.1U_0402_16V4Z

A

2

2

R559 20K_0402_1%

PVT Modify 2007/03/122 1 D D G Q62 AO3413_SOT23-3

PVT Modify 2007/03/12

A

2

1

(15,22) SLP_RMGT#

1

2

2 G 3 S

Q63 2N7002_SOT23 +1.2VALW_MAC

Security Classification1 C691 0.1U_0402_16V4Z 2

Compal Secret Data2006/08/18Deciphered Date

R560 0_0402_5%

Issued Date

2007/8/18

Title

MCP67 LAN/ CRT/ LVDSSize Document Number Custom ICW50 / ICY70 Date:

6 mil

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.3 2

LA-3581PSheet1

Rev 1.0 12 of 42

Friday, April 20, 2007

5

4

5

4

3

2

1

+3V RP3 +3VS SBPWR_EN# (34)

(23) PCI_REQ#0

8.2K_1206_8P4R_5%D

PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3 PCI_REQ#4

E10 G10 J10 M11 E8

PCI_REQ0# PCI_REQ1# PCI_REQ2#/GPIO_40/RS232_DSR# PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN#

PCI_GNT0# PCI_GNT1# PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS# PCI_GNT4#/GPIO_53/RS232_SOUT# PCI_CBE0# PCI_CBE1# PCI_CBE2# PCI_CBE3# PCI_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_PAR PCI_PERR#/GPIO_43/RS232_DCD# PCI_SERR# PCI_STOP# PCI_PME#/GPIO_30 PCI_RESET0# PCI_RESET1# PCI_RESET2# PCI_RESET3#

F10 H10 K10 L10 F8 K12 K13 F14 K16 L13 J14 H14 B14 J13 C13 B13 C16 J9 K9 K8 L9

PCI_GNT#0

PCI_GNT#0 (23)

PCI_PME#

OE#

1 2 3 4

8 7 6 5

PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3

5

1

U23D

MCP67 PART 4 OF 8

U32

P

2

A G 3

Y

4

EC_PME#

EC_PME# (27,28)

Internal PUPCI_CBE#[3..0] PCI_CBE#[3..0] (23)

SN74AHCT1G125DCKR_SC70-5 @

D

RP6 +3VS

1 2 3 4

8 7 6 5

PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#

(23) PCI_AD[31..0]

PCI_AD[31..0] PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 (23) PCI_PIRQE# (23) PCI_PIRQF# PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# PCI_TRDY# LPC_DRQ#1 LPC_DRQ#0 SERIRQ PM_CLKRUN# IDE_D0 IDE_D1 IDE_D2 IDE_D3 IDE_D4 IDE_D5 IDE_D6 IDE_D7 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15

8.2K_1206_8P4R_5%

RP5 +3VS

1 2 3 4

8 7 6 5

PCI_SERR# PCI_TRDY# PCI_FRAME# PCI_STOP#

8.2K_1206_8P4R_5%

RP4 +3VS

1 2 3 4

8 7 6 5

PCI_IRDY# PCI_PERR# PCI_DEVSEL#

8.2K_1206_8P4R_5%C

RP1 +3VS

1 2 3 4

8 7 6 5

PCI_REQ#4 PM_CLKRUN#

D10 B10 C10 L12 K11 J11 D11 C11 J12 H12 G12 F12 E12 D12 C12 B12 G14 E14 D14 J15 C14 D15 K15 C15 L16 G16 J16 E16 H16 D16 F16 A16 L17 J17 B16 K17 K14 C6 B6 D6 D5 AF10 AL9 AK8 AK7 AK6 AJ6 AL5 AL4 AJ5 AK5 AL6 AJ7 AJ8 AL8 AK9 AG10

PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ# PCI_TRDY# LPC_DRQ1#/GPIO19/FANRPM1 LPC_DRQ0#/GPIO_50 LPC_SERIRQ LPC_CLKRUN/GPIO_42 IDE_DATA_P0 IDE_DATA_P1 IDE_DATA_P2 IDE_DATA_P3 IDE_DATA_P4 IDE_DATA_P5 IDE_DATA_P6 IDE_DATA_P7 IDE_DATA_P8 IDE_DATA_P9 IDE_DATA_P10 IDE_DATA_P11 IDE_DATA_P12 IDE_DATA_P13 IDE_DATA_P14 IDE_DATA_P15 IDE_DREQ_P IDE_INTR_P IDE_RDY_P IDE_IOR_P# CABLE_DET_P/GPIO_63MCP67-MV_PBGA836

PCI

PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 PCI_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_PAR PCI_PERR# PCI_SERR# PCI_STOP# PCI_PME# R30 R33

+3VS

PCI_DEVSEL# (23) PCI_FRAME# (23) PCI_IRDY# (23) PCI_PAR (23) PCI_PERR# (23) PCI_SERR# (23) PCI_STOP# (23)

RP2 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

1 2 3 4

8 7 6 58.2K_1206_8P4R_5% @ 2 8.2K_0402_5% @ 2 8.2K_0402_5% @ 2 10K_0402_5% @

1 1PAD PAD

2 33_0402_5% 2 33_0402_5%T4 T5

PCI_RST1394# (23) PCIRST_IDE# (21)

LPC_DRQ#0 R38 LPC_DRQ#1 R72 SERIRQ R36 CLK_PCI_LPC_R

1 1 1

1 C37 10P_0402_50V8J@

2

PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLKIN

C9 B9 B8 A8 C8 D8

CLK_PCI_1394_R

R40

1

2 22_0402_5%

CLK_PCI_1394 (23)C

PCI_CLK4 PCI_CLKIN

R46

1

2 22_0402_5%

8.2K_1206_8P4R_5%

1 C31 1 10P_0402_50V8J C30 10P_0402_50V8J 2 2

JP35

1 3

(23) PCI_TRDY#

9/20 AddedLPC_FRAME# LPC_PWRDWN#/GPIO_54/EXT_NMI# D7 B3 C7 A4 B4 C4 A3 B5 C5 AG12 AE12 AH12 AJ12 AK12 AJ11 AJ10 AM4 AK4 1R51 121_0402_1% IDE_A0 IDE_A1 IDE_A2 IDE_CS1# IDE_CS3# IDE_DACK# IDE_IOW# R329 1 PAD T6 R54 R333 R328 R335 R311 CLK_PCI_LPC_R R59

NC NC CLK0

NC NC

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0

PCI_CBE#0 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16

5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 40 41 42 43

Debug Port

CLK1

2 22_0402_5%LPC_FRAME# 2 33_0402_5% 2 2 2 2 222_0402_5% 22_0402_5% 22_0402_5% 22_0402_5% 22_0402_5% LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME# (14,27,28) PLT_RST# (27,28)

LPC_DRQ#0 (23,27,28) SERIRQ (23,27,28) PM_CLKRUN#

LPC

LPC_RESET# LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_CLK0 LPC_CLK1 IDE_ADDR_P0 IDE_ADDR_P1 IDE_ADDR_P2 IDE_CS1_P# IDE_CS3_P# IDE_DACK_P# IDE_IOW_P# IDE_COMP_3P3V IDE_COMP_GND

1 1 1 1 1 1

LPC_AD0 (27,28) LPC_AD1 (27,28) LPC_AD2 (27,28) LPC_AD3 (27,28) CLK_PCI_LPC (27,28)

A3 A3 A3 A3 A3 A3 A3 A3 A2 A2 A2 A2 A2 A2 A2 A2 GND GND GND GND GND

A1 A1 A1 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 A0 A0 A0

B

IDE_A0 (21) IDE_A1 (21) IDE_A2 (21) IDE_CS1# (21) IDE_CS3# (21) IDE_DACK# (21) IDE_IOW# (21) +3VS

B

IDE

(21) IDE_D[15..0] (21) IDE_DREQ (21) IDE_IRQ (21) IDE_IORDY (21) IDE_IOR#

IDE_D[15..0]

1R29 121_0402_1%

IDE_IOR# 1 R362 2 R43

IDE_DREQ AK11 IDE_IRQ AH10 IDE_IORDY AK10 2 AL10 1 33_0402_5%AF12 15K_0402_5%

S W-CONN AMP 2-767004-2 38P @

9/21 Add 33ohm for IDE_IOR#

A

2

2

A

Security Classification Issued Date

Compal Secret Data2006/08/18Deciphered Date

2007/8/18

Title

MCP67 PCI/ LPC/ IDESize Document Number Custom ICW50 / ICY70 Date:

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

LA-3581PSheet1

Rev 1.0 13 of 42

Friday, April 20, 2007

5

4

3

2

1

PLACE SATA AC COUPLING CAPS CLOSE TO MCP67SATA_STX_C_DRX_P0 SATA_STX_C_DRX_N0 SATA_DTX_C_SRX_N0 SATA_DTX_C_SRX_P0 0.01U_0402_16V7K 1 0.01U_0402_16V7K 1 2 C512 C511 2 SATA_STX_DRX_P0 SATA_STX_DRX_N0

U23E

MCP67 PAR 5 OF 8AE4 AE5 AG5 AG6 SATA_A0_TX_P SATA_A0_TX_N SATA_A0_RX_N SATA_A0_RX_P USB0_P USB0_N USB1_P USB1_N USB2_P USB2_N USB3_P USB3_N U3 U2 U4 U5 U6 U7 V3 V2 W4 W3 W5 W6 W7 W8 Y2 Y3 AA3 AA2 AA5 AA4 AA7 AA6 AB3 AB2 AC3 AC4 T1

(21) SATA_STX_C_DRX_P0 (21) SATA_STX_C_DRX_N0 (21) SATA_DTX_C_SRX_N0 (21) SATA_DTX_C_SRX_P0

USB20_P0 USB20_N0 1 R343 USB20_P1 USB20_N1 1 R342 USB20_P2 USB20_N2 1 R84 USB20_P3 USB20_N3 1 R345 USB20_P4 USB20_N4 USB20_P5 USB20_N5 USB20_P6 USB20_N6 USB20_P7 USB20_N7 USB20_P8 USB20_N8 USB20_P9 USB20_N9 1 2 R347 15K_0402_5% CMOS@ 1 R353 BT@ 1 2 R360 15K_0402_5% MINI1@ 1 2 R352 15K_0402_5% MINI2@ 1 2 R350 15K_0402_5% EXPRESS@ 1 R351 @ 2 15K_0402_5% 1 R358 MINI1@ 1 2 R355 15K_0402_5% MINI2@ 1 2 R356 15K_0402_5% EXPRESS@ 1 R354 @ 2 15K_0402_5% 2 15K_0402_5% 1 2 R344 15K_0402_5% CMOS@ 1 R357 BT@ 2 15K_0402_5% 2 15K_0402_5% 2 15K_0402_5% 1 R348 2 15K_0402_5% 2 15K_0402_5% 1 R80 2 15K_0402_5% 2 15K_0402_5% 1 R341 2 15K_0402_5% 2 15K_0402_5% 1 R346 2 15K_0402_5%

USB20_P0 (26) USB20_N0 (26) USB20_P1 (26) USB20_N1 (26) USB20_P2 (25) USB20_N2 (25) USB20_P3 (25) USB20_N3 (25) USB20_P4 (20) USB20_N4 (20) USB20_P5 (30) USB20_N5 (30) USB20_P6 (25) USB20_N6 (25) USB20_P7 (25) USB20_N7 (25) USB20_P8 (26) USB20_N8 (26) USB20_P9 USB20_N9

USB PORT_1

D

USB PORT_1

D

AD1 AD2 AE2 AE3

SATA_A1_TX_P SATA_A1_TX_N SATA_A1_RX_N SATA_A1_RX_P

USB/B Connector USB/B Connector USB CAMERA

(21) SATA_STX_C_DRX_P1 (21) SATA_STX_C_DRX_N1 (21) SATA_DTX_C_SRX_N1 (21) SATA_DTX_C_SRX_P1

SATA_STX_C_DRX_P1 SATA_STX_C_DRX_N1 SATA_DTX_C_SRX_N1 SATA_DTX_C_SRX_P1

SATA2@ 0.01U_0402_16V7K 1 2 C514 0.01U_0402_16V7K 1 C513 2 SATA2@

SATASATA_STX_DRX_P1 SATA_STX_DRX_N1 AG4 AG3 AH3 AH2 SATA_B0_TX_P SATA_B0_TX_N SATA_B0_RX_N SATA_B0_RX_P

USB

USB4_P USB4_N USB5_P USB5_N USB6_P USB6_N

BLUETOOTH

MINI1

+3VS

JUMPER HDA_SDOUT10K_0402_5% HDA_SDOUT_ICH 2 10K_0402_5% @ 2 10K_0402_5% LPC_FRAME# 2

LPC_FRAME

C

R320 1 R319 1 R44 1 R41 1

10K_0402_5% 2

@

AG7 AG8 AF2 AF3

SATA_B1_TX_P SATA_B1_TX_N SATA_B1_RX_N SATA_B1_RX_P

USB7_P USB7_N USB8_P USB8_N

MINI2

NEW CARDC

FUNCTIONAL1 AL2 RESERVED/SATA_C0_TX_P RESERVED/SATA_C0_TX_N RESERVED/SATA_C0_RX_N RESERVED/SATA_C0_RX_P

LPC_FRAME# (13,27,28)

USB9_P USB9_N RESERVED/USB10_P RESERVED/USB10_N RESERVED/USB11_P RESERVED/USB11_N

NON-USE

"0" "0"+3VS

"0" "1" "0" "1"

LPC BIOS* PCI BIOS

AK3 AL3

+3V 1 1 USB_OC#4 10K_0402_5% USB_OC#3 10K_0402_5% 2 HDA_RST_ICH# 10K_0402_5% 2 2 HDA_SYNC_ICH 10K_0402_5%

"1"1 R35 10K_0402_5%

SPI BIOS RESERVED

AJ1 AJ2 AK1 AK2

RESERVED/SATA_C1_TX_P RESERVED/SATA_C1_TX_N RESERVED/SATA_C1_RX_N RESERVED/SATA_C1_RX_P RESERVED RESERVED USB_RBIAS_GND

R86 R87 1 R338 1.1K_0402_1% 2 +3V USB_OC#0 (26) USB_OC#1 (25) CP_PE# (11,26) USB_OC#3 USB_OC#4

"1"

*DEFAULTSATA_LED# 1 R108 2 2.49K_0402_1% SATA_LED# AJ4 SATA_TERMP

2

1 R316

(27,28) SATA_LED#

D4

SATA_LED#/GPIO_57

USB_OC0#/GPIO_25 USB_OC1#/GPIO_26 USB_OC2#/GPIO_27 USB_OC3#/GPIO_28/MGPIO_1 USB_OC4#/GPIO_29/MGPIO_3 +3.3V_USB_DUAL1 +3.3V_USB_DUAL2

T2 T3 T4 T5 T6 Y8 Y9

1 R313 1 C57 0.1U_0402_16V4Z 1 C63 0.1U_0402_16V4Z

2

+3VS

+3VS

2

2

B

U36 1 HDA_BITCLK_ICH_R R459 10K_0402_5% @ 2 1 2 8 3 1 R460 10K_0402_5% @ 2 CLKIN NC NC SS VDD CLKOUT SSON GND 7 6 5 4

+1.2V_PLL_SP_VDD +1.2VS HDA_BITCLK_ICH 1 C640 0.1U_0402_16V4Z 2 1 +3.3V_PLL 2 C140 0.1U_0402_16V4Z

W13 V13 R13 P13

+1.2V_PLL_SP_VDD +1.2V_PLL_SP_SS +3.3V_PLL_SP_SS +3.3V_PLL_LEG HDA_SDATA_OUT/GPIO_45 HDA_SDATA_IN0/GPIO_22 HDA_SDATA_IN1/GPIO_23/MGPIO_0 HDA_SDATA_IN2/GPIO_24/MGPIO_2 HDA_RESET# B1 B2 A2 D1 C2 C1 D3 C3 HDA_SDOUT_ICH 1 22_0402_5% HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_RST_ICH# 1 22_0402_5% HDA_SYNC_ICH 1 22_0402_5% 2 R318 HDA_SDOUT_MDC HDA_SDIN0 HDA_SDIN1 (30) HDA_BITCLK_ICH HDA_SYNC_ICH HDA_RST_ICH# HDA_SDOUT_ICH C23 C17 10P_0402_50V8J 10P_0402_50V8J 1 @ 1 @ 1 C22 1

B

HDA

HDA_BITCLK

D2

HDA_BITCLK_ICH_R

HDA_BITCLK_ICH 1 33_0402_5%

2 R314

HDA_BITCLK_MDC

(30)

ASM3P623S00CF-08TR_TSSOP8 @

(32) (30)

2 R315 2 R312

HDA_RST_MDC# (30) 2 HDA_SYNC_MDC (30) 2 2 2 C20 10P_0402_50V8J 10P_0402_50V8J

HDA_BITCLK_ICH_R 1 R461

2

HDA_BITCLK_ICH 0_0402_5%

HDA_SYNC/GPIO_44 HDA_DOCK_EN#/GPIO_51 HDA_DOCK_RST#/GPIO_46

+1.2VS

+1.2V_PLL_SP_VDD

+3VS

+3.3V_PLL

MCP67-MV_PBGA836 C149 0.1U_0402_16V4Z 1 1

A

L10 1 2 MBK1608121YZF_0603 1 C54 10U_0805_10V4Z 1

L14 1 2 MBK1608121YZF_0603

C145 4.7U_0805_10V4Z 1 1

HDA_BITCLK_ICH 1 33_0402_5% HDA_SYNC_ICH 1 22_0402_5% HDA_RST_ICH# 1 22_0402_5% HDA_SDOUT_ICH 1 22_0402_5%

2 R25 2 R23 2 R26 2 R27

HDA_BITCLK_AUDIO HDA_SYNC_AUDIO HDA_RST_AUDIO# HDA_SDOUT_AUDIO

(32) (32) (32) (32)A

2

2 C50 0.1U_0402_16V4Z

2

2

2

2 C153 0.1U_0402_16V4Z

Security Classification Issued Date

Compal Secret Data2006/08/18Deciphered Date

2007/8/18

Title

C143 0.1U_0402_16V4Z

MCP67 SATA/ USB/ HDAUDIOSize Document Number Custom ICW50 / ICY70 Date:

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.3 2

LA-3581PSheet1

Rev 1.0 14 of 42

Friday, April 20, 2007

5

4

5

4

3

2

1

+3V

+3V

R469 R470 R78 R53 1 1 LID# 2 100K_0402_5% LLB# 2 10K_0402_5% @

1 1

2 EC_LID_OUT# 10K_0402_5% @ 2 CRT_DET 10K_0402_5% @

CRT_DET R445

2

1 @ 100K_0402_5%

+3V +3VS

U23F IDE_HRESET# 2 0_0402_5% 2 0_0402_5%

D

MCP67 PAR 6 OF 8@ P6 N11 R11 M9 M10 GPIO_1/PWRDN_OK/SPI_CS1 GPIO_2/NMI/PS2_CLK0 GPIO_3/SMI#/PS2_DATA0 GPIO_4/SCI/INTR/PS2_CLK1 GPIO_5/INIT#/PS2_DATA1 GPIO_12/SUS_STAT# SLP_S3# SLP_RMGT# SLP_S5# MCP_VID0/GPIO_13 MCP_VID1/GPIO_14 MCP_VID2/GPIO_15 R3 P3 R4 H5 H6 H7

MCP_SPKR R101 PM_SLP_S3# SLP_RMGT# PM_SLP_S5# PM_SLP_S3# (27,28) SLP_RMGT# (12,22) PM_SLP_S5# (27,28) R104

1 1

(18,27,28,37) ACIN

(27,28) EC_LID_OUT# +RTCVCC

EC_LID_OUT# R464

1

2

0_0402_5%

RI# @

1

2 R542 @

(21) IDE_HRESET# @ (27,28) EC_SWI# D24 (27,28) EC_SMI# RB751V_SOD323 ACIN_R 1 2 1 20K_0402_1%

R92 R97

1 1

2 10K_0402_5% 2 10K_0402_5%

D

@

M4 R283 470K_0402_5% @ 2

1

R340 1M_0402_5% (27,28) EC_GA20 (27,28) EC_KBRST# (27,28) EC_SCI# (27,28) EC_SMI#

MP Modify 2007/04/12R91 R96 1 1 2 0_0402_5% 2 0_0402_5% EC_GA20 EC_KBRST# SIO_PME# EXT_SMI# RI# SM_INTRUDER# K7 K6 M6 P4 P8 L3 A20GATE/GPIO_55 KBRDRSTIN#/GPIO_56 SIO_PME#/GPIO_31 EXT_SMI#/GPIO_32 RI#/GPIO33 INTRUDER#

MSIC

SPKR

K4

MCP_SPKR

MCP_SPKR (32)

Q10 2N7002_SOT23 M_SMBCLK 1 3 MEM_SMBCLK D S MEM_SMBCLK (8,9)

SMB_CLK0 SMB_DATA0 SMB_CLK1/MSMB_CLK SMB_DATA1/MSMB_DATA SMB_ALERT#/GPIO_64

2

E3 G3 E2 F2 F3

SMBCLK1 SMBDATA1 M_SMBCLK M_SMBDATA SMB_ALERT#

SMBCLK1 (25,26) SMBDATA1 (25,26)

2 G

+3VS 2 G M_SMBDATA

1

R93 49.9K_0402_1%

(19) CRT_DET

R463 CRT_DET 1

2

0_0402_5% LID# 2 LLB# C29 1U_0603_10V4Z 1 2 PBTN_OUT# 1 RSTBTN# 10K_0402_5%

P5 N10

D

LID# LLB# THERM_SIC/GPIO_48 THERM_SID0/GPIO_49 THERM_SID1/GPIO_47/PWR_LED# PWRBTN# RSTBTN# RTC_RST# PWRGD_SB PWRGD MEM_VLD MCP_VLD/HT_VLD CPU_VLD JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST# JTAG_TCK FANRPM0/GPIO_60 FANCTL0/GPIO_61 FANCTL1/GPIO_62 F6 F5 F4 1 R438 2 15K_0402_5% +3V R65 R70 R34 MCPVDD_EN/HTVDD_EN CPUVDD_EN N3 M2 ACIN_L SPI_CS0/GPIO_10 SPI_CLK/GPIO_11 SPI_DI/GPIO_8 SPI_DO/GPIO_9 K2 K3 M7 J2 VLDT_EN (34) VR_ON (41) +3VS R73 R60 ACIN (18,27,28,37) 2 10K_0402_5% 2 10K_0402_5% @ @ +3V AC14 AB14 AD12 CPU_SIC (6) CPU_SID (6)

2N7002_SOT23 Q9C

C

PVT Modify 2007/03/12Close To RAM DoorJ1 2 1 @ JOPEN (27,28) (6,18,27,28) (31,40) (11,31) (41) EC_RSMRST# MCP_PWRGD MEM_VLD HT_VLD VGATE EC_RSMRST# MEM_VLD HT_VLD (27,28) PBTN_OUT# +3V R90 2 R10 P9 M5 L4 T10 M8 P7 M3 U9 T8 T7 U8 T9

S

THERM#/GPIO_59

K5

EC_THERM# (6,27,28)

1

3

MEM_SMBDATA

MEM_SMBDATA (8,9)

1 1 1 1 1

C60 1U_0603_10V4Z 1 2

SMBCLK1 2.7K_0402_5% SMBDATA1 2.7K_0402_5% 2 SMB_ALERT# 2.7K_0402_5% 2 2 2 2 M_SMBCLK 2.7K_0402_5% M_SMBDATA 2.7K_0402_5%

D29 RB751V_SOD323 2 1 R74 R56 1 1

2 10K_0402_5%2 10K_0402_5%

1 1

R81 R95

1 R543

ACIN_L 2 470K_0402_5%

XTALIN XTALOUT X1 1 1B

H4 H3

SUS_CLK/GPIO_34 XTALIN XTALOUT BUF_SIO_CLK

P2

R339

1

2 10K_0402_5%

@

MP Modify 2007/04/12

2 1 C35 27P_0402_50V8J C503 18P_0402_50V8J 2 1 X2 2 3 NC NC IN OUT 1 4 J3 1 C16 10P_0402_50V8J @ TEST_MODE_EN PKG_TEST MCP67-MV_PBGA836 P11 P10 2 +3VS R540 1 R541 1 2.2K_0402_5% 2 MEM_SMBCLK 2.2K_0402_5% 2 MEM_SMBDATAB

2

25MHZ_20P C34 27P_0402_50V8J

2

XTALIN_RTC @ R334 10M_0402_5% 1 2

H2 H1

XTALIN_RTC XTALOUT_RTC

9/25 Added for EMI1 1 R71 0_0402_5% 2 2 R100 1K_0402_1%

32.768KHZ_12.5P_MC-306 2 1 18P_0402_50V8J C504

XTAOUT_RTC

PVT Modify 2007/03/23

A

A

Security Classification Issued Date

Compal Secret Data2006/08/18Deciphered Date

2007/8/18

Title

MCP67 MISCSize Document Number Custom ICW50 / ICY70 Date:

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

LA-3581PSheet1

Rev 1.0 15 of 42

Friday, April 20, 2007

5

4

3

2

1

C152 10U_0805_10V4Z 1 1

C527 4.7U_0805_10V4Z 1 1

C73 0.1U_0402_16V4Z 1 1

C100 0.1U_0402_16V4Z 1 1

C114 0.1U_0402_16V4Z 1 1

+1.2VS

U23GD

2

2

2

2

2

2

2

2

2

2D

MCP67 PART 7 OF 8V15 V16 W16 W15 C107 0.1U_0402_16V4Z 1 1 R77 0_0603_5% 2 1 1 C48 0.1U_0402_16V4Z 1 1 C39 0.01U_0402_16V7K 1 +1.2V_RBB1 +1.2V_RBB2 +1.2V_RBB3 +1.2V_RBB4 +1.2V1 +1.2V10 +1.2V11 +1.2V12 +1.2V13 +1.2V14 +1.2V15 +1.2V16 +1.2V17 +1.2V18 +1.2V19 +1.2V2 +1.2V20 +1.2V21 +1.2V22 +1.2V23 +1.2V24 +1.2V25 +1.2V26 +1.2V27 +1.2V28 +1.2V29 +1.2V3 +1.2V4 +1.2V5 +1.2V6 +1.2V7 +1.2V8 +1.2V9 +1.2V_HT1 +1.2V_HT2 +1.2V_HT3 +1.2V_PED1 +1.2V_PED2 +1.2V_PED3 +1.2V_PED4 +1.2V_PED5 +1.2V_PEA1 +1.2V_PEA2 +1.2V_PEA3 +1.2V_PEA4 +1.2V_PEA5 +1.2V_PEA6 +1.2V_PEA7 +1.2V_PEA8 +1.2V_SP_D1 +1.2V_SP_D2 +1.2V_SP_D3 +1.2V_SP_D4 +1.2V_SP_A1 +1.2V_SP_A2 +1.2V_SP_A3 +1.2V_SP_A4 +1.2V_SP_A5 +1.2V_DUAL1 +1.2V_DUAL2 AA22 V19 W20 Y20 Y19 V17 AB21 AA23 Y30 U17 U18 Y31 W17 Y18 U16 AA24 V18 AA25 AA26 AB22 W18 AB23 AA27 AA28 AA29 W19 AA30 AA31 V20 Y15 Y17 Y16 V23 W25 W24 V22 W26 Y22 Y23 Y27 Y29 Y25 W22 W23 Y24 AE8 AE7 AE9 AE6 AB11 AB10 AD10 AC10 AE10 N16 N17 +1.2V_PED +1.2V_PEA 1 C526 150U_D2_6.3VM 1 1 + 2 2

C525 C74 C108 C109 C120 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C147 C125 C132 C131 C134 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 1 1 1 1 1 1

+3V

+3VS

POWER

AJ9 AG9 F11 H11

2

2

2

2

2

2

2

2

2

2 C144 0.1U_0402_16V4Z

+3.3V1 +3.3V2 +3.3V3 +3.3V4

C151 22U_0805_6.3V6M

C159 4.7U_0805_10V4Z

C130 0.1U_0402_16V4Z

C135 0.1U_0402_16V4Z

C139 0.1U_0402_16V4Z

2 2 C102 0.1U_0402_16V4Z

2 2 C110 0.1U_0402_16V4Z

2 2 C47 0.1U_0402_16V4Z +3.3V_DUAL1 +RTCVCC

L6 L8

+3.3V_DUAL1 +3.3V_DUAL2

+1.2V_HT 1

C45 0.1U_0402_16V4Z 1 1

N2 C506 0.1U_0402_16V4Z 1

+3.3V_VBAT

C106 0.1U_0402_16V4Z +1.2V_HT1 2

R102 0_0603_5%

+1.2VS

+1.2VS

2 2 C41 0.1U_0402_16V4ZC

1 C529 150U_D2_6.3VM +@ C121 0.1U_0402_16V4Z 1 1 C124 0.1U_0402_16V4Z 1 1 2C

2

RTC Battery

2

BATT1

+1 +RTCBATT

+RTCBATT

Update FootprintML1220T13RE 45@ 1

R539 1K_0402_1%

PVT Modify 2007/03/221 D22 BAS40-04_SOT23-3 +RTCVCC 3 2

+CHGRTCB

1 C519 4.7U_0805_10V4Z

1 C520 0.1U_0402_16V4Z

2

2

AD9 AH6 AE32 Y32 AD8 M32 AE18 AB25 AB27 U15 AE11 V27 R27 N27 G27 Y14 F15 V29 AC12 AB19 AM9 AB12 AM8 AF8 AH4 E27 AM31 F22 AF4 AM32 AG11 L15 AD27 P22 AD11 V11 L23 P15

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

1

1 C67 1U_0402_6.3V4Z 2

+1.2VS L17 KC FBM-L11-201209-221LMAT_0805

2

2

2

C117 0.1U_0402_16V4Z 1

C128 0.1U_0402_16V4Z 1 1

C156 4.7U_0805_10V4Z 1 1

1 R110 0_0805_5% 2 C119 1 1 10U_0805_10V4Z 2 C118 4.7U_0805_10V4ZB

2 2 C112 0.1U_0402_16V4Z

C189 10U_0805_10V4Z 1 1

2

2 2 C123 0.1U_0402_16V4Z

2 2 C126 1U_0402_6.3V4Z

2 2 C157 22U_0805_6.3V6M

2 C162 10U_0805_10V4Z

2

+1.2V_SP_D C68 1 1 0.01U_0402_16V7K 2

C111 1 1 10U_0805_10V4Z

+1.2VS

C71 1 1 0.1U_0402_16V4Z 2

2 2 C62 0.1U_0402_16V4Z L12 1 C518 1 1 4.7U_0805_10V4Z

2 C116 10U_0805_10V4Z 2 MBK2012121YZF_0805

2 2 C72 0.1U_0402_16V4Z

+1.2V_SP_A C75 1 1 0.1U_0402_16V4Z 2

MCP67-MV POWER STATESPower Signal S0 ON ON ON O


Service Manual Acer Aspire 7520 7220 Series

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BIOL 4605/7220

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