Scalar Processor Report
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Transcript of Scalar Processor Report
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Click to edit Master subtitle style8/1/12
SCALARPROCESSOR
Computer Architecture and OperatingSystem
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11Master of Science in Information Technology
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Definition
Scalar processors arethose executing one
instruction per cycle, onlyone instruction is issued
per cycle and only onecompletion of instruction isexpected from the pipeline
per cycle 8/1/12
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Scalar Processor
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ARCHITECTURAL
OVERVIEW
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A scalar processor logicallyconsists of an integer unit
(IU) and a floating-point unit(FPU), each with its ownregisters. This organization
allows for implementationswith concurrency betweeninteger and floating-pointinstruction execution.
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INTEGER UNIT
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contains the general-purposeregisters and controls the overall
operation of the processor. The IUexecutes the integer arithmeticinstructions and computes
memory addresses for loads andstores. It also maintains theprogram counters and controlsinstruction execution for
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DEFINITION OF TERM
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A request by a processorto replace the value of a
specified memory location.The address and new value
are bound to the storetransaction when theprocessor initiates the store
transaction.
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DEFINITION OF TERM
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A request by a processorto retrieve the value of
the specified memorylocation. The address is
bound to the loadtransaction when the
processor initiates the
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FLOATING- POINT UNIT
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A processing unit thatcontains the floating-point
registers and performsfloating-point operations.
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REGISTERS
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includes two types ofregisters: general-purpose, or
working data registers, andcontrol/status registers
Working registers include:
Integer working registers (rregisters)
Floatin - oint workin
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Control/ Status Registers
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1010 Program Counter register (PC)
Next Program Counter register (nPC)
Trap Base Address register (TBA)
Y register (Y)
Processor Interrupt Level register (PIL)
Current Window Pointer register (CWP)
Trap Type register (TT)
Condition Codes Register (CCR)
Address Space Identifier register (ASI)
Trap Level register (TL)
Trap Program Counter register (TPC)
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CONTROL STATUSREGISTERS
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1111 Other windows register (OTHERWIN)
Clean windows register (CLEANWIN)
Window State register (WSTATE)
Version register (VER)
Implementation-dependent Ancillary State Registers(ASRs)
Implementation-dependent IU Deferred-Trap Queue(impl. dep. #16)
Floating-Point State Register (FSR)
floating-Point Registers State register (FPRS)- - -
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THE USE OF A LARGEREGISTER FILE
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The register file is physicallysmall, on the same chip as theALU and control unit, andemploys much shorter addressesthan addresses for cache andmemory. Thus, a strategy isneeded that will allow the mostfrequently accessed operands tobe kept in registers and tominimiz r i t r- m m r
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