Processor Report Final

8/9/2019 Processor Report Final

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5 STAGE PIPELINED PROCESSOR DESIGN

(Bossolo Nera)

Submitted by

ars!ad Golat"ar Ro!it Ro"ade

Rites! Sarode Sa#$o% Patil


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dersta#di#% t!e Problem

' Pro essor Pi*eli#i#%

The processor we aim to design is 5 stage pipelined processor. Instruction pipelining is a technique used

to increase the throughput of a processor. I# a *ro essor +it!out *i*eli#i#%, all t!e i#stru tio#s arearried out i# a si#%le lo " y le But t!e duratio# o- o#e lo " y le is mu ! %reater t!a# t!at i#

a *i*eli#ed ar !ite ture

It is also observed that when we do not use pipelining, a lot of hardware is sitting idly until theinstruction execution is over. Pipeline breaks the instruction execution into several stages. Thus, insuringthat instructions move along the datapath, one stage at a time, through all stages no hardware remainsidle during execution. The P! "program counter# is updated at every clock cycle. $ext instruction beginslong before the previous instruction is finished. To keep the pipeline moving along at a uniform speed,each pipeline stage is given the same amount of time "one clock cycle#. This is made to be long enough

so that each pipeline stage can complete in this time. In an efficient pipeline, one instruction finishes ateach clock cycle.

I# a *i*eli#ed ar !ite ture, a-ter -irst i#stru tio# is su ess-ully e.e uted, +e %et out*ut(i#stru tio# e.e utio#) at e/ery lo " y le T!us *i*eli#i#% drasti ally im*ro/es t!e 0t!rou%!*ut1(rate at +!i ! out*ut is *rodu ed) o- a *ro essor

A *i*eli#ed ar !ite ture allo+s us to *er-orm multi*le o*eratio#s at same time but it may #otredu e t!e late# y o- a *ro essor (time bet+ee# i#*ut 2 out*ut) It may i# -a t, i# rease t!elate# y as t!e i#stru tio# %oes t!rou%! all t!e sta%es 2 ea ! sta%e re3uires a time *eriod o- o#e

lo " y le%ur processor is a 5 stage pipelined processor. The five different stages are&

I4 & instruction fetched from instruction memory

ID & instruction decoded and register read

E E & '() execution

6E6 & data memory read or write

7B & write result back into a register


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4i/e di--ere#t sta%es i# a *i*eli#e

The instruction passes through all 5 stages. This is illustrated in the diagram below

I#stru tio# -lo+ t!rou%! a *i*eli#e

's seen in the diagram above when the first instruction passes from I* stage to I+ stage, nd instructionenters I* stage. Thus every instruction passes through every stage until it-s execution is complete. henthe first instruction reaches final stage, 5 th instruction is being fetched. This shows the increase inthroughput.

There are pipeline registers between each stage. These registers are very important as they hold thevalues for the duration of clock cycle. They pass these values to the next stage at every clock cycle. *or e.g., The I*/I+ pipeline register contains the fetched instruction "one word#. The I+/'() contains thefetched instruction, plus control signals that are needed to execute the instruction so on.


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e have to design our processor in such a way that it follows all the criteria required for a pipelined processor. e also have to take care of 0 a8ards1 which occur in a pipelined architecture.

9 Deali#% +it! a8ards

In a non0 pipelined processor, one instruction begins after the execution of the previous instruction. Thatis not the case in a pipelined architecture. 1ere, many instructions are present simultaneously in differentstages of processor. These instructions may be dependent on each other. If that is the case, then theinstruction will not be executed correctly. This can be shown with following example&

'++ 23 24 2

'++ 2 24 23

1ere, the result of addition of 24 2 is stored in 23. The next instruction uses 23 as one of theoperand. $ow, due to pipelining, when instruction 4 is executed, instruction is in I+ stage. hen

instruction enters execute stage the result of instruction 4 is not yet written back in register file. Thusthe value taken for addition "23# will be an old value which will produce incorrect result.

This problem could be solved by stalli#% t!e *i*eli#e i.e. second instruction is stalled until result of first instruction is written back. 6ut this defeats the purpose of pipelining as the hardware remains idleduring execution. This approach also fails to improve the throughput of processor.

' better way is to use data -or+ardi#% approach. In this, the new data obtained after execute stage isforwarded so that it is available for the execute stage of next instruction.

A/oidi#% !a8ard by data -or+ardi#%

e have to design our processor in such a way that most of the probable ha7ards are avoided.


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: I#stru tio#s

The processor should be able to carry out ;< di--ere#t i#stru tio#s These include arithmeticinstructions, logical instructions, load/store instructions.

8emory can be accessed only by specific instructions "load, store#. 9very instruction is of fixed length"4: bit#. Thus our processor architecture characteristics are similar to 2I;! architecture.

The instruction format for our processor will be&

%pcode"< bits#

=45&4 >

!ontrol bit"4 bit#

=44>

2econfiguration bit" bits#

=43&?>

+estination" bits#

=@&:>

;ource 4" bits#

=5& >

;ource /8em" bits#

= &3>

I#stru tio# -ormat


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De/isi#% a Pla#=Desi%#

In order to design a processor, we must know the datapath that will be followed by all the instructions.Then, we must combine the different datapaths into a single datapath. *urthermore, we must also takeinto account the ha7ard. 9xtra hardware datapath will be required for overcoming these ha7ards.

6efore designing a datapath, we should assign 4: bit instruction opcode for every instruction. Theopcode cannot be assigned randomly. It should be assigned in such a manner that it is helpful duringhardware design assigning of control signals.

*ollowing table shows the instruction set opcode of our processor

' I#stru tio# set -or 0Bossolo Nera1

Type *unction $ame %pcode !trl4 bit

2econfig bit

+es bit

;rc4 ;rc /8em

'ddition +est=45&3> A;rc4=45&3>B;rc =45&3>

'++ 3333 C 33 =dest> =src4> =src >

+est=45&@> A;rc4=45&@>B;rc =45&@>

'++1 3333 C 34 =dest> =src4> =src >

+est=D&3> A;rc4=D&3>B;rc =D&3>

'++( 3333 C 43 =dest> =src4> =src >

;ubtraction +est=45&3> A;rc4=45&3>B;rc =45&3>

;)6 3334 C 33 =dest> =src4> =src >

+est=45&@> A;rc4=45&@>B;rc =45&@>

;)61 3334 C 34 =dest> =src4> =src >

+est=D&3> A;rc4=D&3>B;rc =D&3>

;)6( 3334 C 43 =dest> =src4> =src >

Increment +est=45&3> A;rc4=45&3>B4

I$! 3343 C 33 =dest> =src4> CCC

+est=45&@> A;rc4=45&@>B4

I$!1 3343 C 34 =dest> =src4> CCC


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+est=D&3> A;rc4=D&3>B4

I$!( 3343 C 43 =dest> =src4> CCC

+ecrement +est=45&3> A;rc4=45&3>04

+9! 3344 C 33 =dest> =src4> CCC

+est=45&@> A;rc4=45&@>04

+9!1 3344 C 34 =dest> =src4> CCC

+est=D&3> A;rc4=D&3>04

+9!( 3344 C 43 =dest> =src4> CCC

'$+

$'$+

%perations

+est=45&3> A;rc4=45&3> ;rc =45&3>

'$+ 3433 3 33 =dest> =src4> =src >

+est=45&@> A;rc4=45&@> ;rc =45&@>

'$+1 3433 3 34 =dest> =src4> =src >

+est=D&3> A;rc4=D&3> ;rc =D&3>

'$+( 3433 3 43 =dest> =src4> =src >

+est=45&3> A;rc4=45&3>E ;rc =45&3>

$'$+ 3433 4 33 =dest> =src4> =src >

+est=45&@> A;rc4=45&@>E ;rc =45&@>

$'$+1 3433 4 34 =dest> =src4> =src >

+est=D&3> A;rc4=D&3>E ;rc =D&3>

$'$+( 3433 4 43 =dest> =src4> =src >

%2

$%2

%perations

+est=45&3> A;rc4=45&3> F ;rc =45&3>

%2 3434 3 33 =dest> =src4> =src >

+est=45&@> A;rc4=45&@> F ;rc =45&@>

%21 3434 3 34 =dest> =src4> =src >

+est=D&3> A;rc4=D&3> F ;rc =D&3>

%2( 3434 3 43 =dest> =src4> =src >

+est=45&3> A;rc4=45&3> EF ;rc =45&3>

$%2 3434 4 33 =dest> =src4> =src >


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+est=45&@> A;rc4=45&@> EF ;rc =45&@>

$%21 3434 4 34 =dest> =src4> =src >

+est=D&3> A;rc4=D&3> EF ;rc =D&3>

$%2( 3434 4 43 =dest> =src4> =src >

9C%2

9C$%2

%perations

+est=45&3> A;rc4=45&3> G ;rc =45&3>

9C%2 3443 3 33 =dest> =src4> =src >

+est=45&@> A;rc4=45&@> G ;rc =45&@>

9C%21 3443 3 34 =dest> =src4> =src >

+est=D&3> A;rc4=D&3> G ;rc =D&3>

9C%2( 3443 3 43 =dest> =src4> =src >

9C%2

9C$%2

%perations

+est=45&3> A;rc4=45&3> EG ;rc =45&3>

9C$%2 3443 4 33 =dest> =src4> =src >

+est=45&@> A

;rc4=45&@> EG ;rc =45&@>

9C$%21 3443 4 34 =dest> =src4> =src >

+est=D&3> A;rc4=D&3> EG ;rc =D&3>

9C$%2( 3443 4 43 =dest> =src4> =src >

6uffer

%perations

+est=45&3> A src=45&3> 29P 3444 3 33 =dest> =src4> CCC

+est=45&@> A src=45&@> 29P1 3444 3 34 =dest> =src4> CCC


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+est=D&3> A src=D&3> 29P( 3444 3 43 =dest> =src4> CCC

Inversion

%perations

+est=45&3> A Esrc=45&3> $%T 3444 4 33 =dest> =src4> CCC

+est=45&@> A Esrc=45&@> $%T1 3444 4 34 =dest> =src4> CCC

+est=45&3> A Esrc=45&3> $%T( 3444 4 43 =dest> =src4> CCC

8ultiply

%peration

+est=45&3> A;rc4=D&3>Hsrc =D&3>

8)(( 4333 3 CC =dest> =src4> =src >

+est=45&3> A;rc4=45&@>Hsrc =45&@>

8)(1 4333 4 CC =dest> =src4> =src >

;hift

%peration

+est A left shift"src4# ;1( 4334 3 CC =dest> =src4> =shift val>

+est A right shift"src4# ;12 4334 4 CC =dest> =src4> =shift val>

(oad +est A mem (+2 4344 3 CC =dest> CCC =mem>

;tore 8em A src4 (+2 4344 3 CC CCC =src4> =mem>

8% 9+est=45&3> A src=45&3> 8% 4434 3 33 =dest> =src4> CCC


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%perations +est=45&@> A src=45&@> 8% 1 4434 3 34 =dest> =src4> CCC

+est=D&3> A src=D&3> 8% ( 4434 3 43 =dest> =src4> CCC

8% 9

Immediate

%perations

+est=45&@> A src=45&@> 8 I1 4434 4 34 JC, @ bit dataK

+est=D&3> A src=D&3> 8 I1 4434 4 43 JC, @ bit dataK

Lump)nconditional Mump L8P 4433 C CCCCCC bit Mump

$ooperation

$o operation / 9nd $%P 4443 C CCCCCCCCC

9nd of Program

9nd of program / 9nd 9+P 4444 C CCCCCCCCC


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9 4i#al Data*at! -or *ro essor

'fter deciding the opcodes of instructions we proceeded to designing datapaths for differentinstructions. e used the basic layout of 5 stages as shown below.

Basi 5 sta%es o- *ro essor

e followed certain steps to get the final datapath&

4. +esign datapaths for different types of instructions "for arithmetic, logical, memory etc.#. There are four different type of instructions which will have different datapaths 0 AL& "logical

arithmetic#, 6E6 "load store#, 6O> 6>I. Combi#e t!e data*at!s of different instruction into a single datapath with help of hardware

such as 8ux, +emux etc.


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I#stru tio# 4et ! Sta%e (I4)

4i#al Data*at! -or I4 sta%e

In this stage, the instruction is fetched from the instruction memory depending on the address in P!"Program counter#

4. The P! is initiali7ed to value P! A 4444N4444. 9n signal is high for the initial value of P! "9n A 4 when P! A 'll 4-s#. The add4 adder adds value 4 to P! "P! A P! B 4#


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I#stru tio# De ode = Re%ister 4et ! Sta%e (ID=R4)

4i#al Data*at! -or ID=R4 sta%e

*rom Instruction *etch stage, we get 4: bit instruction data. This data has information about theinstruction "see instruction format#. Then, values are fetched from registers depending upon theinstruction. !ontrol signals are also generated in same stage.

4. The control unit generates all the control signals responsible for the execution of instructions. The 2eg file contains 2egisters.. The =45&4 > bits areo* ode which go to the control unit.


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re o#-i% bits =43&?> also go to control unit5. The control unit generates various control signals such as AL& trl which decides '()

operation, active low register write enable" Re%7eE# # memory write enable" 6em7rE# #signals, sel signal"type of instructions# etc. T!ese o#trol si%#als are arried to t!e #e.t sta%e

:. =@&3> bits can immediate data for 8 I instructions or source/destination addresses for other

instructions. 1ence a +emux is used here with opcode as its select line.D. =5& > bits are always used as source 4 address@. = &3> bits can be source address / shift value / mem address depending on instructions. 1ence, a

demux is used?. The =@&:> bits are destination address bits are carried forward to next stage.43. The output from 2egfile is also carried forward to next stage.

E.e ute sta%e (E E)

4i#al data*at! -or E E sta%e

The 9xecute stage is the stage where the instruction is executed. The main component in this stage is the'(). %ther hardware is required to avoid the ha7ards encountered during instruction execution.

4. The data coming from 2egfile, rT a# o#ly be used as AL& i#*ut . It is given to '() after passing through O;election block- where ha7ards are resolved "+etails given below#.


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Cm* ; si%#al is high when the sour e address i# ID sta%e is same as desti#atio# address i# 6E6sta%e Thus, when next instruction enters 9C9 stage it must a e*t data -or+arded -rom 7B sta%erather than old data from previous stage. *urthermore, it indicates that we are concerned with onlyhigher byte of data =45&@>

Cm* ' si%#al is high when the sour e address i# ID sta%e is same as desti#atio# address i# E Esta%e Thus, when next instruction enters 9C9 stage it must a e*t data -or+arded -rom 6E6 sta%erather than old data from previous stage. *urthermore, it indicates that we are concerned with only lower

byte of data =D&3>

!mp 4 signal is similar to !mp but it only forwards lower byte of data. 6oth !mp 4 !mp < areactive when we need to forward entire 4: bits of data

!mp !mp < work in similar manner to !mp 4 !mp .

6emory Sta%e (6E6)

4i#al Data*at! -or 6E6 sta%e


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In memory stage, memory will be read / written if the instruction is a memory instruction.

4. If the out?e passed from previous stage is of ;T2 instruction then, outNe signal will go to writeNdata

. %therwise, the outNe signal is passed as it is. The mux is present at the end to determine whether

instruction in 898 stage is a (+2 instruction. If yes, then read output of memory will be written back to 2eg file. 'gain, O;el- line will determine which signals should be passed.

7riteBa " sta%e (7B)

'fter 898 stage, the final output, outNmem will be written into register file" +D #. Re%Dadd signal willdetermine the address of destination register " aD #. Re%7rE# signal will determine which bytes are to

be written " +e , +eL #.

Note & The destination address, all control signals, mvidata signal etc. will pass through every stage. They are not shown inabove diagrams to avoid confusion.

COMPONENTS:

i. 2:1 MUX:


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//////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 23:45:04 04/05/2014// Modu e !a"e: t#o$one$"u%

//////////////////////////////////////////////////////////////////////////////////"odu et#o$one$"u%&a,',s,()*in+uta,',s*

out+ut (*

assign ( &-s a) &s ') *

end"odu e

2:1 MUX RTL SCHEMATIC

ii. 4:1 MUX:

//////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 23:4 :32 04/05/2014// Modu e !a"e: our$one$"u%//////////////////////////////////////////////////////////////////////////////////


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"odu e our$one$"u%&a,', ,d,s,()*in+uta,', ,d*

in+ut 1:0 s*out+utreg (*

a #a(s &6)'egin ( &&-s 1 ) &-s 0 ) a) &&-s 1 ) s 0 ') &s 1 &-s 0 ) ) &s 1 s 0 d) *end

end"odu e

1:4 MUX RTL SCHEMATIC

iii. 2:1 DEMUX://////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 15:32:17 04/08/2014// Modu e !a"e: t#o$one$de"u%//////////////////////////////////////////////////////////////////////////////////"odu et#o$one$de"u%&in,s,(0,(1)*in+ut in,s*out+utreg (0,(1*


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a #a(s &6)'egin (0 19'%* (1 19'%*

ase&s)19'0 : (0 in*19'1 : (1 in*end ase

endend"odu e

1:2 DEMUX RTL SCHEMATIC

iv. 4:1 DEMUX:

//////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 13:10:08 04/08/2014

// Modu e !a"e: our$one$de"u%//////////////////////////////////////////////////////////////////////////////////

"odu e our$one$de"u%&in,s,(0,(1,(2,(3)* in+ut in*in+ut 1:0 s*out+ut reg (0,(1,(2,(3*


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a #a(s &6)'egin (0 19'%*

(1 19'%* (2 19'%*

(3 19'%* ase&s) 29'00 : (0 in* 29'01 : (1 in* 29'10 : (2 in* 29'11 : (3 in* end ase

endend"odu e

1:4 DEMUX RTL SCHEMATIC


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STAGE 1:

i. INPUT AND OUTPUT LINES:

ii. INTERNAL BLOCKS:

Stage 1 e!i"#g C#$e:

//////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 14:57:17 04/0 /2014


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// Modu e !a"e: stage1$+//////////////////////////////////////////////////////////////////////////////////

"odu e stage1$+& o ;,j"+$dis+,o+,inst$ ,


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STAGE 1 RTL SCHEMATIC

a% INCREMENTER:


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//////////////////////////////////////////////////////////////////////////////////

// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 00:4 :03 04/08/2014// Design !a"e:

// Modu e !a"e: adder$@A$//////////////////////////////////////////////////////////////////////////////////

"odu e adder$@A$ &a,',()*in+ut :0 a,'*out+ut :0 (*

assign ( aF'*

end"odu e

INCREMENTER

&% INSTRUCTION MEMOR':

//////////////////////////////////////////////////////////////////////////////////


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// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 00:5 :03 04/0 /2014// Modu e !a"e: @!S R C $MEM//////////////////////////////////////////////////////////////////////////////////

"odu e @!S R C $MEM&a,r)*in+ut :0 a* //Me"or( Gddressout+ut 15:0 r* //Me"or( data out+ut

reg 15:0 ro" 17:0 * //de aration o 258 18 "e"or( &2I 6 18)

initia'egin Jread"e"h&KhaLard. ist.t%tK,ro")* //Read and o+( he% ode ro"te%t e to "e"or(end

assign r ro" a * //Read ro" "e"or(

end"odu e

INSTRUCTION MEMOR'

STAGE 2:

i. INPUTS AND OUTPUT LINES:


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ii. I(te!(a" B"#)*+:

Stage 2 e!i"#g C#$e://////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 12:33:30 04/08/2014// Modu e !a"e: S GNE$2//////////////////////////////////////////////////////////////////////////////////

"odu e S GNE$2& o ;, inst,#D, aD, #$en, r , rS,

reg#ren,"e"#ren,se ,a u$ tr , tr ,ed+,shi t,aMe",aDest,

j"+$dis+,M>iData,aS,a)*

in+ut o ;*in+ut 15:0 inst* //instru tion et hed ro" stage 1 >ia 'uOer#ire :0 inst$ o+(,">i*out+ut :0 M>iData*


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#ire 3:0 o *#ire 1:0 r'*#ire ontro *

out+ut 1:0 reg#ren,se *out+ut"e"#ren*

out+ut 3:0 a u$ tr *out+ut tr *out+uted+*

out+utreg 2:0 aS* //sour e 1out+utreg 2:0 a * //sour e 2in+ut 2:0 aD* //dest. register addressin+ut 15:0 #D* //data to 'e #rittenin+ut 1:0 #$en* //a ti>e o# #rite ena' eout+ut 15:0 rS* //s r1 o/+out+ut 15:0 r * //s r2 o/+

out+ut 2:0 shi t, aMe"*out+utreg 2:0 aDest*out+ut 2:0 j"+$dis+*

#ire 2:0 sour e2*

assigno inst 15:12 * //o+ odeassignr' inst 10:7 * //re on g 'itsassign ontro inst 11 * // ontro 'itassignj"+$dis+ inst 2:0 * // ju"+ dis+ a e"ent to stage 1

#ire ">i$# a u$ tr 3 a u$ tr 2 &-a u$ tr 1 ) a u$ tr 0 tr * /6se e tine to ">i "u%6/

t#o$one$de"u% td :0 &inst :0 ,">i$#,inst$ o+(,">i)* //to se e tMP@data or //instru tion o+(

assignM>iData ">i :0 * //to se e t 'it MP@data

//???a #a(s ' o ; to se e t address o sour e 1???//a #a(s &6)'eginaS inst$ o+( 5:3 *

ase&o )49'1011 :'egini & tr 19'0)aS 39'%%%* // oadend


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49'1100 :aS 39'%%%* // j"+49'1110 :aS 39'%%%* // no+49'1111 :aS 39'%%%* // ed+end ase

end

#ire de"u%1 a u$ tr 3 &-a u$ tr 2 ) a u$ tr 0 * ////to se e t 'et#een"e"address/shi t other instru tions

#ire de"u%2 a u$ tr 1 * // to se e t 'et#een "e" address or shi t#ire 2:0 #*

t#o$one$de"u% t1 2:0 &inst$ o+( 2:0 ,de"u%1, sour e2, #)*t#o$one$de"u% t2 2:0 ,de"u%2, shi t, aMe")*

//???a #a(s ' o ; to se e t address o sour e 2???//

a #a(s &6)'egina sour e2 *

ase&o )49'0010 :a 39'%%%* // in r49'0011 :a 39'%%%* // de r49'0111 :a 39'%%%* // re+ and not

49'1101 :a 39'%%%* // "o>

49'1100 :a 39'%%%* // j"+49'1110 :a 39'%%%* // no+49'1111 :a 39'%%%* // ed+end ase

end

reg$ e a $reg &aS,a , o ;,aD,#D,rS,r ,#$en)* // a to register e

tr $unit a $ ontro &o , ontro ,r',reg#ren,"e"#ren,a u$ tr , tr ,ed+,se )*

// a to ontro unit

//???a #a(s ' o ; or destination address???//

a #a(s &6)

'eginaDest inst$ o+( :8 *


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ase&o )

49'1101 :'egini & tr )

aDest 39'000* // ">iend

49'1011 :'egini & tr ) // storeaDest 39'%%%*end

49'1100 :aDest 39'%%%* // j"+49'1110 :aDest 39'%%%* // no+

49'1111 :aDest 39'%%%* // ed+end aseendend"odu e


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STAGE 2 RTL SCHEMATIC

REN@S ER

CQ! RQ


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a% REGISTER ,ILE:

/////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 22:11:31 04/05/2014

// Modu e !a"e: reg$ e//////////////////////////////////////////////////////////////////////////////////

"odu e reg$ e&aS,a , ;,aD,#D,rS,r ,#$en)*in+ut ;* //in+ut 1:0 r'* //a ti>e o# re on gura' e 'itsin+ut 2:0 aS* //sour e 1in+ut 2:0 a * //sour e 2in+ut 2:0 aD* //dest. registerin+ut 15:0 #D* //data to 'e #rittenin+ut 1:0 #$en* //a ti>e o# #rite ena' e

out+utreg 15:0 rS* //s r1 o/+out+utreg 15:0 r * //s r2 o/+

reg 15:0 g+r :0 *

a #a(s &negedge ;)'eginrS= g+r aS * //read the datar = g+r a * //at negati>e edgeend

a #a(s &+osedge ;) //#rite at +ositi>e'egin //edge

i $en 29'00)g+r aD = #D* //18 'it #ritee se i $en 29'10)g+r aD :0 = #D :0 * // o#er '(te #ritee se i $en 29'01)g+r aD 15: = #D 15: * //higher '(te #riteend

end"odu e


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') Contro nit:


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//////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 01:4 :50 04/08/2014// Modu e !a"e: tr $unit//////////////////////////////////////////////////////////////////////////////////

"odu e tr $unit&o , ontro ,r',reg#ren,"e"#ren,a u$ tr , tr ,ed+,se )*in+ut 3:0 o *in+ut 1:0 r'*

in+ut ontro *out+utreg 1:0 reg#ren,se *out+utreg"e"#ren*out+utreg 3:0 a u$ tr *out+ut tr *

out+utreged+*

initia'eginreg#ren 29'11*

ed+ 19'1*end

// assign o+ ode to a u$ tr signaa #a(s &6)'egina u$ tr = o *end


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assign tr ontro *

// assigning >a ue to ed+signa &a ti>e o#)

a #a(s &6)'egined+ -&o 3 o 2 o 1 o 0 )*end

// #rite ena' e signa s&a ti>e o#)a #a(s &6)'egin"e"#ren 19'1*

reg#ren r'*

ase&o )

49'1000 : // "u ti+ ('egin"e"#ren 19'1*

reg#ren 29'00*end

49'1001 : // shi t'egin

"e"#ren 19'1*reg#ren 29'00*end

49'1011 : // "e"or('egini & tr ) // store

'egin"e"#ren 19'0*

reg#ren 29'11*end

e se // oad'egin"e"#ren 19'1*

reg#ren 29'00*end

end

49'1110 : // no+


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'egin"e"#ren 19'1*

reg#ren 29'11*end

49'1100 : // ju"+'egin"e"#ren 19'1*

reg#ren 29'11*end

49'1111 : // ed+'egin"e"#ren 19'1*

reg#ren 29'11*end

end aseend

// or se signaa #a(s &6)'eginse 29'00* // a u

ase&o 3:0 )49'1011 :se 29'01* // "e" oad,store

49'1101 :'egini & tr )

se 29'10* /// ">ie sese 29'11* /// "o>

end

end aseend

end"odu e


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CONTROL UNIT RTL SCHEMATIC

)% HA-ARD UNIT:

//////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 00:12:22 04/0 /2014// Modu e !a"e: haLard$unit$ na//////////////////////////////////////////////////////////////////////////////////

SE EC @!E QN@C !@

REN@S ER R@ E E!GT E

MEMQRU R@ E E!GT E QN@C


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"odu ehaLard$unit$ na &aD$e,aD$",aS,a , "+$"e"$S, "+$"e"$ , "+$e%e$S,"+$e%e$ )*in+ut 2:0 aD$e,aD$",aS,a *

out+utreg "+$"e"$S, "+$"e"$ , "+$e%e$S, "+$e%e$ *

initia'egin

"+$"e"$S 19'0*"+$"e"$ 19'0*"+$e%e$S 19'0*"+$e%e$ 19'0*

end

a #a(s &6)'egin

"+$"e"$S 19'0*"+$"e"$ 19'0*"+$e%e$S 19'0*"+$e%e$ 19'0*

i &aD$e aS) // o"+aring sr 1 addr #ith destaddr o e%e stage"+$e%e$S 19'1*

i &aD$e a ) // o"+aring sr 2 addr #ith destaddr o e%e stage

"+$e%e$ 19'1*i &aD$" aS) // o"+aring sr 1 addr #ith destaddr o "e" stage

"+$"e"$S 19'1*i &aD$" a ) // o"+aring sr 2 addr #ith destaddr o "e" stage

"+$"e"$ 19'1*end

end"odu e


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HA-ARD UNIT RTL SCHEMATIC

STAGE : EXECUTION UNIT


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INPUT AND OUTPUT LINES:

I/O LINES O, EXECUTION UNIT

i. INTERNAL BLOCKS O, EXECUTION UNIT:


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ERILOG CODE ,OR EXECUTION UNIT:

//////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.

// Create Date: 23:2 :48 04/0 /2014// Modu e !a"e: stage3//////////////////////////////////////////////////////////////////////////////////

"odu e stage3&r $e, rS$e, se $e,a u$ tr $e, tr $e,shi t$e,

M>iData$e,"+$e%e$S$e, "+$"e"$S$e, "+$e%e$ $e, "+$"e"$ $e,

reg#ren$e,reg#ren$",reg#ren$#', r#d$"e", r#d$#',out$e

)*

in+ut 15:0 r $e, rS$e*in+ut "+$e%e$S$e, "+$"e"$S$e, "+$e%e$ $e, "+$"e"$ $e*

#ire :0 #1$s,#2$s,#3$s,#4$s*#ire "+1, "+2, "+3, "+4*#ire :0 #1$t,#2$t,#3$t,#4$t*#ire "+5, "+8, "+ , "+ *

in+ut 1:0 reg#ren$e,reg#ren$",reg#ren$#',se $e*#ire 15:0 Mo>Data$e*

#ire 15:0 Me"Data$e*in+ut :0 M>iData$e*

out+ut 15:0 out$e*#ire 15:0 G,T,U*

in+ut 3:0 a u$ tr $e*in+ut tr $e*in+ut 2:0 shi t$e*in+ut 15:0 r#d$"e", r#d$#'*

assign "+1 "+$e%e$S$e &-reg#ren$" 0 )* //se ines or "u% tose e t 'et#een or#arded data

assign "+2 "+$"e"$S$e &-reg#ren$#' 0 )* // or +re>ious dataonsidering higher o#er '(tes

assign "+3 "+$e%e$S$e &-reg#ren$" 1 )* // using destnaddr,sr addr reg#ren signa s or sr 1assign "+4 "+$"e"$S$e &-reg#ren$#' 1 )*


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t#o$one$"u% e$"$1 :0 &rS$e :0 , r#d$"e" :0 , "+1,#1$s)*t#o$one$"u% e$"$2 :0 $s, r#d$#' :0 , "+2,#2$s)* // to se e tsour e 1 datat#o$one$"u% e$"$3 :0 &rS$e 15: , r#d$"e" 15: , "+3,#3$s)*

t#o$one$"u% e$"$4 :0 $s, r#d$#' 15: , "+4,#4$s)*

our$one$de"u% e$d"$1 15:0 &B#4$s,#2$s ,se $e,G,Me"Data$e, ,Mo>Data$e )* //to se+erate sr 1 data de+ending on se e t ine

assign "+5 "+$e%e$ $e &-reg#ren$" 0 )* //se ines or "u% to se e t'et#een or#arded dataassign "+8 "+$"e"$ $e &-reg#ren$#' 0 )* // or +re>ious data

onsidering higher o#er '(tesassign "+ "+$e%e$ $e &-reg#ren$" 1 )* // using

destnaddr, sr addr reg#ren signa s or sr 1assign "+ "+$"e"$ $e &-reg#ren$#' 1 )*

t#o$one$"u% e$"$5 :0 &r $e :0 , r#d$"e" :0 , "+5,#1$t)*t#o$one$"u% e$"$8 :0 $t, r#d$#' :0 , "+8,#2$t)* // to se e t sour e2 datat#o$one$"u% e$"$ :0 &r $e 15: , r#d$"e" 15: , "+ ,#3$t)*t#o$one$"u% e$"$ :0 $t, r#d$#' 15: , "+ ,#4$t)*

assign T B#4$t,#2$t *

G $+ro essor a $stage3&G,T,a u$ tr $e, tr $e,reg#ren$e,U,shi t$e)* //a to a u

our$one$"u% e$ "$1 15:0 &U,Me"Data$e,BM>iData$e,M>iData$e ,Mo>Data$e,se $e,out$e)*

end"odu e


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EXECUTION STAGE RTL SCHEMATIC

i. ALU UNIT:

G !@


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//////////////////////////////////////////////////////////////////////////////////// Engineer:Harshad, Ritesh, Sanjog, Rohit.// Create Date: 15:55:31 04/05/2014// Modu e !a"e: G $+ro essor//////////////////////////////////////////////////////////////////////////////////

"odu eG $+ro essor&a,',a u$ tr , tr ,r',(,shi t)*in+ut 15:0 a*in+ut 15:0 '*

out+ut 15:0 (*in+ut 2:0 shi t*in+ut 3:0 a u$ tr *

in+ut tr *in+ut 1:0 r'*

#ire 15:0 #0,#1*

arith a1 &a,',a u$ tr , tr ,r',shi t,#0)* //arith"eti unit

ogi $unit 1 &a,',r',a u$ tr 1:0 , tr ,#1)* // ogi a unit

t#o$one$"u% "1 15:0 ,#1,a u$ tr 2 ,()* //to se e t 'et#een t#o units

end"odu e


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ALU RTL SCHEMATIC

a% ARITHMATIC UNIT:


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//////////////////////////////////////////////////////////////////////////////////// Engineer:Harshad, Ritesh, Sanjog, Rohit.

// Create Date: 13:11:17 04/05/2014// Modu e !a"e: arith//////////////////////////////////////////////////////////////////////////////////

"odu earith&a,',a u$ tr , tr ,r',shi t,(arith)*in+ut 15:0 a*in+ut 15:0 '*out+ut 15:0 (arith*in+ut 2:0 shi t*

in+ut 3:0 a u$ tr *in+ut tr *

in+ut 1:0 r'*

#ire 15:0 #0,#1,# ,#10,#11,#12*#ire :0 #2,#3,#4,#5,#8,# ,#7*#ire 15:0 i0*

our$one$"u% 1 15:0 &',&-'F189'1),189'1,B18B19'1 ,a u$ tr 1:0 ,#0)*//to se e t addition,su'stra tion,in ,de


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a18 adder1&a,#0,19'0,#1)* //18 'it adder

t#o$one$"u% t1 :0 &a 15: ,a :0 ,r' 1 ,#2)* // to se e t higher'(te or o#er '(te or 'it o+eration

our$one$"u% 2 :0 &' 15: ,&-' 15: F 9'1), 9'1,B B19'1 ,a u$ tr 1:0 ,#3)* //to se e t addition,su'stra tion,in ,de

// or higher 'its

our$one$"u% 3 :0 &' :0 ,&-' :0 F 9'1), 9'1,B B19'1 ,a u$ tr 1:0 ,#4)* //to se e t addition,su'stra tion,in ,de

// or o#er 'its

t#o$one$"u% t2 :0 ,#4,r' 1 ,#5)*

a adder2,#5,19'0,#8)*

t#o$one$"u% i0$"u% 15:0 &B#8, 9'0000$0000 ,B 9'0000$0000,#8 ,r' 1 ,i0)* // to on>ert 'it o+ into 18 'it data

t#o$one$"u% t3 15:0 ,i0,&r' 0 Ir' 1 ),# )*

t#o$one$"u% t4 :0 &a :0 ,a 15: , tr ,# )*//to se e t o#er or higher '(te or "u

t#o$one$"u% t5 :0 &' :0 ,' 15: , tr ,#7)*//to se e t o#er or higher '(te or "u

eight$unsigned "u ti+ ier ,#7,#10)*

shi ter s1 &a,shi t, tr ,#11)*t#o$one$"u% t8 15:0 ,#11,a u$ tr 0 ,#12)* // "u or shi t

t#o$one$"u% t 15:0 ,#12,&a u$ tr 3 a u$ tr 2 ),(arith)* // nao+

end"odu e


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ARITHMATIC UNIT RTL SCHEMATIC

COMPONENTS O, ARITHMATIC UNIT:

1. 4BIT CLA:

//////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 03:13:55 04/0 /2014// Modu e !a"e: a$4


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//////////////////////////////////////////////////////////////////////////////////

"odu e a$4&a,', in,s, out)*in+ut 3:0 a,'*

in+ut in*

out+ut 3:0 s*out+ut out*

#ire 3:0 g,+, *

assign g 0 a 0 ' 0 *assign + 0 a 0 I' 0 *assign g 1 a 1 ' 1 *assign + 1 a 1 I' 1 *assign g 2 a 2 ' 2 *

assign + 2 a 2 I' 2 *assign g 3 a 3 ' 3 *assign + 3 a 3 I' 3 *

assign 0 g 0 &+ 0 in)*assign 1 g 1 &+ 1 g 0 ) &+ 1 + 0 in)*assign 2 g 2 &+ 2 g 1 ) &+ 2 + 1 g 0 ) &+ 2 + 1 + 0 in) *assign out g 3 &+ 3 g 2 ) &+ 3 + 2 g 1 ) &+ 3 + 2 + 1 g 0 ) &+ 3 + 2 + 1 + 0 in)*

assign s 0 + 0 I in*

assign s 1 + 1 I 0 *assign s 2 + 2 I 1 *assign s 3 + 3 I 2 *

end"odu e


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4BIT CLA RTL

2. 10BIT CLA:

//////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 03:13:55 04/0 /2014// Modu e !a"e: a$4//////////////////////////////////////////////////////////////////////////////////

"odu e a$4&a,', in,s, out)*


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in+ut 3:0 a,'*in+ut in*out+ut 3:0 s*out+ut out*

#ire 3:0 g,+, *

assign g 0 a 0 ' 0 *assign + 0 a 0 I' 0 *assign g 1 a 1 ' 1 *assign + 1 a 1 I' 1 *assign g 2 a 2 ' 2 *assign + 2 a 2 I' 2 *assign g 3 a 3 ' 3 *assign + 3 a 3 I' 3 *

assign 0 g 0 &+ 0 in)*assign 1 g 1 &+ 1 g 0 ) &+ 1 + 0 in)*assign 2 g 2 &+ 2 g 1 ) &+ 2 + 1 g 0 ) &+ 2 + 1 + 0 in) *assign out g 3 &+ 3 g 2 ) &+ 3 + 2 g 1 ) &+ 3 + 2 + 1 g 0 ) &+ 3 + 2 + 1 + 0 in)*

assign s 0 + 0 I in*assign s 1 + 1 I 0 *assign s 2 + 2 I 1 *assign s 3 + 3 I 2 *

end"odu e


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10 BIT CLA RTL SCHEMATIC

. BIT CLA:

//////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 03:17:18 04/0 /2014// Modu e !a"e: a//////////////////////////////////////////////////////////////////////////////////

"odu e a &a,', in,s)*


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in+ut :0 a,'*in+ut in*out+ut :0 s*

#ire 1, 2*a$4 add1&a 3:0 ,' 3:0 , in,s 3:0 , 1)*a$4 add2&a :4 ,' :4 , 1,s :4 , 2)*

end"odu e

BIT CLA RTL SCHEMATIC

4. BIT UNSIGNED MULTIPLIER:


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a% HAL, ADDER:

//////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 10:35:08 03/0 /2014

// Modu e !a"e: ha//////////////////////////////////////////////////////////////////////////////

"odu e ha&a,',s, out)*in+ut a*in+ut '*out+ut s*out+ut out*assign s aI'*assign out a '*

end"odu e

HAL, ADDER RTL SCHEMATIC

&% ,ULL ADDER:

//////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 10:3 :48 03/0 /2014


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// Modu e !a"e: a//////////////////////////////////////////////////////////////////////////////////

"odu e a&a,', in,s, out)*in+ut a*

in+ut '*in+ut in*out+ut s*out+ut out*

assign s aI'I in*assign out &a ') &' in) &a in)*

end"odu e

,ULL ADDER RTL SCHEMATIC

. SHI,TER UNIT:


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//////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 15:07:27 04/05/2014// Modu e !a"e: shi ter//////////////////////////////////////////////////////////////////////////////////

"odu e shi ter&a,shi t, tr ,()*in+ut 15:0 a*in+ut 2:0 shi t*

in+ut tr *out+ut 15:0 (*

#ire 15:0 #1,#2*assign #1 a==shi t*assign #2 aVVshi t*

t#o$one$"u% "1 15:0 ,#2, tr ,()*

end"odu e


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SHI,TER UNIT RTL SCHEMATIC

&% L#gi) U(it:


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//////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.// Create Date: 18:57:43 04/08/2014// Modu e !a"e: ogi $unit//////////////////////////////////////////////////////////////////////////////////"odu e ogi $unit&a,',r',a u$ tr , tr ,()*in+ut 15:0 a,'*

in+ut 1:0 r',a u$ tr *in+ut tr *out+ut 15:0 (*

#ire 15:0 #$and, #$or, #$e%or, #$out,#1*

assign#$and a '*assign#$or a '*assign#$e%or a I '*

our$one$"u%"u%$ ogi 15:0 $and,#$or,#$e%or,a,a u$ tr ,#$out)*

t#o$one$"u%"u%$gate 15:0 $out,&-#$out), tr ,#1)*


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our$one$"u% "2 15:0 ,B#1 15: , 9'00000000 ,B 9'00000000,#1 :0 ,#1,r',()*

end"odu e

LOGIC UNIT RTL SCHEMATIC


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STAGE 4: MEMOR' 3RITE:

i. INPUT OUTPUT LINES:

ii. INTERNAL BLOCKS O, MEMOR' 3RITE:

INSTRUCTION MEMOR':

//////////////////////////////////////////////////////////////////////////////////

// Engineer: Harshad, Ritesh, Sanjog, Rohit.

// Create Date: 22:00:24 04/05/2014

// Modu e !a"e: data$"e"or(

//////////////////////////////////////////////////////////////////////////////////

"odu edata$"e"or(&a,#, o ;,#$en,r)*

+ara"eter ! 3,M 18* //! V "e"or( address siLe, M V Me"or( data siLe

in+ut !?1:0 a* //"e"or( address

in+ut M?1:0 #* //"e"or( #rite data in+ut


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in+ut o ;*

in+ut#$en* //#rite Ena' e

out+utreg M?1:0 r* //Me"or( read out+ut

reg M?1:0 "e" 266!?1:0 * //de aration o %18 "e"or( 2I&!) ? 1 : 0

a #a(s &+osedge o ;) //#rite on +ositi>e ; edge

'egin

i $en 19'0)

"e" a = #* // #rite data in "e"or(

end

a #a(s &negedge o ; //Me" read on negati>e ; edge

'egin

r = "e" a * // read data ro" "e"or(

end

end"odu e


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DATA MEMOR' AND EDP INST. LOGIC RTL SCHEMATIC

ERILOG CODE ,OR MEMOR' 3RITE STAGE:

//////////////////////////////////////////////////////////////////////////////////// Engineer: Harshad, Ritesh, Sanjog, Rohit.

// Create Date: 23:53:14 04/07/2014// Modu e !a"e: stage4//////////////////////////////////////////////////////////////////////////////////

"odu e stage4& o ;, in$", "e"#ren$",se $",aMe"$",out$"e" )*

in+ut o ;*in+ut 15:0 in$"*in+ut 1:0 se $"*in+ut"e"#ren$"*in+ut 2:0 aMe"$"*

out+ut 15:0 out$"e"*

#ire 15:0 readMe"$"*


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Carryi#% out t!e *la#

Test Be# ! 7a/e-orms

ARIT 6ATIC &NIT

O* ode I#stru tio# O&T?E

+'34 8 I1 23,341 231A341

+!43 8 I( 23,431 23(A431

+3


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I$!1 25,25

+9!( 2


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8)(( 2:,2


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9+P


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LOGICAL &NIT

O* ode I#stru tio# O&T?E

+'34 8 I1 23,341 231A341

+!43 8 I( 23,431 23(A431

+3


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'$+ 2


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$%T1 2D,25

This instruction will I$ 92T the contents of 25 and store the result at 2


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A@ARD &NIT

OPCODE INSTR&CTION O&T?E E

+'34 8 I1 23, 341 231 A 34

+!43 8 I( 23, 431 23( A 43

+3


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:0 '++ CCC ;T%29 D0 8% ;T%29 @0 (%'+ 8%

The 1a7ard unit and all the logic circuit considering ha7ards are located in stage "+ecode# and stage"9xecute#. 1ence the output of sta%e : is important in order to verify whether the ha7ards are

considered or not. Therefore, we will consider only stage outputs to analy7e and verify the ha7ard

unit.

a8ard A#alysis

') 1a7ard for

8 I1 23 A 34

8 I( 23 A 43

8% 24 A 23

%)TNe A 3443 a+estNe A 334 shows that 24 is getting correct value considering data from 8emoryand rite 6ack stage and also considering 1igher and (ower 6yte.

9) 1a7ard for

8% 24 A 23 A 3443,

;T%29 8em334 A 24


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;imulation 2esults for ;T%29 8em334 A 24 in execute stage

%)TNe A 3443 a8emNe A 334 and memwrenNe A 3 shows that 8emory (ocation 334 is gettingcorrect value considering data from 8emory stage.

In intermediate steps, we have initiali7ed R : ;, R9 99 and 6em : ; which we aregoing to use in remaining part of the program.

:) !onsider (%'+ CCC '2IT1 as follows

(%'+ 2 A 8em333 A 33

:. The speed functionality of the processor will depend upon the units which we have designed04# !ontrol unit # 1a7ard )nit # '()


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Sy#t!esis Re*ort

Processor Report Final

Documents

Transcript of Processor Report Final