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ECE 4430 Project 2ECE 4430 Project 2

Operational Amplifier

Dennis Larsen

Yining Zhang

Julius Ivester

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Design SpecificationsDesign Specifications

Technology TSMC 0.18 m

Supply Voltage (V) 1.8

Maximum Power Consumption (W) 200

Differential Gain (dB) 100

CMRR (dB) 100

ICMR (V) 0 - 1.8

Output Swing (V) 0 - 1.8

Bandwidth - 3dB (kHz) 50

Loading (pF || kOhm) 10 II 100

Slew Rate (V/us) 20

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Initial DesignInitial Design

The wide swing Diff Amp with constant gm topology was

chosen to achieve the rail to rail swing.

Initially open circuit tests were used to determine the

number of required stages to achieve 100 dB.

Max power consumption is 200uW and Supply is 1.8 V

so there is room for more current.

Choose Push-Pull output buffer for full output swing.

Only two stages were needed one Diff Amp and one

Push-Pull output buffer.

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Design StepsDesign Steps

Added two source followers to match the high DC

output of ~.9 V from the Diff Amp and the low input of

~.3 V of the buffer.

Changed topologies after finding poor VDD sensitivity.

Changed from Voltage output Diff amp to Current

output Diff amp.

No longer need the source followers.

Fine tuned the output buffer to change the differential

transition region and improve differential gain.

Add Cc equal to 70fF for phase margin.

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Topology ChangesTopology Changes

Topology Reasoning

Classic Diff Pair with Common Source

amplifier and Push-Pull buffer

Gave up some ICMR to increase Gain,

CMRR, and improve Power Dissipation.

Classic Diff Pair with Source Follower

and Push-Pull buffer

Gave up ICMR to improve Power

Dissipation and increase Gain

Wide Swing Diff Amp with Source

Follower and Push-Pull buffer

Achieved ICMR, Gain, and CMRR but

VDD sensitivity was bad.

Current

Wide Swing Diff Amp with Push-Pull

buffer

Achieved close to all targets, but more

tuning is needed to achieve everything.

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Overview of CircuitOverview of Circuit

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Original Differential Amplifier TopologyOriginal Differential Amplifier Topology

Topology was based on Baker Figure 24.48

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Current Differential Amplifier TopologyCurrent Differential Amplifier Topology

Topology was based on Baker Figure 24.48

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Output StageOutput Stage

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Slew RateSlew Rate

There is no noticeable ringing in output waveform.

Rise Time = 126 ns Positive Slew Rate = 14 V/us

Fall time = 163 ns Negative Slew Rate = 11.6 V/us

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THDTHD

The Output swinging from rail to rail.

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Output SwingOutput Swing

The output swings exactly from 0 - VDD

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PSRRPSRR

A usual graph for an OpAmp that has a supply of VDD and 0 rather than

+/- VDD

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DC/Avc SweepDC/Avc Sweep

A common mode sweep of the amplifier without the

constant gm stage.

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CMRRCMRR

The CMRR goes out of spec when one of the

NMOS or PMOS pairs turns off and extra

current is added

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AC gain with Common mode inputAC gain with Common mode input

The amplifier maintains a gain of over 97 dB between

.25V and 1.37V

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Minimum VDD for differential outputMinimum VDD for differential output

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Final Specs and ResultsFinal Specs and Results

Specification Result

Diff. Amp topology Wide swing

with const. gm

Reference topology BGR

Min Supply (V) 0.805 V

Max Supply (V) N/A

Diff. Amp Gain (dB) 36.6

CMRR (dB) 84 138

Ref. power consumption (W) 25.6

OpAmp power consumption with

zero input (W)

467

OpAmp power consumption with

no load (W)

675

Total power consumption (W) 684

Positive Slew Rate (V/us) 14

Negative Slew Rate (V/us) 11.6

ICMR (Vmin ~ Vmax) 0.25 1.37

Output Swing (Vmin ~ Vmax) 0 - VDD

VDD PSRR (dB) 9.15

Nominal output voltage (V) 0.9

Input offset voltage (mV) 676 nV

Unloaded Bandwidth (kHz) 417 Hz

Loaded Bandwidth (kHz) 494 Hz

Gain bandwidth product (MHz) 46.1 MHz

Compensation capacitor (pF) 70 fF

Phase margin (degrees) 53

Rise time (ns) 126

Fall time (ns) 163

Settling time (ns) 0

THD for full Swing (%) 2.53

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Changes from required SpecificationsChanges from required Specifications

Parameter Specification

Required

Specification

achieved

Max Power

Consumption (uW)

200 684

Differential Gain (dB) 100 97

CMRR (dB) 100 84 138

ICMR (V) 0 1.8 0.25 - 1.37

Output Swing (V) 0 1.8 0 1.8

Bandwidth - 3dB (kHz) 50 494 Hz

Slew Rate (V/us) 20 14

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ConclusionsConclusions

We have much larger power consumption to improve

the slew rate.

Could fine tune the Differential Amplifier stage to

improve ICMR.

Phase margin is high enough to prevent oscillations in

the step response.

The cascoded structures lowered the ICMR.

All testing was done by altering the total schematic no

test structures were used.

The output stage consumed most of the power.