Instruction list S7-300 CPUs and ET 200 CPUs ______________________________________________________________________________________________________________________________________________________________________________________________ SIMATIC S7-300 Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual This manual is part of the documentation package with order number:6ES7398-8FA10-8BA0

06/2011 A5E02354744-05 Validity Range of the Instructions List 1 Address Identifiers and Parameter Ranges 2 Constants 3 Abbreviations 4 Registers 5 Status Word 6 Addressing 7 Examples of how to calculate the pointer 8 Instruction list 9 SSL partial list 10 Legal information Legal information Warning notice system This manual contains notices you have to observe in order to ensure your personal safety, as well as to prevent damage to property. The notices referring to your personal safety are highlighted in the manual by a safety alert symbol, notices referring only to property damage have no safety alert symbol. These notices shown below are graded according to the degree of danger. DANGER indicates that death or severe personal injury will result if proper precautions are not taken. WARNING indicates that death or severe personal injury may result if proper precautions are not taken. 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Qualified personnel are those who, based on their training and experience, are capable of identifying risks and avoiding potential hazards when working with these products/systems. Proper use of Siemens products Note the following: WARNING Siemens products may only be used for the applications described in the catalog and in the relevant technical documentation. If products and components from other manufacturers are used, these must be recommended or approved by Siemens. Proper transport, storage, installation, assembly, commissioning, operation and maintenance are required to ensure that the products operate safely and without any problems. The permissible ambient conditions must be complied with. The information in the relevant documentation must be observed. Trademarks All names identified by are registered trademarks of Siemens AG. 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Technical data subject to change Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-053 Table of contents 1Validity Range of the Instructions List ........................................................................................................ 5 2Address Identifiers and Parameter Ranges ............................................................................................... 7 3Constants ................................................................................................................................................ 11 4Abbreviations........................................................................................................................................... 13 5Registers ................................................................................................................................................. 15 6Status Word............................................................................................................................................. 17 7Addressing............................................................................................................................................... 19 7.1Address types ..............................................................................................................................19 7.2Examples of addressing...............................................................................................................21 8Examples of how to calculate the pointer................................................................................................. 23 9Instruction list........................................................................................................................................... 25 9.1Logic instructions .........................................................................................................................26 9.1.1Bit logic instructions .....................................................................................................................26 9.1.2Bit logic instructions with parenthetical expressions....................................................................27 9.1.3Logic Instructions with Timers and Counters...............................................................................28 9.1.4Logic Instructions Using AND, OR and EXCLUSIVE OR............................................................29 9.2EdgeTriggered Instructions..........................................................................................................31 9.3Setting/Resetting Bit Addresses ..................................................................................................31 9.4Instructions Directly Affecting the RLO........................................................................................32 9.5Timer Instructions ........................................................................................................................33 9.6Counter Instructions.....................................................................................................................34 9.7Load Instructions..........................................................................................................................35 9.8Load Instructions for Timers and Counters..................................................................................35 9.9Transfer Instructions ....................................................................................................................36 9.10Load and Transfer Instructions for Address Registers ................................................................36 9.11Load and Transfer Instructions for the Status Word....................................................................38 9.12Load Instructions for DB Number and DB Length .......................................................................38 9.13Word Logic Instructions with the Contents of Accumulator 1 ......................................................39 9.14Fixedpoint arithmetic (16/32-bit) / Floatingpoint arithmetic (32-bit) .............................................40 9.15Square root, square (32 bit)/logarithm function (32 bit) ...............................................................42 9.16Trigonometrical functions (32 bits)...............................................................................................43 9.17Adding Constants.........................................................................................................................43 Table of contents

Instruction list S7-300 CPUs and ET 200 CPUs 4Parameter Manual, 06/2011, A5E02354744-05 9.18Adding Using Address Registers ................................................................................................ 44 9.19Comparison instructions with integers (16/32 bit) or with 32-bit real numbers........................... 45 9.20Shift Instructions.......................................................................................................................... 46 9.21Rotate Instructions ...................................................................................................................... 47 9.22ACCU-transfer instructions, incrementing and decrementing..................................................... 48 9.23Program Display and Null Operation Instructions....................................................................... 48 9.24Data Type Conversion Instructions............................................................................................. 49 9.25Forming the Ones and Twos Complements ............................................................................... 50 9.26Block Call Instructions................................................................................................................. 50 9.27Block End Instructions................................................................................................................. 52 9.28Exchange Data Blocks................................................................................................................ 52 9.29Jump instructions ........................................................................................................................ 53 9.29.1Examples of jump instructions .................................................................................................... 56 9.30Instructions for the Master Control Relay (MCR) ........................................................................ 58 9.31Execution Times.......................................................................................................................... 59 9.31.1Execution Time ........................................................................................................................... 59 9.31.2Loading the Addresses and Operands ....................................................................................... 60 9.31.3Execution times for address access - indirect addressing.......................................................... 60 9.31.4Execution times for address access to I/O - direct and indirect addressing (PI/PO) .................. 61 9.32Master Control Relay - active (MCR) .......................................................................................... 62 9.33Calculating the execution time using CPU 315-2 DP as an example......................................... 63 9.34Example of I/O Access................................................................................................................ 65 9.35Organization Blocks (OB)............................................................................................................ 66 9.36Function Blocks (FBs) ................................................................................................................. 70 9.37Functions (FC) ............................................................................................................................ 70 9.38Data blocks (DB) ......................................................................................................................... 70 9.39System Functions (SFC) ............................................................................................................. 71 9.40System Function Blocks (SFB) ................................................................................................... 79 9.41Standard blocks for S7 communication ...................................................................................... 83 9.42Function Blocks for Open Communication via Industrial Ethernet.............................................. 84 9.43IEC Functions.............................................................................................................................. 85 10SSL partial list.......................................................................................................................................... 87 Index........................................................................................................................................................ 93 Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-055 Validity Range of the Instructions List1Table 1- 1This instruction list applies to the CPUs listed below: Order numberAs of firmware version In the following referred to as 1) S7-300 CPUs CPU 3126ES7312-1AE14-0AB0V3.3 CPU 312C6ES7312-5BF04-0AB0V3.3 312 CPU 313C6ES7313-5BG04-0AB0V3.3 CPU 313C-2 PtP6ES7313-6BG04-0AB0V3.3 CPU 313C-2 DP6ES7313-6CG04-0AB0V3.3 313 CPU 3146ES7314-1AG14-0AB0V3.3 CPU 314C-2 PtP6ES7314-6BH04-0AB0V3.3 CPU 314C-2 DP6ES7314-6CH04-0AB0V3.3 CPU 314C-2 PN/DP6ES7314-6EH04-0AB0V3.3 314 CPU 315-2 DP6ES7315-2AH14-0AB0V3.3 CPU 315-2 PN/DP6ES7315-2EH14-0AB0V3.2 315 CPU 317-2 DP6ES7317-2AK14-0AB0V3.3 CPU 317-2 PN/DP6ES7317-2EK14-0AB0V3.2 317 CPU 319-3 PN/DP6ES7318-3EL01-0AB0V3.2319 ET 200 CPUs IM151-7 CPU6ES7151-7AA21-0AB0V3.3 IM151-8 PN/DP CPU6ES7151-8AB01-0AB0V3.2 151 IM154-8 PN/DP CPU6ES7154-8AB01-0AB0V3.2154 1) except in those tables requiring a detailed differentiation Validity Range of the Instructions List

Instruction list S7-300 CPUs and ET 200 CPUs 6Parameter Manual, 06/2011, A5E02354744-05 Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-057 Address Identifiers and Parameter Ranges2 The following address identifiers and address areas are used. Because the values of CPU 313C-2 DP, 314C-2 DP and 314C-2 PN/DP deviate from the generally applicable table, there follows a separate table with the values of the listed CPUs. Parameter RangesAddress 312313314315317319151154 Description Q0.0 to 127.7 (can be set up 1023.7) 0.0 to 127.7 (can be set up to 2047.7) 0.0 to 255.7 (can be set up to 8191.7) 0.0 to 127.7 (can be set up to 2047.7) Output (in PIQ) QB0 to 127 (can be set up 1023) 0 to 127 (can be set up to 2047) 0 to 255 (can be set up to 8191) 0 to 127 (can be set up 2047) Output byte (in PIQ) QW0 to 126 (can be set up 1022) 0 to 126 (can be set up to 2046) 0 to 254 (can be set up to 8190) 0 to 126 (can be set up 2046) Output word (in PIQ) QD0 to 124 (can be set up 1020) 0 to 124 (can be set up to 2044) 0 to 252 (can be set up to 8188) 0 to 124 (can be set up 2044) Output double word (in PIQ) DB1 to 16000Data block DBX0.0 to 32731.7 1) 0.0 to 65533.7Data bit in data block DBB0.0 to 32731 1) 0 to 65533Data byte in DB DBW0.0 to 32730 1) 0 to 65532Data word in DB DBD0.0 to 32728 1) 0 to 65530Data double word in DB DI1 to 16000Instance data block DIX0.0 to 32731.7 1) 0.0 to 65533.7Data bit in instance DB DIB0.0 to 32731 1) 0 to 65533Data byte in instance DB DIW0.0 to 32730 1) 0 to 65532Data word in instance DB DID0.0 to 32728 1) 0 to 65530Data double word in instance DB 1) The same parameter ranges apply to the CPU 312C as for the other CPUs. Address Identifiers and Parameter Ranges

Instruction list S7-300 CPUs and ET 200 CPUs 8Parameter Manual, 06/2011, A5E02354744-05 Parameter RangesAddress 312313314315317319151154 Description I0.0 to 127.7 (can be set up to 1023.7) 0.0 to 127.7 (can be set up to 2047.7) 0.0 to 255.7 (can be set up to 8191.7) 0.0 to 127.7 (can be set up to 2047.7) Input (in PII) IB0 to 127 (can be set up to 1023) 0 to 127 (can be set up to 2047) 0 to 255 (can be set up to 8191) 0 to 127 (can be set up to 2047) Input byte (in PII) IW0 to 126 (can be set up to 1022) 0 to 126 (can be set up to 2046) 0 to 254 (can be set up to 8190) 0 to 126 (can be set up to 2046) Input word(in PII) ID0 to 124 (can be set up to 1020) 0 to 124 (can be set up to 2044) 0 to 252 (can be set up to 8188) 0 to 124 (can be set up to 2044) Input double word (in PII) M0.0 to 255.70.0 to 2047.7 0.0 to 4095.7 0.0 to 8191 0.0 to 255.7 0.0 to 2047.7 Bit memory MB0 to 2550 to 2047 0 to 4095 0 to 8191 0 to 2550 to 2047Bit memory byte MW0 to 2540 to 2046 0 to 4094 0 to 8190 0 to 2540 to 2046Bit memory word MD0 to 2520 to 2044 0 to 4092 0 to 8188 0 to 2520 to 2044Bit memory double word L 2)0.0 to 2047.7Local data LB 2)0 to 2047Local data byte LW 2)0 to 2046Local data word LD 2)0 to 2044Local data double word 2) When using temporary variables, please note that these are only valid within the particular block or are available as parent local data of other blocks called in this block.After exit and renewed block call, it is not certain that the temporary variables will still include the same values that were present when the block call was closed previously.Temporary variables are initially undefined during the block call and must always be re-initialized each time they are used for the first time in the block. Address Identifiers and Parameter Ranges

Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-059 Parameter rangesAddress 312313314315317319151154 Description PQB0 to 10230 to 2047 0 to 81910 to 2047I/O output byte PQW0 to 10220 to 2046 0 to 81900 to 2046I/O output word PQD0 to 10200 to 2044 0 to 81880 to 2044I/O output double word PIB0 to 10230 to 2047 0 to 81910 to 2047I/O input byte PIW0 to 10220 to 2046 0 to 81900 to 2046I/O input word PID0 to 10200 to 2044 0 to 81880 to 2044I/O input double word T0 to 2550 to 5110 to 2047 0 to 255Timer C0 to 2550 to 5110 to 2047 0 to 255Counter The following addresses and address ranges apply to CPU 313C-2 DP, 314C-2 DP and 314C-2 PN/DP: Parameter rangesAddress 313C-2 DP314C-2 DP314C-2 PN/DP Description Q0.0 to 127.7 (can be set up 2047.7) 0.0 to 255.7 (can be set up to 2047.7) Output (in PIQ) QB0 to 127 (can be set up to 2047) 0 to 255 (can be set up to 2047) Output byte (in PIQ) QW0 to 126 (can be set up to 2046) 0 to 254 (can be set up to 2046) Output word (in PIQ) QD0 to 124 (can be set up to 2044) 0 to 252 (can be set up to 2044) Output double word (in PIQ) DB1 to 16000Data block DBX0.0 to 65533.7Data bit in data block DBB0 to 65533Data byte in DB DBW0 to 65532Data word in DB DBD0 to 65530Data double word in DB DI1 to 16000Instance data block DIX0.0 to 65533.7Data bit in instance DB DIB0 to 65533Data byte in instance DB DIW0 to 65532Data word in instance DB DID0 to 65530Data double word in instance DB Address Identifiers and Parameter Ranges

Instruction list S7-300 CPUs and ET 200 CPUs 10Parameter Manual, 06/2011, A5E02354744-05 Parameter rangesAddress 313C-2 DP314C-2 DP314C-2 PN/DP Description I0.0 to 127.7 (can be set up to 2047.7) 0.0 to 255.7 (can be set up to 2047.7) Inputs (in PII) IB0 to 127 (can be set up to 2047) 0 to 255 (can be set up to 2047) Input byte (in PII) IW0 to 126 (can be set up to 2046) 0 to 254 (can be set up to 2046) Input word (in PII) ID0 to 124 (can be set up to 2044) 0 to 252 (can be set up to 2044) Input double word (in PII) M0.0 to 255.7Bit memory MB0 to 255Bit memory byte MW0 to 254Bit memory word MD0 to 252Bit memory double word L 1)0.0 to 2047.7Local data LB 1)0 to 2047Local data byte LW 1)0 to 2046Local data word LD 1)0 to 2044Local data double word PQB0 to 2047I/O output byte PQW0 to 2046I/O output word PQD0 to 2044Peripheral output double word PIB0 to 2047I/O input byte PIW0 to 2046I/O input word PID0 to 2044Peripheral input double word T0 to 255Timer C0 to 255Counter 1) When using temporary variables, please note that these are only valid within the particular block or are available as parent local data of other blocks called in this block.After exit and renewed block call, it is not certain that the temporary variables will still include the same values that were present when the block call was closed previously.Temporary variables are initially undefined during the block call and must always be re-initialized each time they are used for the first time in the block. Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0511 Constants3Table 3- 1The following constants are used: ConstantDescription ParameterAddress, addressed via parameter B#16#Byte hexadecimal W#16#Word hexadecimal DW#16#Double word hexadecimal D#DateIEC date constant L#Integer32-bit integer constant P#BitpointerPointer constant S5T#TimeS5 time constant 1) (16 bit), T#1D_5H_3M_1S_2MS T#TimeTime constant (16/32 bit), T#1D_5H_3M_1S_2MS TOD#TimeIEC time constant, T#1D_5H_3M_1S_2MS C#Count valueCounter constant (BCD coded) 2#nBinary constant B (b1, b2) or B (b1, b2, b3, b4)Constant, 2 or 4 byte 1) Serves for loading the S5-Timer Constants

Instruction list S7-300 CPUs and ET 200 CPUs 12Parameter Manual, 06/2011, A5E02354744-05 Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0513 Abbreviations4Table 4- 1The abbreviations are used: Abbreviation... DescriptionExample k88-bit constant32 k1616-bit constant631 k3232-bit constant1272 5624 i88-bit integer-155 i1616-bit integer+6523 i3232-bit integer-2 222 222 mPointer constantP#240.3 nBinary constant1001 1100 pHexadecimal constantEA12 q32-bit floating-point number12.34567E+5 LABELSymbolic jump address (max. 4 characters) DEST aByte address2 bBit addressx.1 cAddress range (bit)I, Q, M, L, DBX, DIX fTimer/counter number5 gAddress range (byte)IB, QB, PIB, PQB MB, LB, DBB, DIB hAddress range (word)IW, QW, PIW, PQW, MW, LW, DBW, DIW iAddress range (double word)ID, QD, PID, PAD MD, LD, DBD, DID rBlock number10 ACRange of address memory cell RERange error (invalid range) Abbreviations

Instruction list S7-300 CPUs and ET 200 CPUs 14Parameter Manual, 06/2011, A5E02354744-05 Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0515 Registers5ACCU1 and ACCU2 (32 bit) The accumulators are registers for processing bytes, words or double words. The addresses are loaded into the accumulators, where they are logically gated. The result of the logic operation (RLO) is in ACCU1. The accumulators are 32 bit long. Table 5- 1Designations: AccumulatorBit ACCUx (x = 1 to 2)Bit 0 to 31 ACCUx-LBit 0 to 15 ACCUx-HBit 16 to 31 ACCUx-LLBit 0 to 7 ACCUx-LHBit 8 to 15 ACCUx-HLBit 16 to 23 ACCUx-HHBit 24 to 31 Address Registers AR1 and AR2 (32 bit) The address registers contain the areainternal or areacrossing addresses for instructions using indirect addressing. The address registers are 32 bit long. The areainternal and/or areacrossing addresses have the following syntax: Areainternal address: 00000000 00000bbb bbbbbbbb bbbbbxxx Areacrossing address: 10000yyy 00000bbb bbbbbbbb bbbbbxxx Legend for structure of addresses: b: Byte address x: Bit number y: Area identifier (see section: Examples of Addressing (Page 21)) Registers

Instruction list S7-300 CPUs and ET 200 CPUs 16Parameter Manual, 06/2011, A5E02354744-05 Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0517 Status Word6Status word (16 bit) The status word bits are evaluated or set by the instructions. The status word is 16 bit long. BitAssignmentDescription 0/FC 1) 2)First check, bit cannot be written and evaluated in the user program because it is not updated at program runtime. 1RLOResult of logic operation 2STA 1) 2)Status, bit cannot be written and evaluated in the user program because it is not updated at program runtime. 3OR 1) 2)Or, bit cannot be written and evaluated in the user program because it is not updated at program runtime. 4OSStored overflow 5OVOverflow 6CC0Result display 7CC1Result display 8BRBinary result 9 to 15Unassigned- 1) In the U-Stack display, the value "0" is always output. 2) In the display to STATUS block and breakpoint, the bit is displayed/refreshed correctly. Status Word

Instruction list S7-300 CPUs and ET 200 CPUs 18Parameter Manual, 06/2011, A5E02354744-05 Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0519 Addressing77.1Address types Table 7- 1The following address types are used: 1. access2. access CommandsIQMPLDBDIVIQMPLDBDIV A, AN, O, ON, X, XN, =, R, S, FP, FN - Directc 0.0cccccc Memory indirectc [AC D 0]ACACACACcccccc Memory indirect via block parameter [#par]cccREREccc Register indirect, area-internal c[AR1, P#..] c[AR2, P#..] cccccc Register indirect, area-crossing [AR1, P#..] [AR2, P#..] cccREcccc L, T - DirectcB 0. cW 0. cD 0 ccccccc Memory indirectcB[AC D 0] cW[AC D 0] cD]AC D 0] ACACACACccccccc Memory indirect via block parameter Bpar, Wpar, Dpar ccccREccc Register indirect, area-internal cB[AR1, P#..] cW[AR1, P#..] cD[AR1, P#..] cB[AR2, P#..] cW[AR2, P#..] cD[AR2, P#..] ccccccc Register indirect, area-crossing B[AR1, P#..] W[AR1, P#..] D[AR1, P#..] B[AR2, P#..] W[AR2, P#..] D[AR2, P#..] cccccccc Addressing 7.1 Address types Instruction list S7-300 CPUs and ET 200 CPUs 20Parameter Manual, 06/2011, A5E02354744-05 1. access2. access CommandsIQMPLDBDIVIQMPLDBDIV SP, SE, SD, SS, SF, R, FR, L, LC, A, AN, O, ON, X, XN - DirectT 0 Memory indirectT[AC W 0]ACACACAC Memory indirect via block parameter #Tpar S, CU, CD, R, FR, L, LC, A, AN, O, ON, X, XN - DirectC 0 Memory indirectC[AC W 0]ACACACAC Memory indirect via block parameter #Zpar UC, CC - DirectFB 0. FC 0 Memory indirectFB[AC W 0],FC[AC W 0] ACACACAC Memory indirect via block parameter FBpar, #FCpar OPN - DirectDB 0, DI 0 Memory indirectDB[AC W 0],DI[AC W 0] ACACACAC Memory indirect via block parameter DBpar, #FCpar 1) 1) The STL syntax prohibits opening the 2nd data block as block parameter. Definition of abbreviations c= address range (bit) AC= range of address memory cell; RE= Range error (invalid range) See also Abbreviations (Page 13) Examples of addressing (Page 21) Addressing 7.2 Examples of addressing Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0521 7.2Examples of addressing Examples of addressingDescription Immediate addressing L +27Load 16bit integer constant "27" into ACCU1 L L#1Load 32bit integer constant "-1" into ACCU1 L 2#1010101010101010Load binary constant into ACCU1 L DW#16#A0F0BCFDLoad hexadecimal constant into ACCU1 L 'END'Load ASCII character into ACCU1 L T#500 msLoad time value into ACCU1 L C#100Load count value into ACCU1 L B#(100,12)Load constant as 2 byte L B#(100,12,50,8)Load constant as 4 byte L P#10.0Load areainternal pointer into ACCU1 L P#E20.6Load areacrossing pointer into ACCU1 L -2.5Load real number into ACCU1 L D#19950120Load date L TOD#13:20:33.125Load time of day Direct Addressing A I 0.0ANDing of input bit 0.0 L IB1Load input byte 1 into ACCU1 L IW 0Load input word 0 into ACCU1 L ID 0Load input double word 0 into ACCU1 Indirect Addressing of Timers/Counters SP T [LW 8]Start timer; the timer number is in local data word 8 CU C [LW 10]Start counter; the counter number is in local data word 10 AreaInternal MemoryIndirect Addressing A I [LD 12]AND operation: The address of the input is in local data double word 12 as pointer Example: L P#22.2 T LD 12 A I [LD 12] A I [DBD 1]AND operation: The address of the input is in data double word 1 of the DB as pointer A Q [DID 12]AND operation: The address of the output is in data double word 12 of the instance DB as pointer A Q [MD 12]AND operation: The address of the output is in memory double word 12 as pointer Addressing 7.2 Examples of addressing Instruction list S7-300 CPUs and ET 200 CPUs 22Parameter Manual, 06/2011, A5E02354744-05 Examples of AddressingDescription Area-Internal Register-Indirect Addressing A I [AR1,P#12.2]AND operation: The address of the input is calculated from the pointer value in address register 1+ pointer P#12.2" Area-Crossing Register-Indirect Addressing 1) For areacrossing registerindirect addressing, bit 24 to 26 of the address must also contain an area identifier. The address is in the address register. Area IDCoding binaryCoding hexadecimal Area P1000 000080I/O area I1000 000181Input area Q1000 001082Output area M1000 001183Bit memory area DB1000 010084Data area DI1000 010185Instance data area L1000 011086Local data area VL1000 011187Predecessor local data area (access to local data of invoking block) L B [AR1,P#8.0]Load byte into ACCU1: The address is calculated from the "pointer value inAR1+P#8.0" A [AR1,P#32.3]AND operation: The address is calculated from the "pointer value in address register 1+ pointer P#32.3" Addressing Via Parameters A ParameterAddressing via parameters 1) Logic Instructions with timers and counters (Page 28) Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0523 Examples of how to calculate the pointer8 Example for sum of bit addresses 7: LAR1 P#8.2 A I [AR1,P#10.2] Result:Input 18.4 is addressed (by adding the byte and bit addresses) Example for sum of bit addresses >7: L MD 0Random pointer, e.g. P#10.5 LAR1 A I [AR1,P#10.7] Result:Input 21.4 is addressed (by adding the byte and bit addresses with carry) Examples of how to calculate the pointer

Instruction list S7-300 CPUs and ET 200 CPUs 24Parameter Manual, 06/2011, A5E02354744-05 Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0525 Instruction list9 This chapter contains the complete list of S7-300 instructions. The descriptions have been kept as concise as possible. Note Execution times For indirect addressing and special addresses, you have to also add to the execution times a time for loading of the address or the respective address. See also: Examples of addressing (Page 21) Address types (Page 19) Execution Time (Page 59) Additional information Detailed descriptions of the function are included in the STEP 7 reference manuals. See also Load Instructions for Timers and Counters (Page 35) Instruction list 9.1 Logic instructions Instruction list S7-300 CPUs and ET 200 CPUs 26Parameter Manual, 06/2011, A5E02354744-05 9.1Logic instructions 9.1.1Bit logic instructions Examining the signal state of the addressed instruction and gating the result with the RLO according to the appropriate logic function. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 A1)AND AN1)AND NOT 1/20,100,070,060,050,030,0040,060,05 Status word for: A, ANBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-----Yes-YesYes Instruction affects:-----YesYesYes1 O 1)OR ON1)OR NOT X 1)EXCLUSIVE OR XN 1)EXCLUSIVE OR NOT 1/20,100,070,060,050,030,0040,060,05 Status word for: O, ON, X, XNBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-------YesYes Instruction affects:-----0YesYes1 1) for valid addresses and parameter ranges see Address types (Page 19), Logic Instructions with Timers and Counters (Page 28) Instruction list 9.1 Logic instructions Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0527 9.1.2Bit logic instructions with parenthetical expressions Saving the BR, RLO and OR bits and a function identifier (A, AN, ...) to the nesting stack. Seven nesting levels are possible per block.The listed parentheses also apply to the "right parenthesis" instructions. Typ. execution time in sInstructionDescriptionLength in words 312313314315317319151154 A(AND left parenthesis AN(AND NOT left parenthesis O(OR left parenthesisON(OR NOT left parenthesis X(EXCLUSIVE OR left parenthesis XN(EXCLUSIVE OR NOT left parenthesis 10.280.180.150.120.050.0130.150.12 Status word for: A(, AN(, O(, ON(, X(, XN(BRCC1CC0OVOSORSTARLO/FC Instruction depends on:Yes----Yes-YesYes Instruction affects:-----01-0 )Right parenthesis, popping an entry off the nesting stack, gating the RLO with the current RLO in the processor 10.280.180.150.120.050.0130.150.12 Status word for: )BRCC1CC0OVOSORSTARLO/FC Instruction depends on:-------Yes- Instruction affects:Yes----Yes1Yes1 OORing of AND operations according to the rule: AND before OR 10.080.060.050.040.020.0080.050.04 Status word for: OBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-----Yes-YesYes Instruction affects:-----Yes1-Yes Instruction list 9.1 Logic instructions Instruction list S7-300 CPUs and ET 200 CPUs 28Parameter Manual, 06/2011, A5E02354744-05 9.1.3Logic Instructions with Timers and Counters Examining the signal state of the addressed timer/counter and gating the result with the RLO according to the appropriate logic function. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 T f 1)AND Timer0,600,300,260,230,130,020,260,23AC f 1)AND Counter0,300,150,120,100,050,010,120,10 T f 1)AND NOT Timer0,600,300,260,230,130,020,260,23ANC f 1)AND NOT Counter 1/2 0,300,150,120,100,050,010,120,10 Status word for: A, ANBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-----Yes-YesYes Instruction affects:-----YesYesYes1 T f 1)OR Timer0,600,300,260,230,130,020,260,23O C f 1)OR Counter0,300,150,120,100,050,010,120,10 T f 1)OR NOT Timer0,600,300,260,230,130,020,260,23ON C f 1)OR NOT Counter0,300,150,120,100,050,010,120,10 T f 1)EXCLUSIVE OR Timer 0,600,300,260,230,130,020,260,23X C f 1)EXCLUSIVE OR Counter 0,300,150,120,100,050,010,120,10 T f 1)EXCLUSIVE OR NOT Timer 0,600,300,260,230,130,020,260,23XN C f 1)EXCLUSIVE OR NOT Counter 1/2 0,300,150,120,100,050,010,120,10 Status word for: O, ON, X, XNBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-------YesYes Instruction affects:-----0YesYes1 1) for valid parameter ranges, see Address types (Page 19) Instruction list 9.1 Logic instructions Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0529 9.1.4Logic Instructions Using AND, OR and EXCLUSIVE OR Examining the specified conditions for their signal status, and gating the result with the RLO according to the appropriate function. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 A AND OOR XEXCLUSIVE OR == 0Result = 0 (CC1 = 0) and (CC0 = 0) > 0Result > 0 (CC1 = 1) and (CC0 = 0) < 0Result < 0 (CC1 = 0) and (CC0 = 1) 0Result 0 ((CC1 = 0) and (CC0 = 1) or (CC1 = 1) and (CC0 = 0)) = 0Result 0 ((CC1 = 1) and (CC0 = 0) or (CC1 = 0) and (CC0 = 0)) AOAND unordered/ invalid (CC1 = 1) and (CC0 = 1) OSAND OS = 1 BRAND BR = 1 OVAND OV = 1 10,300,110,090,080,030,010,090,08 Status word for: A, O, XBRCC1CC0OVOSORSTARLO/FC Instruction depends on:YesYesYesYesYesYes-YesYes Instruction affects:-----YesYesYes1 Instruction list 9.1 Logic instructions Instruction list S7-300 CPUs and ET 200 CPUs 30Parameter Manual, 06/2011, A5E02354744-05 Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 AN AND NOT ONOR NOT XNEXCLUSIVE OR NOT == 0Result = 0 (CC1 = 0) and (CC0 = 0) > 0Result > 0 (CC1 = 1) and (CC0 = 0) < 0Result < 0 (CC1 = 0) and (CC0 = 1) 0Result00 ((CC1 = 0) and (CC0 = 1) or (CC1 = 1) and (CC0 = 0)) = 0Result 0 ((CC1 = 1) and (CC0 = 0) or (CC1 = 0) and (CC0 = 0)) AOAND unordered/ invalid (CC1 = 1) and (CC0 = 1) OSAND OS = 1 BRAND BR = 1 OVAND OV = 1 10,300,110,090,080,030,010,090,08 Status word for: AN, ON, XNBRCC1CC0OVOSORSTARLO/FC Instruction depends on:YesYesYesYesYesYes-YesYes Instruction affects:-----YesYesYes1 Instruction list 9.2 EdgeTriggered Instructions Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0531 9.2EdgeTriggered Instructions Detection of an edge change. The current signal state of the RLO is compared with the signal state of the address or edge bit memory". FP detects a change in the RLO from "0" to "1". FN detects an edge change from "1" to "0". Auxiliary edge bit memory is the bit addressed in the instruction. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 FP 1)Detecting the positive edge in the RLO. FN 1)Detecting the negative edge in the RLO. 20,260,190,170,150,080,0150,170,15 Status word for: FP, FNBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-------Yes- Instruction affects:-----0YesYes1 1) for all valid addresses and parameter ranges see Address types (Page 19) 9.3Setting/Resetting Bit Addresses Assigning the value "1" or "0" or the RLO of the addressed instruction.The instructions can be MCR-dependent. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 S 1)Set input/output/bit memory/local data bit/data bit/instance data bit to "1" R1)Set input/ output/bit memory/local data bit/data bit/instance data bit to "0" =1)Assign RLO to input/output/bit memory/local data bit/data bit/instance data bit 20,140,100,090,080,040,010,090,08 Status word for: S, R, =BRCC1CC0OVOSORSTARLO/FC Instruction depends on:-------Yes- Instruction affects:-----0Yes-0 1) for all valid addresses and parameter ranges see Address types (Page 19) Instruction list 9.4 Instructions Directly Affecting the RLO Instruction list S7-300 CPUs and ET 200 CPUs 32Parameter Manual, 06/2011, A5E02354744-05 9.4Instructions Directly Affecting the RLO The following instructions have a direct effect on the RLO. Typ. execution time in sInstructionDescriptionLength in words 312313314315317319151154 CLR Set RLO to "0"20,070,060,050,040,020,0040,050,04 Status word for: CLRBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:-----0000 SETSet RLO to "1"20,070,060,050,040,020,0040,050,04 Status word for: SETBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:-----0110 NOTNegate RLO20,070,060,050,040,020,0040,050,04 Status word for: NOTBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-----Yes-Yes- Instruction affects:------1Yes- SAVERetain the RLO in the Bit BR20,080,060,050,040,020,0040,050,04 Status word for: SAVEBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-------Yes- Instruction affects:Yes-------- Instruction list 9.5 Timer Instructions Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0533 9.5Timer Instructions Starting or resetting a timer (addressed directly or via a parameter). The time value must be in ACCU1-L. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 SPT f 1)Start timer as pulse on edge change from "0" to "1" 1.200.790.630.480.190.0750.630.48 SET f 1)Start timer as extended pulse on edge change from "0" to "1" 1.110.730.570.460.180.0650.570.46 SDT f 1)Start timer as ON delay on edge change from "0" to "1" 1.310.900.690.530.210.0800.690.53 SST f 1)Start timer as retentive ON delay on edge change from "0" to "1" 1.250.840.660.510.200.0700.660.51 SFT f 1)Start timer as OFF delay on edge change from "1" to "0" 1.370.840.720.550.210.0800.720.55 FRT f 1)Enable timer for restarting on edge change from "0" to "1" (reset edge bit memory for starting timer) 1.280.830.670.520.200.0600.670.52 RT f 1)Reset timer 4/6 1.510.980.790.610.240.1150.790.61 Status word for: SP, SE, SD, SS, SF, FR, RBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-------Yes- Instruction affects:-----0--0 1) for valid parameter ranges, see Address types (Page 19) Instruction list 9.6 Counter Instructions Instruction list S7-300 CPUs and ET 200 CPUs 34Parameter Manual, 06/2011, A5E02354744-05 9.6Counter Instructions The count value is in ACCU1-L or in the address transferred as parameter. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 SC f 1)Presetting of counter on edge change from "0" to "1" 1.761.200.920.710.280.0900.920.71 RC f 1)Reset counter to 0" on edge change from "0" to "1" 1.150.730.600.460.170.0500.600.46 CUC f 1)Increment counter by 1 on edge change from "0" to "1" 1.220.790.640.490.200.0550.640.49 CDC f 1)Decrement counter by 1 on edge change from "0" to "1" 4/6 1.310.840.690.530.200.0600.690.53 FRC f 1)Enable counter on edge change from "0" to "1" (reset edge bit memory for up and down counting) 21.190.760.620.480.190.0550.620.48 Status word for: S, R, CU, CD, FRBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-------Yes- Instruction affects:-----0--0 1) for valid parameter ranges, see Address types (Page 19) Instruction list 9.7 Load Instructions Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0535 9.7Load Instructions Loading address identifiers into ACCU1. The contents of ACCU1 and ACCU2 are saved first. The status word is not affected. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 Load ... B 1)Byte 0,240,150,120,090,030,0070,120,09 W 1)Word 0,280,180,140,110,040,0100,140,11 DW 1)Double word1/2 0,320,200,160,120,040,0150,160,12 k8 2)8bit constant in ACCU1-LL 1 k16 2)16bit constant in ACCU1-L 2 L k32 2)32bit constant in ACCU1 3 0,240,150,120,090,030,0070,120,09 1) for all valid addresses and parameter ranges, see Address types (Page 19) 2) valid for all Constants (Page 11) 9.8Load Instructions for Timers and Counters Loading a time value or count value into ACCU1. The contents of ACCU1 are first saved to ACCU2. The condition code bits are not affected. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 LT f 1)Load time value1,701,300,800,800,340,1750,800,80 LCT f 1)Load time value BCD coded 2,711,731,411,090,430,2801,411,09 LC f 1)Load count value1,110,700,580,450,140,0500,580,45 LCC f 1)Load count value BCD coded 1/2 1,711,100,890,690,270,1550,890,69 1) for valid parameter ranges, see Address types (Page 19) Instruction list 9.9 Transfer Instructions Instruction list S7-300 CPUs and ET 200 CPUs 36Parameter Manual, 06/2011, A5E02354744-05 9.9Transfer Instructions Transferring the contents of ACCU1 to the addressed operand. The status word is not affected. Remember that some transfer instructions depend on the MCR. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 Transfer contents of... B 1)ACCU1-LL input byte 0.200.130.100.080.030.0070.100.08 W 1)ACCU1-L input word 0.240.150.120.090.030.0080.120.09 T DW 1)ACCU1 input double word 1/2 0.280.180.140.110.040.0100.140.11 1) for all valid addresses and parameter ranges, see Address types (Page 19) 9.10Load and Transfer Instructions for Address Registers Loading a double word from a memory area or register into AR1 or AR2. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 Load contents from ...... into AR1 -ACCU1 ...10,200,150,100,100,030,010,100,10 AR2Address register 2...10,200,150,100,100,030,010,100,10 DBD aData double word ...20,510,340,270,210,080,020,270,21 DID aInstance data double word ... 20,980,610,510,400,150,050,510,40 m32bit constant as pointer ... 30,300,180,150,120,040,010,150,12 LD aLocal data double word ... 20,510,340,270,210,080,020,270,21 LAR1 MD aBit memory double word ... 20,510,340,270,210,080,020,270,21 Instruction list 9.10 Load and Transfer Instructions for Address Registers Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0537 Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 Load contents from ...... into AR2 -ACCU1 ...10,200,150,100,100,030,010,100,10 DBD aData double word ...20,510,340,270,210,080,020,270,21 DID aInstance data double word ... 20,980,610,510,400,150,050,510,40 m32bit constant as pointer ... 30,300,180,150,120,040,010,150,12 LD aLocal data double word ... 20,510,340,270,210,080,020,270,21 LAR2 MD aBit memory double word ... 20,510,340,270,210,080,020,270,21 Transfer contents of AR1 to -ACCU110,300,190,160,130,040,020,160,13 AR2Address register 210,200,150,100,100,030,010,100,10 DBD aData double word20,390,260,210,170,060,020,210,17 DID aInstance data double word 20,930,590,490,380,140,0450,490,38 LD aLocal data double word 20,390,260,210,170,060,020,210,17 TAR1MD aBit memory double word ... 20,390,260,210,170,060,020,210,17 Transfer contents of AR2 to -ACCU110,300,190,160,130,040,020,160,13 DBD aData double word20,390,260,210,170,060,020,210,17 DID aInstance data double word 20,930,590,490,380,140,0450,490,38 LD aLocal data double word 20,390,260,210,170,060,020,210,17 TAR2 MD aBit memory double word 20,390,260,210,170,060,020,210,17 TARExchange the contents of AR1 and AR2 10,280,190,160,130,040,010,160,13 Instruction list 9.11 Load and Transfer Instructions for the Status Word Instruction list S7-300 CPUs and ET 200 CPUs 38Parameter Manual, 06/2011, A5E02354744-05 9.11Load and Transfer Instructions for the Status Word Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315 317319151154 LSTWLoad status word 1) into ACCU1 10,630,430,330,260,090,0250,330,26 Status word for: L STWBRCC1CC0OVOSORSTARLO/FC Instruction depends on:YesYesYesYesYes00Yes0 Instruction affects:--------- TSTWTransfer ACCU1 (bits 0 to 8) to the status word 1) 10,580,380,310,240,090,0200,310,24 Status word for: T STWBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:YesYesYesYesYes--Yes- 1) Structure of the status word, see: Status word(Page 17) 9.12Load Instructions for DB Number and DB Length Loading the number/length of a data block into ACCU1. The old contents of ACCU1 are saved to ACCU2. The condition code bits are not affected. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 LDBNOLoad number of data block LDINOLoad number of instance data block 10,270,180,150,120,040,010,150,12 LDBLGLoad length of data block into byte LDILGLoad length of instance data block into byte 10,340,220,190,140,040,010,190,14 Instruction list 9.13 Word Logic Instructions with the Contents of Accumulator 1 Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0539 9.13Word Logic Instructions with the Contents of Accumulator 1 Linking the contents of ACCU1 or ACCU1-L with a word or double word according to the appropriate function. The word or double word is either a constant in the instruction or in ACCU2. The result is in ACCU1 or ACCU1-L. Typ. execution time in sInstruction AddressDescriptionLength in words 312313314315317319151154 AWAND ACCU2-L OWOR ACCU2-L XOWEXCLUSIVE OR ACCU2-L 10.330.220.180.140.050.0140.180.14 AWk16AND 16-bit constant OWk16OR 16-bit constant XOWk16EXCLUSIVE OR 16-bit constant 20.330.220.180.140.050.0140.180.14 Status word for: AW, OW, XOWBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:-Yes00----- ADAND ACCU2 ODOR ACCU2 XODEXCLUSIVE OR ACCU2 10.280.190.160.130.050.0140.160.13 ADk32AND 32-bit constant ODk32OR 32-bit constant XODk32EXCLUSIVE OR 32-bit constant 30.280.190.160.130.050.0140.160.13 Status word for: AD, OD, XODBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:-Yes00----- Instruction list 9.14 Fixedpoint arithmetic (16/32-bit) / Floatingpoint arithmetic (32-bit) Instruction list S7-300 CPUs and ET 200 CPUs 40Parameter Manual, 06/2011, A5E02354744-05 9.14Fixedpoint arithmetic (16/32-bit) / Floatingpoint arithmetic (32-bit) Mathematical functions of two 16-/32-bit numbers. The result is in ACCU1 orACCU1-L. I = Integer 16 bit, D = Integer 32 bit, R = Real number 32 bit Typ. execution time in sInstructionDescriptionLength in words 312313314315317319151154 Add 2 integers or real numbers +I(ACCU1-L) = (ACCU1-L) + (ACCU2-L) 0.250.170.130.100.040.0100.130.10 +D(ACCU1) = (ACCU2) + (ACCU1) 0.220.150.120.090.030.0100.120.09 +R(ACCU1) = (ACCU2) + (ACCU1) 1.100.720.580.440.160.0400.580.44 Subtract 2 integers or real numbers I(ACCU1-L) = (ACCU2-L) - (ACCU1-L) 0.250.170.130.100.040.0100.130.10 D(ACCU1) = (ACCU2) - (ACCU1) 0.220.150.120.090.030.0100.120.09 R(ACCU1) = (ACCU2) - (ACCU1) 1 1.100.720.580.440.160.0400.580.44 Status word for: +I, +D, +R, -I, -D, -RBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:-YesYesYesYes---- Instruction list 9.14 Fixedpoint arithmetic (16/32-bit) / Floatingpoint arithmetic (32-bit) Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0541 Typ. execution time in sInstructionDescriptionLength in words 312313314315317319151154 Multiply 2 integers or real numbers *I(ACCU1) = (ACCU2-L) * (ACCU1-L) 0.280.180.150.120.040.0100.150.12 *D(ACCU1) = (ACCU2) * (ACCU1) 0.210.150.120.090.030.0080.120.09 *R(ACCU1) = (ACCU2) * (ACCU1) 1.110.710.580.440.160.0400.580.44 Divide 2 integers or real numbers /I(ACCU1-L) = (ACCU2-L): (ACCU1-L) The remainder of the division is in ACCU1-H 0.520.340.270.220.080.0600.270.22 /D(ACCU1) = (ACCU2): (ACCU1) 0.510.330.270.210.080.0500.270.21 /R(ACCU1) = (ACCU2): (ACCU1) 4.853.002.521.890.250.0602.521.89 MODDivide 2 integers (32 bit) and load the remainder of the division in ACCU1:(ACCU1) = Remainder of [(ACCU2): (ACCU1)] 1 0.430.290.230.180.070.0600.230.18 Status word for: *I, *D, *R, /I, /D, /R, MODBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:-YesYesYesYes---- NEGRNegate the real number in ACCU1 0.200.140.120.090.030.0050.120.09 ABSForm the absolute value of the real number in ACCU1 1 0.200.140.120.090.030.0050.120.09 Status word for: NEGR, ABSBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:--------- Instruction list 9.15 Square root, square (32 bit)/logarithm function (32 bit) Instruction list S7-300 CPUs and ET 200 CPUs 42Parameter Manual, 06/2011, A5E02354744-05 9.15Square root, square (32 bit)/logarithm function (32 bit) The result of the instruction / logarithm function is in ACCU1. The instructions can be interrupted by interrupts. Typ. execution time in sInstructionDescriptionLength in words 312313314315317319151154 SQRTCalculate the square root of a real number in ACCU1 8,145,164,223,241,260,4754,223,24 SQRForm the square of a real number in ACCU1 1 1,150,730,590,460,180,0400,590,46 LNForm the natural logarithm of a real number in ACCU1 7,344,653,802,921,200,4553,802,92 EXPCalculate the exponential value of a real number in ACCU1 to the base e (= 2.71828) 1 9,135,804,733,631,500,5254,733,63 Status word for: SQRT, SQR, LN, EXPBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:-YesYesYesYes---- Instruction list 9.16 Trigonometrical functions (32 bits) Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0543 9.16Trigonometrical functions (32 bits) The result of the instruction is in ACCU1. The instructions can be interrupted by interrupts. Typ. execution time in sInstructionDescriptionLength in words 312313314315317319151154 SIN1)Calculate the sine of a real number 7,524,773,903,001,200,5303,903,00 ASIN2)Calculate the arcsine of a real number 15,80 10,238,406,441,300,4808,406,44 COS1)Calculate the cosine of a real number 9,195,784,753,651,500,5304,753,65 ACOS2)Calculate the arccosine of a real number 7,214,563,732,871,200,4503,732,87 TAN1)Calculate the tangent of a real number 10,92 6,935,674,351,800,6205,674,35 ATAN2)Calculate the arctangent of a real number 1 7,915,104,103,141,300,4854,103,14 Status word for: SIN, ASIN, COS, ACOS, TAN, ATAN BRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:-YesYesYesYes---- 1) Specify the angle in radians; the angle must be given as a floating point value in ACCU1. 2) The result is an angle in radians. 9.17Adding Constants Adding integer constants and storing the result in ACCU1. The condition code bits are not affected. Typ. execution time in sInstructionAddressDescriptionLength in words312313314315317319151154 + i8Add an 8bit integer constant 10,200,140,100,100,050,010,100,10 +i16Add an 16bit integer constant 20,200,140,100,100,050,010,100,10 +i32Add an 32bit integer constant 30,200,140,100,100,050,010,100,10 Instruction list 9.18 Adding Using Address Registers Instruction list S7-300 CPUs and ET 200 CPUs 44Parameter Manual, 06/2011, A5E02354744-05 9.18Adding Using Address Registers Adding an integer (16 bit) to the contents of the address register. The value is in the operation or in ACCU1-L. The condition code bits are not affected. Typ. execution time in sInstructionAddressDescriptionLength in words312313314315317319151154 +AR1-Add the contents of ACCU1-L to AR1 10.200.160.100.100.070.010.100.10 +AR1mAdd a pointer constant to the contents of AR1 20.400.200.150.120.070.010.150.12 +AR2-Add the contents of ACCU1-L to AR2 10.200.160.100.100.070.010.100.10 +AR2mAdd pointer constant to the contents of AR2 20.400.200.150.120.070.010.150.12 Instruction list 9.19 Comparison instructions with integers (16/32 bit) or with 32-bit real numbers Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0545 9.19Comparison instructions with integers (16/32 bit) or with 32-bit real numbers Comparison of integers (16 bit) in ACCU1-L and ACCU2-L. RLO = 1, if the condition is satisfied. Comparison of integers (32 bit) in ACCU1 and ACCU2. RLO = 1, if the condition is satisfied. Comparison of 32bit real numbers in ACCU1 and ACCU2. RLO = 1, if the condition is satisfied. Typ. execution time in sInstructionDescriptionLength in words 312313314315317319151154 ==I ==D ==R ACCU2-L = ACCU1-L ACCU2 = ACCU1 ACCU2 = ACCU1 0,48 0,43 1,67 0,31 0,28 1,07 0,26 0,23 0,87 0,20 0,18 0,67 0,07 0,06 0,27 0,028 0,023 0,046 0,26 0,23 0,87 0,20 0,18 0,67 I D R ACCU2-L ACCU1-L ACCU ACCU1 ACCU ACCU1 0,48 0,43 1,67 0,31 0,28 1,07 0,26 0,23 0,87 0,20 0,18 0,67 0,07 0,06 0,27 0,028 0,023 0,046 0,26 0,23 0,87 0,20 0,18 0,67 ACCU1 0,48 0,43 1,67 0,31 0,28 1,07 0,26 0,23 0,87 0,20 0,18 0,67 0,07 0,06 0,27 0,028 0,023 0,046 0,26 0,23 0,87 0,20 0,18 0,67 >=I >=D >=R ACCU2-L ACCU1-L ACCU2 ACCU1 ACCU2 ACCU1 1 0,48 0,43 1,67 0,31 0,28 1,07 0,26 0,23 0,87 0,20 0,18 0,67 0,07 0,06 0,27 0,028 0,023 0,046 0,26 0,23 0,87 0,20 0,18 0,67 Status word for: == I, ==D, I, D, =D BRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:-YesYes0-0YesYes1 Status word for: ==R, R, =RBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:-YesYesYesYes0YesYes1 Instruction list 9.20 Shift Instructions Instruction list S7-300 CPUs and ET 200 CPUs 46Parameter Manual, 06/2011, A5E02354744-05 9.20Shift Instructions Shift the contents of ACCU1 or ACCU1-L to the left or right by the number of specified digits. If no address is specified, shift by the number of digits to ACCU2-LL. Any positions that become free are filled with zeros or with the sign. The last bit shifted is in condition code bit CC1. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 Shift the contents of ACCU1-L to the left. SLW 0 ... 15Positions that become free are filled with zeros. 0.510.340.270.210.080.0190.270.21 Shift the contents of ACCU1 to the left. SLD 0 ... 32Positions that become free are filled with zeros. 0.460.300.240.190.070.0190.240.19 Shift the contents of ACCU1-L to the right. SRW 0 ... 15Positions that become free are filled with zeros. 0.510.240.270.210.080.0190.270.21 Shift the contents of ACCU1 to the right. SRD 0 ... 32Positions that become free are filled with zeros. 0.460.300.240.190.070.0190.240.19 Shift the contents of ACCU1L with sign to the right. SSI 0 ... 15Positions that become free are filled with the sign (bit 15). 0.600.360.300.230.090.0190.300.23 Shift the contents of ACCU1 with sign to the right. SSD 0 ... 32Positions that become free are filled with the sign (bit 31). 1 0.460.310.270.190.080.0190.270.19 Status word for: SLW, SLD, SRW, SRD, SSI, SSDBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:-YesYesYes----- Instruction list 9.21 Rotate Instructions Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0547 9.21Rotate Instructions Rotate the contents of ACCU1 to the left or right by the specified number of places. If no address is specified, rotate the number of places in ACCU2-LL. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 RLD- 0 ... 32 Rotate the contents of ACCU1 to the left 0.450.290.240.190.070.0190.240.19 RRD- 0 ... 32 Rotate the contents of ACCU1 to the right 1 0.450.290.240.190.070.0190.240.19 Status word for: RLD, RRDBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:-YesYesYes----- RLDA-Rotate the contents of ACCU1 one bit position to the left via condition code bit CC10.300.200.160.130.050.0120.160.13 RRDA-Rotate the contents of ACCU1 one bit position to the left via condition code bit CC11 0.300.200.160.130.050.0150.160.13 Status word for: RLDA, RRDABRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:-Yes00----- Instruction list 9.22 ACCU-transfer instructions, incrementing and decrementing Instruction list S7-300 CPUs and ET 200 CPUs 48Parameter Manual, 06/2011, A5E02354744-05 9.22ACCU-transfer instructions, incrementing and decrementing The status word is not affected. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 TAW-Reverse the order of the bytes in ACCU1-L; LL, LH becomes LH, LL. 0.200.130.100.100.050.010.100.10 CAD-Reverse the order of the bytes in ACCU1. LL, LH, HL, HH becomes HH, HL, LH, LL. 0.400.240.200.160.060.010.200.16 TAK-Swap the contents of ACCU1 and ACCU2 0.250.170.140.110.040.010.140.11 PUSH-The contents of ACCU1 are transferred to ACCU2. 0.200.130.100.080.030.010.100.08 POP-The contents of ACCU2 are transferred to ACCU1. 0.200.140.100.080.030.010.100.08 INC0 ... 255Increment ACCU1-LL0.200.140.100.100.050.010.100.10 DEC0 ... 255Decrement ACCU1-LL 1 0.200.140.100.100.050.010.100.10 9.23Program Display and Null Operation Instructions The status word is not affected. Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 BLD1)0 ... 255Program display instruction: Is treated by the CPU like a null operation instruction. 0,000,000,000,000,000,000,000,00 NOP2)0 1 Null operation 1 0,000,000,000,000,000,000,000,00 1)The BLD instructions are generated and used by the programming device and should not be deleted, changed or added to. 2)The NOP1 instruction should not be used. If you require a NOP instruction, use NOP0. Instruction list 9.24 Data Type Conversion Instructions Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0549 9.24Data Type Conversion Instructions The results of the conversion are in ACCU1. When converting real numbers, the execution time depends on the value. Typ. execution time in sInstructionDescriptionLength in words 312313314315317319151154 BTIConvert ACCU1 from BCD to integer (16 bit)(BCD To Integer) 0,730,460,390,300,110,0400,390,30 BTDConvert ACCU1 from BCD to integer (32 bit)(BCD To Doubleinteger) 1,080,670,570,440,160,0900,570,44 DTRConvert ACCU1 from integer (32 bit) to real (32 bit) (Doubleint. To Real) 0,700,450,370,290,110,0200,370,29 ITDConvert ACCU1 from integer (16 bit) to integer (32 bit) (Integer To Doubleinteger) 1 0,210,140,100,090,030,0080,100,09 Status word for: BTI, BTD, DTR, ITDBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:--------- ITBConvert ACCU1 from integer (16 bit) to BCD 0 to 999 (Integer To BCD) 1,090,700,570,440,170,1170,570,44 DTBConvert ACCU1 from integer (32 bit) to BCD 0 to 9 999 999 (Doubleinteger To BCD) 2,981,901,541,190,470,3151,541,19 RNDConvert a real number into a 32-bit integer. 4,823,062,491,920,150,0252,491,92 RND- Convert a real number into a 32-bit integer. The number is rounded to the next integer. 4,823,062,491,920,150,0252,491,92 RND+Convert a real number into a 32-bit integer. The number is rounded to the next integer. 4,823,062,491,920,150,0252,491,92 TRUNCConvert a real number into a 32-bit integer. The places after the decimal point are truncated. 1 4,823,062,491,920,150,0252,491,92 Status word for: ITB, DTB, RND, RND-, RND+, TRUNC BRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:---YesYes---- Instruction list 9.25 Forming the Ones and Twos Complements Instruction list S7-300 CPUs and ET 200 CPUs 50Parameter Manual, 06/2011, A5E02354744-05 9.25Forming the Ones and Twos Complements Typ. execution time in sInstructionDescriptionLength in words 312313314315317319151154 INVIForm the ones complement of ACCU1-L 0.130.100.080.070.040.0100.080.07 INVDForm the ones complement of ACCU1 1 0.110.090.070.060.030.0050.070.06 Status word for: INVI, INVDBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:--------- NEGIForm the twos complement of ACCU1-L (integer) 0.160.120.100.080.050.0100.100.08 NEGDForm the twos complement of ACCU1 (double integer) 1 0.120.090.070.060.030.0050.070.06 Status word for: NEGI, NEGDBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:-YesYesYesYes---- 9.26Block Call Instructions Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 CALLFB p, DB rUnconditional call of an FB, with parameter transfer 15,103,252,652,050,780,352,652,05 CALLSFB p, DB r Unconditional call of an SFB, with parameter transfer 2 1) CALLFC pUnconditional call of a function, with parameter transfer 14,873,152,592,030,830,352,592,03 CALLSFC pUnconditional call of an SFC, with parameter transfer 2 1) Status word for: CALLBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:----001-0 1) in chapter: System Functions (SFC) (Page 71) System Function Blocks (SFB) (Page 79) Instruction list 9.26 Block Call Instructions Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0551 Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 FBq3,972,532,061,590,620,302,061,59 FCq Unconditional call of blocks without parameter transfer 4,262,762,271,770,720,302,271,77 UC ParameterFB/FC call via parameter 1 4,262,762,271,770,720,302,271,77 FBq3,972,532,061,590,620,302,061,59 FCq Conditional call of blocks without parameter transfer4,262,762,271,770,720,302,271,77 CC ParameterFB/FC call via parameter 1 4,262,762,271,770,720,302,271,77 Status word for: UC, CCBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:----001-0 DBpOpen data block1/2 2)0,400,280,210,170,080,020,210,17 DIpOpen instance data block20,400,280,210,170,080,020,210,17 OPN 3) ParameterOpen instance data block20,400,280,210,170,080,020,210,17 Status word for: OPNBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:--------- 2) For long block numbers (> 255) 3) The CPUs offer high-performance support of symbolic programming. The fully qualified DB accesses (e.g. DB100.DBX 1.2) used here generally cause no additional runtimes. This applies also for the OPN DB command contained in the access. Instruction list 9.27 Block End Instructions Instruction list S7-300 CPUs and ET 200 CPUs 52Parameter Manual, 06/2011, A5E02354744-05 9.27Block End Instructions Typ. execution time in sInstructionDescriptionLength in words 312313314315317319151154 BEEnd block1,201,090,880,680,260,070,880,68 BEA End block absolute 1 1,201,090,880,680,260,070,880,68 Status word for: BE, BEABRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:----001-0 BEC End block conditionally if RLO = "1" 11,201,090,880,680,260,070,880,68 Status word for: BECBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-------Yes- Instruction affects:----Yes0110 9.28Exchange Data Blocks Exchanging the two current data blocks. The current data block becomes the current instance data block and vice versa. The condition code bits are not affected. Typ. execution time in sInstructionDescriptionLength in words 312313314315317319151154 CDB Exchange data blocks10,200,150,100,100,100,050,100,10 Instruction list 9.29 Jump instructions Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0553 9.29Jump instructions Jump depends on the condition. With 8bit addresses, the jump width is between (-128 and +127). In the case of 16bit addresses, the jump width lies between (-32768 and -129) or (+128 and +32767). Note Please note for S7-300 CPU programs that the jump instructions starting from a logic string or into a logic string are invalid. Instructions that set /FC = 0 indicate the end of a logic string.The beginning is the first logic instruction after the end of a logic string. Here the linear program sequence is relevant without taking into consideration the jump instructions. Note that AND before OR also indicates the beginning of a new logic string. Jump instructions into a different nesting level are also invalid. Examples of jump instructions (Page 56) Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 JCLABELJump conditionally if RLO = "1" 1 1) /20.390.260.210.160.100.010.210.16 JCNLABELJump conditionally if RLO = "0" 20.390.260.210.160.100.010.210.16 Status word for: JC, JCNBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-------Yes- Instruction affects:-----0110 JCBLABELJump conditionally if RLO ="1"; Save the RLO in the BR bit 20.390.260.210.160.100.010.210.16 JNBLABELJump conditionally if RLO ="0"; Save the RLO in the BR bit 20.390.260.210.160.100.010.210.16 Status word for: JCB, JNBBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-------Yes- Instruction affects:Yes----0110 1)1 word long for jump width of -128 to +127 Instruction list 9.29 Jump instructions Instruction list S7-300 CPUs and ET 200 CPUs 54Parameter Manual, 06/2011, A5E02354744-05 Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 JBILABELJump conditionally if BR = "1" 20.390.260.210.160.100.010.210.16 JNBILABELJump conditionally if BR = "0" 20.390.260.210.160.100.010.210.16 Status word for: JBI, JNBIBRCC1CC0OVOSORSTARLO/FC Instruction depends on:Yes-------- Instruction affects:-----01-0 JOLABELJump conditionally on stored overflow (OS = "1") 1 1) /20.390.260.210.160.100.010.210.16 Status word for: JOBRCC1CC0OVOSORSTARLO/FC Instruction depends on:---Yes----- Instruction affects:--------- JOSLABELJump conditionally on stored overflow (OS = "1") 20.390.260.210.160.100.010.210.16 Status word for: JOSBRCC1CC0OVOSORSTARLO/FC Instruction depends on:----Yes---- Instruction affects:----0---- JIILABELJump conditionally if "invalid instruction" (CC1 = 1 and CC0 = 1) 20.390.260.210.160.100.010.210.16 JZLABELJump conditionally result = 0 (CC1 = 0 and CC0 = 0) 1 1) /20.390.260.210.160.100.010.210.16 JPLABELJump conditionally if result > 0 (CC1 = 1 and CC0 = 0) 1 1) /20.390.260.210.160.100.010.210.16 JMLABELJump conditionally if result < 0 (CC1 = 0 and CC0 = 1) 1 1) /20.390.260.210.160.100.010.210.16 Status word for: JII, JZ, JP, JMBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-YesYes------ Instruction affects:--------- 1)1 word long for jump width of -128 to +127 Instruction list 9.29 Jump instructions Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0555 Typ. execution time in sInstructionAddressDescriptionLength in words 312313314315317319151154 JNLABELJump conditionally if result 00; (CC1 = 1 and CC0 = 0) or (CC1 = 0) and (CC0 = 1) 1 1) /20.390.260.210.160.100.010.210.16 JMZLABELJump conditionally if result 0; (CC1 = 0 and CC0 = 1) or (CC1 = 0 and CC0 = 0) 20.390.260.210.160.100.010.210.16 JPZLABELJump conditionally if result 0; (CC1 = 1 and CC0 = 0) or (CC1 = 0) and (CC0 = 0) 20.390.260.210.160.100.010.210.16 Status word for: JN, JMZ, JPZBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-YesYes------ Instruction affects:--------- JULABELJump unconditionally 1 1) /20.390.260.210.160.100.0100.210.16 JLLABELJump distributor The instruction is followed by a list of jump instructions. The address is a jump label to the following instruction in the list. ACCU1-L includes the number of the jump instruction to be executed 20.390.260.210.160.100.0320.210.16 LOOPLABELDecrement ACCU1-L and jump ifACCU1-L 00 (loop programming) 20.350.240.190.150.060.0100.190.15 Status word for: JU, JL, LOOPBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:--------- 1) 1 word long for jump width of -128 to +127 Instruction list 9.29 Jump instructions Instruction list S7-300 CPUs and ET 200 CPUs 56Parameter Manual, 06/2011, A5E02354744-05 9.29.1Examples of jump instructions // Example 1: Invalid jump over the end of a logic string M = 10.0M = 20.0M = 10.1M 0.0M 2.0M 0.1L01L01:AAJO// End of logic string 1// End of logic string 3// End of logic string 2// Start of logic string 2// Start of logic string 3// Jump is not permitted because it exceeds the end of the logic stringA // Example 2: Invalid jump at the end of a logic string M = 10.0M = 20.0M = 10.1M 0.0M 2.0M 0.1L02L02: AAAJO// End of logic string 1// End of logic string 4// Start of logic string 3// End of logic string 3// Start of logic string 2// Start of logic string 4// End of logic string 2, because JC sets status bit /FC=0. Jump is permitted because it is at the end of the logic string. // Example 3: Valid jump within a logic string M = 10.0M = 20.0M = 10.1M 0.0M 0.1M 0.2M 2.0M 0.3M 0.4L03L03:AAAAAAJO// End of logic string 1// End of logic string 3// Jump to label within logic string is permitted// End of logic string 2// Start of logic string 2// Logic instructions// Start of logic string 3Jump within logic string is permitted.JO does not end the logic string. Instruction list 9.29 Jump instructions Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0557 // Example 4: Valid jump over and past a logic string M = 10.0M = 20.0M = 10.1M 0.0M 0.1M 2.0M 0.2M 0.3M 0.4L04L04: AAAAAAJO// End of logic string 1// End of logic string 3// End of logic string 2// Start of logic string 2// Logic instructions// Start of logic string 3. Jump to label is permitted,because jump is not within a logic string// Jump over logic string is permitted // Example 5: Invalid jumps between nesting levels M = 10.0M = 20.0M 0.0M 0.1M 0.2M 0.3M 0.4M 2.0))L05b:L05bL05aL05a:AAAA(AAAJZA(JO// End of logic string 1// Label is located in different nesting level than jump// Label is located in different nesting level than jump// Jump from nesting level is not permitted// Jump to another nesting level is not permitted // Example 6: Invalid jumps in AND before OR gatings M = 10.0M = 20.0M 0.1M 0.2M 0.3M 0.0M 0.4M 0.5M 0.6L06b:M = 20.0L06bL06aL06a:AAAAAAAOJZJO// End of logic string 1// Label is outside of link// Start of first AND or OR logic string// Jump to second AND or OR logic string is not permitted// AND before OR operation// Start of second AND before OR logic string// Label is located in different logic string than jump// Jump from AND before OR logic string is not permitted Instruction list 9.30 Instructions for the Master Control Relay (MCR) Instruction list S7-300 CPUs and ET 200 CPUs 58Parameter Manual, 06/2011, A5E02354744-05 9.30Instructions for the Master Control Relay (MCR) MCR=1 MCR is deactivated MCR=0 MCR is activated; "T" and "=" instructions write zeros to the corresponding addresses; "S" and "R" instructions leave the memory contents unchanged. Typ. execution time in sInstructionDescriptionLength in words 312313314315317319151154 MCR(Open an MCR zone. Save the RLO to the MCR stack. 0,210,170,150,130,080,030,150,13 )MCRClose an MCR zone. Save the RLO to the MCR stack. 1 0,210,170,150,130,080,030,150,13 Status word for: MCR (, )MCRBRCC1CC0OVOSORSTARLO/FC Instruction depends on:-------Yes- Instruction affects:-----01-0 MCRAActivate the MCR0,200,150,100,100,070,030,100,10 MCRDDeactivate the MCR 1 0,200,150,100,100,070,030,100,10 Status word for: MCRA, MCRDBRCC1CC0OVOSORSTARLO/FC Instruction depends on:--------- Instruction affects:--------- Instruction list 9.31 Execution Times Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0559 9.31Execution Times 9.31.1Execution Time You have to calculate the basic execution times for direct/indirect addressing. In this chapter we will explain the calculation to you. Two-Part Statement A statement consists of two parts: Part 1: Executing the instruction (see starting with chapter: Logic Instructions (Page 26)) Part 2: Loading the address (as of next table) This means that you also have to calculate the basic execution time of a statement with address from these two parts. Calculating the Execution Time +=The following applies to the basic execution time:Execution time of the instructionBasic execution time of the instructionExecution time for loading of address The execution times listed in the chapter "List of Instructions" apply to the second part of an instruction, which means the actual execution of an instruction. You must then add the time required for loading the address to this execution time (see following table). Instruction list 9.31 Execution Times Instruction list S7-300 CPUs and ET 200 CPUs 60Parameter Manual, 06/2011, A5E02354744-05 9.31.2Loading the Addresses and Operands Typ. execution time in sAddress areaExample 312313314315317319151154 Direct addressing L 1.234567e3600000000 I/O A I a.b00000000 M A M a.b00000000 L A L a.b00000000 DB/DI fully qualified 1)DB100.DBX10.300000000 DB/DI partly qualifiedDBX10.3 with unknown DB number (e.g. after ON DB[MW20]) 0,120,090,060,040,020,010,060,04 Timer 00000000 Counter 00000000 I/O access 2) 1) The CPUs offer high-performance support of symbolic programming. The fully qualified DB accesses (e.g. DB100.DBX 1.2) supported here generally cause no additional runtimes. This applies also for the OPN DB command contained in the access. 2) See table: Execution times for address access to I/O - direct and indirect addressing (PI/PO) (Page 61) 9.31.3Execution times for address access - indirect addressing Typ. execution time in sAddress areaExample 312313314315317319151154 Areainternal, register indirect addressing (AR1/AR2) = Q [AR1, P#1.1]0,280,160,140,100,030,0150,140,10 Areacrossing, register indirect addressing (AR1/AR2) = [AR1, P#1.0]0,880,550,440,330,110,050,440,33 Memory-indirect addressing= Q [MD2]0,640,400,320,240,080,040,320,24 Addressing via parametersA FC_Parameter0,120,080,060,040,020,010,060,04 Access to FB instance dataA FC_Parameter, L Var_Stat 0,120,080,060,040,020,010,060,04 Timer L T [MW2]0,960,600,480,360,120,100,480,36 Counter L C [MW2]0,960,600,480,360,120,100,480,36 I/O access 1) 1) See table:Execution times for address access to I/O - direct and indirect addressing (PI/PO) (Page 61) Instruction list 9.31 Execution Times Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0561 9.31.4Execution times for address access to I/O - direct and indirect addressing (PI/PO) Additional runtimes for address access in s (typ.)AddressI/O areasExample 312313314315-2 DP 317-2 DP 315-2 PN/DP 317-2 PN/DP 319151154 Load byteL PIB 014.367.8 Load WordL PIW 018.171.8 Load DWordL PID 035.680.2 Transfer byteT PQB 011.263.4 Transfer WordT PQW 012.767.4 Transfer DWord Central T PQD 025.075.2 Load byteL PIB 1244.4-- Load WordL PIW 1244.5-- Transfer byte T PQB 1244.5-- Transfer WordDigital on-board I/O 1) T PQW 124-4.2-- Load byteL PIB 752-4.7-- Load WordL PIW 752-4.9-- Load DWordL PID 752-6.1-- Transfer byte T PQB 752-4.0-- Transfer Word T PQW 752-4.1-- Transfer DWordAnalog on-board I/O 2) T PQD 752-4.4-- Load byteL PIB 0-3.9 3)3.91.73.9 Load WordL PIW 0-4.1 3)4.11.84.1 Load DWordL PID 0-4.2 3)4.21.84.2 Transfer byteT PQB 0-3.9 3)3.90.73.9 Transfer WordT PQW 0-4.1 3)4.10.74.1 Transfer DWord Distributed (PROFIBUS) T PQD 0-4.3 3)4.30.84.3 1) C-CPUs only 2) CPU 313C, CPU 314C-2 DP, CPU 314C-2 PtP, and CPU 314C-2 PN/DP only 3) CPU 313C-2 DP, 314C-2 DP and 314C-2 PN/DP only Instruction list 9.32 Master Control Relay - active (MCR) Instruction list S7-300 CPUs and ET 200 CPUs 62Parameter Manual, 06/2011, A5E02354744-05 Additional runtimes for address access in s (typ.)AddressI/O areasExample 312313314315-2 DP 317-2 DP 315-2 PN/DP 317-2 PN/DP 319151154 Load byteL PIB 0-6.6 4)-6.62.26.6 5) Load WordL PIW 0-6.7 4)-6.72.26.7 5) Load DWordL PID 0-8.0 4)-8.05.98.0 5) Transfer byteT PQB 0-7.8 4)-7.82.27.8 5) Transfer WordT PQW 0-7.9 4)-7.92.27.9 5) Transfer DWord Distributed (PROFINET) T PQD 0-7.9 4)-7.92.37.9 5) 4) Only CPU 314C-2 PN/DP 5) These values do not apply to IM151-7 CPU 9.32Master Control Relay - active (MCR) For the execution times in the active MCR area, an addition must be calculated for each command. In the active MCR area, the runtime additions per command in s are as follows: 312313314315317319151154 0,400,350,300,200,070,040,300,20 Instruction list 9.33 Calculating the execution time using CPU 315-2 DP as an example Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0563 9.33Calculating the execution time using CPU 315-2 DP as an example You will find a few examples here for calculating the execution times for the various methods of indirect addressing. Execution times are calculated for the CPU 315-2 DP. Calculating the Execution Time for AreaInternal MemoryDirect Addressing Example: A M 0.0 1. Step: Execution time of instruction (times: Bit logic instructions (Page 26)) InstructionDescriptionTyp. execution time in s AAND0,05 2. Step: Execution times of address access (times: Loading the Addresses and Operands (Page 60)) Address areaTyp. execution time in s M0 Total execution time:0.05 s + 0.00 s = 0.05 s Calculating the Execution Time for AreaInternal MemoryIndirect Addressing Example: A I [DBD 12] 1. Step: Execution time of instruction (times: Bit logic instructions (Page 26)) InstructionDescriptionTyp. execution time in s AAND0,05 2. Step: Execution times of address access (times: Execution times for address access - indirect addressing (Page 60)) Address areaTyp. execution time in s Memory-indirect addressing0,24 Total execution time:0.05 s + 0.24 s = 0.29 s Instruction list 9.33 Calculating the execution time using CPU 315-2 DP as an example Instruction list S7-300 CPUs and ET 200 CPUs 64Parameter Manual, 06/2011, A5E02354744-05 Calculating the Execution Time for AreaInternal Register-Indirect Addressing Example: A I [AR1, P#34.3] 1. Step: Execution time of instruction (times: Bit logic instructions (Page 26)) InstructionDescriptionTyp. execution time in s AAND0,05 2. Step: Execution times of address access (times: Execution times for address access - indirect addressing (Page 60)) Address areaTyp. execution time in s Area-internal, register-indirect addressing0,10 Total execution time:0.05 s + 0.10 s = 0.15 s Calculating the Execution Time for AreaCrossing RegisterIndirect Addressing Example: A [AR1, P#23.1] ... with P#E1.0 in AR1 1. Step: Execution time of instruction (times: Bit logic instructions (Page 26)) InstructionDescriptionTyp. execution time in s AAND0,05 2. Step: Execution times of address access (times Execution times for address access - indirect addressing (Page 60)) Address areaTyp. execution time in s Areacrossing, registerindirect addressing0,33 Total execution time: 0.05 s + 0.33 s = 0.38 s Instruction list 9.34 Example of I/O Access Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0565 Execution Time for Addressing via Parameters Example: A "Start"... The parameter "Start" is linked with I 0.5 at the block call. 1. Step: Execution time of instruction (times: Bit logic instructions (Page 26)) InstructionDescriptionTyp. execution time in s AAND0,05 2. Step: Execution times of address access (times: Execution times for address access - indirect addressing (Page 60)) Address areaTyp. execution time in s Addressing via parameters0,04 Total execution time: 0.05 s + 0.04 s = 0.09 s See also Execution Time (Page 59) 9.34Example of I/O Access Example: L PIB 0 (centralized I/O) 1. Step: Time of the loading instructions - direct and indirect addressing (times: Load Instructions (Page 35)) InstructionAddressTyp. execution time in s LB0,09 2. Step: Execution times of address access (times: Execution times for address access to I/O - direct and indirect addressing (PI/PO) (Page 61)) AddressAdditional Runtimes for address access in s Load Byte14,3 Total execution time: 0.09 s + 14.30 s = 14.39 s Instruction list 9.35 Organization Blocks (OB) Instruction list S7-300 CPUs and ET 200 CPUs 66Parameter Manual, 06/2011, A5E02354744-05 9.35Organization Blocks (OB) A user program for an S7-300 consists of blocks which contain the instructions, parameters and data for the respective CPU. The various S7-300 CPUs differ in the number of blocks that you can define for the respective CPU or the blocks provided by the CPU operating system. For a detailed description of the OBs and their applications, refer to the STEP 7 Online Help. Organization blocks 312313314315317319151154Start events (hexadecimal value) Free cycle: 1101HOB1 start eventOB 1xxxxxxxx 1103HRunning OB1 start event (conclusion of the free cycle) Time-of-day interrupts: OB 10xxxxxxxx1111HTimeofday interrupt event Time-delay interrupts: OB 20xxxxxxxx1121HDelay interrupt event OB 21xxxxxxxx1122HDelay interrupt event Cyclic interrupts: OB 32xxxxxxxx1133HCyclic interrupt event OB 33xxxxxxxx1134HCyclic interrupt event OB 34xxxxxxxx1135HCyclic interrupt event OB 35xxxxxx 1)xx1136HCyclic interrupt event Hardware interrupts: OB 40xxxxxxxx1141HHardware interrupt DPV1 interrupts (DP-CPUs only): OB 55-xxxxxxx1155HStatus interrupt OB 56-xxxxxxx1156HUpdate interrupt OB 57-xxxxxxx1157HManufacturer-specific interrupt Synchronous cycle interrupts: OB 61 2)--x 3)xxxx 4)x1164HSynchronous program execution 1) In addition to the setting in milliseconds for the OB 35 call interval, you can also select a setting in microseconds in STEP 7 for OB 35 in order to be able to set the parameters for even the shortest interrupt cycle of 500 s and multiples thereof (the range of values can be set from 500 s to 60000 ms). 2) IM151-8 PN/DP CPU and CPU 314C-2 PN/DP: Synchronous cycle to PROFINET IO (not to PROFIBUS DP) CPU 315, 154, 317 and 319: Synchronous cycle either to PROFIBUS DP or to PROFINET IO (because only one synchronous cycle interrupt OB is available) CPU 313C-2 DP and CPU 314C-2 DP: No synchronous cycle 3) Only applies to CPU 314C-2 PN/DP 4) Does not apply to IM151-7 CPU Instruction list 9.35 Organization Blocks (OB) Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0567 Organization blocks 312313314315317319151154Start events (hexadecimal value) Asynchronous error interrupts: 3501HCycle time exceeded 3502HOB or FB request error 3505HTimeofday interrupt elapsed due to time jump OB 80xxonxxxxx 3507HMultiple OB request error caused start info buffer overflow 3842HModule working properlyOB 82 (Diagnostics interrupt) xxxxxxxx 3942HModule defective 3854HPROFINET IO submodule inserted and matches configured submodule 3855HPROFINET IO submodule inserted but does not match configured submodule 3861HModule inserted 3951HPROFINET IO module removed OB 83--x 5)x 5)x 5)x 5)x 6) 7)x 6) 3961HModule removed 35A1HNo OB or FB 35A3HError when operating system accesses a block 39B1HI/O access error during process image update of the inputs (during each access) 39B2HI/O access error during transfer of the process image to the output modules (during each access) 38B3HI/O access error during process image update of the inputs (outgoing event) 39B3HI/O access error during process image update of the inputs (incoming event) 38B4HI/O access error during transfer of the process image to the output modules (outgoing event) OB 85xxxxxxxx 39B4HI/O access error during transfer of the process image to the output modules (incoming event) 5) For PROFINET IO only 6) For central I/O devices and PROFINET IO 7) On IM151-7 CPU, only applies to central I/O devices Instruction list 9.35 Organization Blocks (OB) Instruction list S7-300 CPUs and ET 200 CPUs 68Parameter Manual, 06/2011, A5E02354744-05 Organization blocks 312313314315317319151154Start events (hexadecimal value) 32C9HPROFIBUS DP: Station activated by SFC 12 (mode 3) 33C9HPROFIBUS DP: Station deactivated by SFC 12 (mode 4) 38C4HDistributed I/O: Station failure, outgoing 39C4HDistributed I/O: Station failure, incoming 32CFHPROFINET IO: Station activated by SFC 12 (mode 3) 33CFHPROFINET IO: Station deactivated by SFC 12 (mode 4) 38CBHPROFINET IO: Station return 39CBHPROFINET IO: Station failure 38F8HPROFINET IO: Partial station return OB 86 8)-xxxxxxx 39F8HPROFINET IO: Partial station failure 35E1HIncorrect message frame ID in GD 35E2HGD package status cannot be entered in DB OB 87xxxxxxx 9)x 35E6HGD total status cannot be entered in DB Restart (warm restart): 1381HManual restart (warm restart) requestOB 100xxxxxxxx 1382HAutomatic restart (warm restart) request 8) Only applies to CPUs with DP and/or PN interface 9) Does not apply to IM151-8 PN/DP CPU Instruction list 9.35 Organization Blocks (OB) Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0569 Organization blocks 312313314315317319151154Start events (hexadecimal value) Synchronous error interrupts: 2521HBCD conversion error 2522HArea length error when reading 2523HArea length error when writing 2524HRange error when reading 2525HRange error when writing 2526HTimer number error 2527HCounter number error 2528HAlignment error when reading 2529HAlignment error when writing 2530HWrite error during access to DB 2531HWrite error during access to DI 2532HBlock number error when opening a DB 2533HBlock number error when opening a DI2534HBlock number error when calling an FC 2535HBlock number error when calling an FB253AHDB not loaded 253CHFC not loaded OB 121xxxxxxxx 253EHFB not loaded 2944HI/O access error at nth read access (n > 1) OB 122xxxxxxxx 2945HI/O access error at nth write access (n > 1) Instruction list 9.36 Function Blocks (FBs) Instruction list S7-300 CPUs and ET 200 CPUs 70Parameter Manual, 06/2011, A5E02354744-05 9.36Function Blocks (FBs) The following table lists the quantity, number and maximum size of the function blocks that you can define in the individual CPUs of the S7-300. Function blocks 312312C313314315317319151154 Quantity1024204840961024 Permitted number0 to 79990 to 7999 Maximum size of an FB (processrelevant code) 32 KB64 KB64 KB 9.37Functions (FC) The following table lists the quantity, number and maximum size of the functions that you can define in the individual CPUs of the S7-300. Functions 312312C313314315317319151154 Quantity1024204840961024 Permitted number0 to 79990 to 7999 Maximum size of an FC (processrelevant code) 32 KB64 KB64 KB 9.38Data blocks (DB) The following table lists the quantity, number and maximum size of the data blocks that you can define in the individual CPUs of the S7-300. Data blocks 312312C313314315317319151154 Quantity1024204840961024 Permitted number1 to 160001 to 16000 Maximal size of a DB (data byte quantity) 32 KB64 KB64 KB Instruction list 9.39 System Functions (SFC) Instruction list S7-300 CPUs and ET 200 CPUs Parameter Manual, 06/2011, A5E02354744-0571 9.39System Functions (SFC) The following tables show the system functions provided by the operating system of the S7-300 CPUs, including the execution times on the relevant CPU. Typ. execution time in sSFC no.SFC nameDescription 312313314315317319151154 0SET_CLKSet time of day2121721 1READ_CLKRead time of day7637 2SET_RTMSet operating hours counter 6536 3CTRL_RTMStarts/stops operating hours counter 6526 4READ_RTMRead operating hours counter 8738 5GADR_LGCDetermine logical base address of a module 26181226 6RD_SINFORead start information of the current OB 115311 Trigger hardware interrupt from the user program of the CPU as DP slave to DP master -87 (for DP CPU only) 872687 1)877DP_PRAL Concurrently running jobs to different modules, max. -34 jobs together with SFB 75 jobs Synchronize groups of DP slaves -65 (for DP CPU only) 65542365 2)6511DPSYC_FR Concurrently running jobs, max. -2 jobs Activate or deactivate DP slaves/PN IO devices -64 (for DP CPU only) 64483064 2)6412D_ACT_DP Concurrently running jobs, max. -8 jobs Read slave diagnostics-33 (for DP CPU only) 33231033 2)3313DPNRM_DG Concurrently running jobs, max. -4 jobs 14DPRD_DATRead consistent user data (n byte) -27 (for DP CPU only) 27201527 2)27 15DPWR_DATWrite consistent user data (n byte) -26 (for DP CPU only) 26241526 2)26 1) IM151-8 PN/DP CPU does not support this SFC 2) With inserted DP master module Instruction list 9.39 System Functions (SFC) Instruction list S7-300 CPUs and ET 200 CPUs 72Parameter Manual, 06/2011, A5E02354744-05 Typ. execution time in sSFC no.SFC nameDescription 312313314315317319151154 17ALARM_SQGenerate blockrelated alarms that can be acknowledged 1269967126 18ALARM_SGenerate blockrelated alarms that cannot be acknowledged 12610168126 19ALARM_SCAcknowledgment state of the last ALARM_SQ incoming alarms 2720527 20BLKMOVCopy variables within the working memory 10 + 0.01 per byte7 + 0.01 per byte 2 + 0.003 per byte 10 + 0.01 per byte 21FILLPreset field within the working memory 10 + 0.035 per byte6 + 0.035 per byte 3 + 0.01 per byte 10 + 0.035 per byte 22CREAT_DBGenerate data block in the working memory 86635086 Delete data block9487529423 3)DEL_DB Concurrently running jobs, max. 21 jobs 24TEST_DBTest data block137513 28SET_TINTSet time-of-day interrupt1711517 29CAN_TINTCancel time-of-day interrupt 8428 30ACT_TINTActivate time-of-day Interrupt 105210 31QRY_TINTQuery time-of-day interrupt116211 32SRT_DINTStart time-delay interrupt10710 33CAN_DINTCancel time-delay interrupt10510 34QRY_DINTQuery time-delay interrupt838 3)The SFC 23 deletes data blocks in the RUN operating mode. If a SFC 23 call is present in the loaded project, additional tests are carried out when data bloc