1

Torbjörn Hult

RUAG SpaceMicroprocessors in present and future equipment

2

Products

Spacecraft Management Units

Guidance and Control Computers

Payload processing and control

Radio occultation instruments

3

SMU Technical Concept

SMU core

Processor board

TM/TC/RM/MM board

TC

TM

CPDUcommands

Alarms

EGSE I/F

I/O bus

I/O board

Processor board

TM/TC/RM/MM board

Alarms

TM

TC

I/O board I/O board

I/O bus

I/O board

EGSE I/F

External buses and links

External buses and links

CPDUcommands

HPTM

HPTM

4

Current generation processor boards

Based on TSC695 including:

COCOS ASIC

Ext. interfaces: 2x1553, 2xSpaceWire/UART, 2xPacketWire, Sync, EGSE

Int. interfaces: 1553, OBDH, 4xSpaceWire, 2xPacketWire Sync, Alarms

Based on COLE ASIC including:

1,8V DC/DC converter

Ext. interfaces: 2x1553, 2xSpaceWire, 2xUART, 2xCAN, Sync, EGSE

Int. interfaces: 1553, OBDH, 5xSpaceWire, 2xPacketWire Sync, Alarms

5

3 MIL-STD-1553B

1 to 3 UARTs(pins shared with SpaceWire)

PCI bus

3 Packet Wire Receiver (PWR)

3 Packet Wire Transmitter

(PWT)

3 to 6 SpaceWire(pins shared with UARTs)

CPU Interface

Memory Interface

Interrupt Controller

Watchdog

Alarms

Memory Copy Controller

On Board Time (OBT)

COCOS, CPU Companion and I/O ASIC

6

COLE chip

Integration of:

”LEON” SPARC v. 8

processor

COCOS I/O controller

S P WS P WS P W

C O L E

N o n - v o l a t i l eM e m o r y

( P R O M a n d /o r E E P R O M )

L o w B a n d w i d t hM e m o r y( S R A M )H i g h B a n d w i d t h M e m o r y

( S D R A M o r S R A M )

M e m o r y C o n t r o l l e rS c r u b b e r

E r r o r D e t e c t i o nA n d C o r r e c t i o n

A M B A A H BA M B A

A r b i t e r &D e c o d e r

slav

e

A H B /A P BB r i d g e

mas

ter

L E O N

m a s t e r * 2

AM

BA

AH

B

C A N* 2

* 4S P W

AM

BA

AP

B

D e b u gI n t e r f a c e

I n t e r r u p tC o n t r o l l e r

L S U A R T

T i m e r

* 2

A M B A /P i B u sB r i d g e

mas

ter

P i B u s M a s t e r

PiB

us

E D A C &S c r u b b e r

M e m o r yI / F

C l o c kG e n e r a t o r P L L

1 5 5 3B C / B M

S u p p o r t 1 5 5 3

M e m o r y C o p yC o n t r o l l e r

O B D HC T

O n B o a r dT i m e

P W T

P W R

H S U A R T

G e n e r a l I / O

* 3

A l a r m S i g n a lG e n e r a t o r

W a t c h d o g

L I C E

D a t a C a c h e( 1 6 K b y t e )

I n s t r u c t i o nC a c h e

( 3 2 K b y t e )

M e m o r y M a n a g e m e n t U n i t

I n t e g e r U n i t

F l o a t i n gP o i n t U n i t

S P W* 4

D e b u gS u p p o r t

U n i t

T r a c eB u f f e r * 3

* 3

1 5 5 3B C / B M

1 5 5 3B C / R T / B M

P a r a l l e l I / O

m a s t e r

slav

e

Bu

ffer

Bu

ffer

3 2 b i td a t a 16

bit

data

mas

ter

s l a v e

m a s t e r *8

m a s t e r * 8

AH

B /

AH

B B

ridge

slav

e

Major improvements:

Processing Performance

I/O Speed and Functionality(MMU, enhanced DSU, SpaceWire RMAP)

CAN bus I/O

Cost

7

Next generation computers

>10 years design lifetime

Higher performance, i.e. multi-core CPU needed

Flexible architecture to handle future requirement changes

New standards impose upgrade of IP blocks and software

New interfaces such as sensor buses and wireless

Built-in GPS receiver

Star Tracker processing in the main computer

Time and Space Partitioning support

8

Next generation computer architecture

Processor technology evolves faster than system architecture

Separate application processor from system application chip

• Fast bus slave I/F available as IP

• No need for advanced memory I/F on the CPU

• Backwards compatibility for I/O interfaces to reduce software development effort

Application

specific

support chip

CPUincluding RAM

NVM

Applicationspecificmemory

I/O interfaces:SpaceWire, 1553, CAN,SpaceFibre, WLAN

Host computer(s)

Bus I/F

9

CPU architecture considerations(from 2006 microprocessor RT)

Anything else we can do better in Europe?

Are European

foundries

competitive?

Eurospace Oct 05

1.251

0.7

1995 2000 2005 2010

100.13 µm

0.2

CMOS/SOS1.25 µm

5

Parity protection0.8 µm

SEU hardened F/FParity protection

0.5 µm

TMR Parity protection0.18 µm

1 µm RH CMOS

Europe

ERC32 SCERC32 Chipset

LEON -NG

MA3 - 1750

LEON

RAD750 (US)

PPC603e (US)

RAD6000 (US)

GVSC1750 (US)

0.5 µm RH CMOS

0.25 µm RH CMOS

US

1990 1995 2000 2005 2010

Micro-processor MA3-1750ERC32 Chip

SetERC32 Single

ChipLEON LEON NG

CPU 4 MIIPS 14 MIPS 20 MIPS 100 MIPS 200 MIPS

RAM (chip) 256 Kbit 1 Mbit 4 Mbit 16 Mbit 56 Mbit

Real Time OS Proprietary CommercialQualified

Open SourceQualified

Open SourceQualified

Open Source

Language ADA ADA/C C CJAVAC++

1.251

0.7

1995 2000 2005 2010

100.13 µm

0.2

CMOS/SOS1.25 µm

5

Parity protection0.8 µm

SEU hardened F/FParity protection

0.5 µm

TMR Parity protection0.18 µm

1 µm RH CMOS

Europe

ERC32 SCERC32 Chipset

LEON -NG

MA3 - 1750

LEON

RAD750 (US)

PPC603e (US)

RAD6000 (US)

GVSC1750 (US)

0.5 µm RH CMOS

0.25 µm RH CMOS

US

Japan

Does the SPARC

architecture give

sufficient

performance?

Do we have the resources to participate in the performance race?

New European goal?

Performance by

extrapolation:

What will be the consequences if we do not participate?