RTSX-S and RTSX-SU Reliability Test Vehicles Daniel K. Elftmann Director Product Engineering Richard...

RTSX-S and RTSX-SU Reliability Test Vehicles

Daniel K. ElftmannDirector Product Engineering

Richard KatzHead Grunt Office of Logic Design

Igor KleynerDeputy Grunt Office of Logic Design

September 8th, 2004

Paper #172 2Wednesday, September 8th, 2004MAPLD 2004: RTSX-S and RTSX-SU Reliability Test Vehicles

Background Background

In 2003, some customers reported clusters of failures

Customer failures had some common factors Stressful designs

I/O and/or power supplies exceeding datasheet limits

Failures occur early in device life

Actel investigation indicated isolated programmed antifuses were failing to a higher impedance state

Industry investigation Actel working closely with Industry Tiger Team (ITT) led by The Aerospace Corp.

Participants include Lockheed Martin, Boeing, General Dynamics, Northrop Grumman Space Technology, JPL, NASA

A series of experiments are being conducted to investigate the customer failures

Remainder of presentation describes the two different Test Vehicles being used for the following experiments

Industry Tiger Team Design

NASA Test Design


Industry Tiger Team Design Top Level Block Diagram

1,146 StageSlow RingOscillator

707 BitArrayShift

Register

140 BitI/O

ShiftRegister

A_Monitor

IO_Monitor

delay_out

Reset_n

zoom[1:0]2

zoom_sel_n

Set_n

Freq_outA0

B1

S

S

OEClk_o_sel

ResetSyncD

TOG_n

Clksel[2:0]Clk_ext

ShiftFreq[1:0]

A_Pattern_length[2:0]A_Pattern_type

IO_Pattern_length[2:0]IO_Pattern_type

3

2

3

3

IO_pin[1] IO_pin[139]



1,146 Stage Slow Ring Oscillator

Synchronized Reset input assures clean startup of slow ring oscillator Delta Read & Record must be done via frequency measurement

No mechanism to break ring and measure delay directly Zoom Debug feature

Allows for enhanced isolation of delays during debug only Long oscillator frequency stabilization time of ~15 minutes at startup

0123

A0

B1

S

S

A0

B1

S

S

Delay_out

zoom[0]zoom[1]

zoom_sel_n

ResetSyncD

Q

QSET

CLR

D

R-Cell CLR haspriority over SET

ResetSyncD

Delay_out

Delay Line TPDL

Delay Line TPDH

A0

B1

S

S

Monitor



Slow Oscillator Startup


Independent controls to set Pattern generator toggle rate for internal R-Cells 16 unique patterns possible, with range of toggle rates (more later)

Clock generated via internal 15 stage ring oscillator (~50MHz) Dedicated Startup Synchronization circuitry for IO_clock domain

IO_Monitor indicates pass/fail On-chip self-checking circuitry detects and latches detected errors

Note: not all errors are detectable by self-test

IO_MonitorIO_Pattern_length[2:0] 3

IO_Pattern_type

ShiftFreq[1:0] 2 IO_Shift_enable_n

Reset_nIO_ResetSyncD

50MHzRing

OscillatorD = 0

I/O Reset Block

3

Set_nIO_SetSyncD

StartupSynchronizer

IO_ClockClksel[2:0]

Clk_ext

PatternGenerator

ShiftEnableControl

I/O Weave ShiftRegister

SerialPatternChecker

Monitor Pin Behavior

Startup Test OK Error

Monitor


140 Bit I/O Shift Register



Ring Oscillator

Ring Oscillator instantiated twice 1st drives Array SR, 2nd drives I/O SR Additional delay stage inserted in Array oscillator to keep two oscillators out of sync

Ring Oscillators frequency dependent on Temperature & VCCA voltage Ring Oscillators NOT recommended for flight designs



Shift Enable Control

Independent Shift Enable circuits instantiated in each of the 2 sequential blocks to pace R-Cell toggling

ShiftEnable_n fanout = 16 R-Cell U0 fan out managed

via register replication

Both Array shift register &I/O shift register blocks set by same input configuration pin settings:

If ShiftFreq==00: Every Cycle

If ShiftFreq==01: Every 2nd Cycle

If ShiftFreq==10: Every 3rd Cycle

If ShiftFreq==11: Every 4th Cycle

Asserted active low enable is consistent with SX-A/S R-CELL enable polarity

Clock

ResetSyncD

ShiftEnable_n

ShiftEnable_n

ShiftEnable_n

ShiftEnable_n


QSET

CLR

D QSET

CLR

D QSET

CLR

D QSET

CLR

D QSET

CLR

D QSET

CLR

D

0 1 2

0 1 2 3 4 5 6 7

1

345

0

7

Pattern_Length[2:0]

Pattern_type

ResetSyncD

Serial_PatternQSET

CLR

D

Serial_Feedback

SetSyncD

ShiftEnable_n

E E E E E E E E

Clock

6

PatternType

PatternLength

CodeLength

BitsSwitching

Rate

0 000 1 0 0 1 2 2 100.00%0 001 1 0 0 0 1 0 0 0 1 3 2 66.67%0 010 One hot I/O at a time switching in entire I/O ring #Bits+9 2 N/A0 011 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 5 2 40.00%0 100 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 6 2 33.33%0 101 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 7 2 28.57%0 110 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 8 2 25.00%0 111 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 9 2 22.22%1 000 1 0 1 1 0 1 0 0 2 1 50.00%1 001 1 0 0 1 1 0 1 1 1 0 1 1 0 0 1 0 0 0 3 1 33.33%1 010 Wave of 0's followed by wave of 1's #Bits+9 1 N/A1 011 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 5 1 20.00%1 100 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 6 1 16.67%1 101 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 1 1 7 1 14.29%1 110 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 8 1 12.50%1 111 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 9 1 11.11%

3

QSET

CLR

D QSET

CLR

D

E


Pattern Generator



I/O Weave Shift Register I/O Weave block three modes of operation

Mode 1: I/O Bypass (OE=‘0’ TOG_n=‘X’) Operates as shift register bypassing the I/Os thru 2-1 multiplexers No I/Os toggle and are tri-stated

Last CellUsed Once

First CellUsed Once

Middle Cell#I/Os - 2


IO_Clock

IO_Feedback

I/Os placedsequentially arounddevice in order of

shift register

TOG_n

0

1

S

S

0

1

S

S

0

1

S

S

0

1

S

S

0

1

S

S

0

1

S

S

OE

IO_Serial_Pattern

IO_ResetSyncD

IO_SetSyncD

IO_ShiftEnable_n

Q

QSET

CLR

D

E

0

1

S

S

0

1

S

S

Q

QSET

CLR

D

E Q

QSET

CLR

D

E Q

QSET

CLR

D

E Q

QSET

CLR

D

E

0

1

S

S




Mode 2: I/O Weave (OE=‘1’ TOG_n=‘1’) Operates as shift register toggling I/O pad at pattern generator defined rate Signal takes path thru output buffer to the pad and back into input buffer I/O toggle rate controlled by Pattern Generator

Last CellUsed Once

First CellUsed Once



IO_Clock

IO_Feedback


shift register

TOG_n

0

1

S

S

0

1

S

S

0

1

S

S

0

1

S

S

0

1

S

S

0

1

S

S

OE

IO_Serial_Pattern

IO_ResetSyncD

IO_SetSyncD

IO_ShiftEnable_n

Q

QSET

CLR

D

E

0

1

S

S

0

1

S

S

Q

QSET

CLR

D

E Q

QSET

CLR

D

E Q

QSET

CLR

D

E Q

QSET

CLR

D

E

0

1

S

S




Mode 3: All I/O Toggle (OE=‘1’ TOG_n=‘0’) Simultaneously switches all I/Os from 0 to 1 then 1 to 0 Pattern follows shift register chain enabling pattern checker to detect errors at any point in chain

Register n+1 <= !n Simultaneous 100% I/O Toggle Rate

Last CellUsed Once

First CellUsed Once



IO_Clock

IO_Feedback


shift register

TOG_n

0

1

S

S

0

1

S

S

0

1

S

S

0

1

S

S

0

1

S

S

0

1

S

S

OE

IO_Serial_Pattern

IO_ResetSyncD

IO_SetSyncD

IO_ShiftEnable_n

Q

QSET

CLR

D

E

0

1

S

S

0

1

S

S

Q

QSET

CLR

D

E Q

QSET

CLR

D

E Q

QSET

CLR

D

E Q

QSET

CLR

D

E

0

1

S

S



707 Bit Array Shift Register

Array shift register has independent controls to set Pattern generator toggle rate for internal R-Cells Options for the Pattern Generator identical to I/O Shift Register Pattern Generator Typical setting for Simultaneous Switching Registers (SSR) set at 12.5%

Clock generated via internal 16 stage ring oscillator (~50MHz) Dedicated Startup Synchronization circuitry for A_Clock domain

A_Monitor indicates pass/fail On-chip self-checking circuitry detects and latches detected errors

Note: not all errors are detectable by this self-test

A_MonitorA_Pattern_length[2:0] 3

A_Pattern_type

ShiftFreq[1:0] 2 A_Shift_enable_n

Reset_nA_ResetSyncD

50MHzRing

OscillatorD = 1

Array Reset Block

3

Set_nA_SetSyncD

StartupSynchronizer

A_ClockClksel[2:0]

Clk_ext

PatternGenerator

ShiftEnableControl

Array Shift Register707 R-Cells




Monitor



Aerospace Experiments

83 parts

General Test

Project 4b1Temp = ~40°CVCCA= 2.5V

Project 4b2Temp = ~40°C

VCCA= 2.5V

~500 partsProject 7Temp = ~40°C

VCCA= 2.5V

Colonel Test

600 hrs

RT54SX32S MEC with “old” algo

1000 hrs +

RT54SX32S MEC with “old” algo

RT54SX32S MEC with “new” algo

330 parts

1000 hrs +

83 partsProject 4b2

Temp = 85°CVCCA= 3.0V

Project 4b2Temp = ~40°C

VCCA= 2.5V


NASA Design Top Level Block Diagram

1,236 StageDelay Line

621 BitArrayShift

Register

144 BitI/O

ShiftRegister

A_Monitor

IO_Monitor

delay_out

Reset_n

delay_sel_n[1:0]2

delay_in

Set_n

Array_out

OE

ResetSyncD

TOG_n

CLKAShiftFreq[1:0]

A_Pattern_length[2:0]A_Pattern_type

IO_Pattern_length[2:0]IO_Pattern_type

2

3

3

HCLK

IO_pin[1] IO_pin[143]


NASA Design

Header Bd. Clock & Reset Driver

NASA Office of Logic Design (OLD) designed and built solder in card to Burn-in Board (BIB) to provide clock and reset to 8 Devices Under Test (DUT) Card solders into BIB configuration socket locations Clocks for DUTs in each column can be controlled to run 180° out of phase Clocks can be driven up to 64MHz

Jumper selectable clock dividers available on Header Board HCLK, CLKA, and CLKB frequency independently settable


NASA Design

1,236 Stage Delay Line

0123

Delay_out

delay_sel_n[1]delay_sel_n[0]

Delay_in

ResetSyncD

Q

QSET

CLR

D

R-Cell CLR haspriority over SET

SlidingDecoder

Q

CLR

D

E

HCLKQ

CLR

D

E

Q

CLR

D

E

Q

CLR

D

E

2 8128

1,236 NAND4 gateDelay Line

Monitor

Configuration lines select input to delay line during operation Synchronized Reset input insures clean startup Direct delay delta read & record measurement possible via Delay_in

No free running oscillator & related self-heating thermal effects, therefore no startup stabilization issues

Allows for more accurate delay measurements Zoom feature removed as un-needed, Action Probe circuitry sufficient for debug


NASA Design

144 Bit I/O Shift Register

Changes Utilizes HCLK vs. 15 stage internal ring oscillator

Industry Tiger Team design does NOT utilize the HCLK resource HCLK driven by NASA header board add-on card

Dedicated Reset Synchronization circuitry for HCLK clock domain Increased fan out of Shift Register Enable nets from 16 vs. 29

Exceeds maximum fan out allowed (24) in Designer Software by 20%

Number of I/Os 143 vs. 139 78 configured for 5V CMOS, remainder 5V TTL; Industry Tiger Team design all TTL

IO_MonitorIO_Pattern_length[2:0] 3

IO_Pattern_type

ShiftFreq[1:0] 2 IO_Shift_enable_n

Reset_nIO_ResetSyncD

I/O Reset Block

Set_nIO_SetSyncD

StartupSynchronizer

HCLK

PatternGenerator

ShiftEnableControl

I/O Weave ShiftRegister




Monitor


NASA Design

621 Bit Array Shift Register

Changes Utilizes CLKA vs. 16 stage internal ring oscillator

CLKA driven by NASA header board add-on card

Increased fan out of Shift Register Enable nets from 16 vs. 29 Exceeds maximum fan out allowed (24) in Designer Software by 20%

Shift register R-Cells manually placed to improve utilization of Long Vertical Tracks (LVT) and Long Horizontal Tracks (LHT)

Array_out added to increase observability at tester Number of bits 621 vs. 707

A_MonitorA_Pattern_length[2:0] 3

A_Pattern_type

ShiftFreq[1:0] 2 A_Shift_enable_n

Reset_nA_ResetSyncD

Array Reset Block

Set_nA_SetSyncD

StartupSynchronizer

CLKA

PatternGenerator

ShiftEnableControl

Array Shift Register621 R-Cells


Monitor

Array_out


NASA Design

Final Design Summary

UtilizationPost-Combiner device utilization:

SEQUENTIAL Used: 1080 Total: 1080 (100.00%) COMB Used: 1800 Total: 1800 (100.00%) LOGIC Used: 2880 Total: 2880 (100.00%) (seq+comb) IO w/ Clocks Used: 168 Total: 170 (78 CMOS) (89 TTL) CLOCK Used: 2 Total: 2 HCLOCK Used: 1 Total: 1

Fan out 23 nets have fan out of 29 1 net with fan out of 28

Timing Analysis Maximum frequency (@ 125C, VCCA = 2.25V, VCCI = 4.5V, Speed –1)

Array Clk => 72MHz IO Clk => 71MHz

Hold time analysis (@ -55C, VCCA = 2.75V, VCCI = 5.5V, Speed –1) Shortest path slack => 0.51ns

NASA design bounds user applications better than Industry Tiger Team design


NASA Experiments

Project KH1Temp = 125°CVCCA= 2.75V

300 parts

HOT

250 hrs

RT54SX32S MEC

“Modified New Algo”

300 parts

Increasing VCCA/VCCI Voltage

Increasing SSOIncreasing SSUIncreased time

Project KC1Temp = -55°CVCCA= 2.75V

300 parts

COLD

250 hrs

RT54SX32S MEC

“Modified New Algo”

300 parts

RTSX32SU UMC

Increasing VCCA/VCCI Voltage Increasing SSOIncreasing SSUIncreased time

RTSX32SU UMC

Parts to be tested in 500 hour stepsStress levels increased for each step.

Voltage, # SSOs, amount of SSU, timeInternal circuit loading fixed at 120% of max load

Each step is 250 hours of HTOL followed by 250 hours of LTOL

Test Protocol


Appendix: RTSXS-U Test Data


ITT Design

Actel RTSX-SU (UMC) Data set

This data set includes the following for RTSXS-U: 2 sets of experiments were completed (P7, P4B2) RTOL = Room Temperature Operating Life TC = Temperature Cycle (-65°C to 150°C)

Product Number of units Failures Unit hours Type Expt

RTSX32S-U 366 0 104288 RTOL P7

RTSX72S-U 100 0 16800 RTOL P7

RTSX32S-U 198 0 33264 RTOL P4B2*Total 466 154352

RTSX32S-U 68 0 6800 TC NA

RTSX72S-U 68 0 6800 TC NA

Total 136 13600

* These 198 Units completed 168 hours of P7 before being put into the P4B2 configuration

Industry Tiger Team Design - Summary


ITT Design

P7 Data Configuration Details:

No I/O’s toggle, Array toggle rate = I/O toggle rate = 12.5% 3 monitor pins toggling - Visual readout using LED

Undershoot less than -0.4V

Product Number of units Failures #of hours Unit hours TypeRTSX32S-U 100 0 596 59600 RTOL

RTSX32S-U 266 0 168 44688 RTOL

RTSX72S-U 100 0 168 16800 RTOLTotal 466 121088

Industry Tiger Team Design - P7


ITT Design

P4B2 Data Configuration Details:

I/O toggle rate = 50% (70 I/Os), Array toggle rate = 12.5% ~2V undershoot

Product Number of units Failures #of hours Unit hours TypeRTSX32S-U 198* 0 168 33264 RTOL

Total 198 33264* These 198 Units completed 168 hours of P7 before being put into the P4B2 configuration

Industry Tiger Team Design - P4B2


NASA/Actel Team

NASA Igor Kleyner Rich Katz

Actel Manish Babladi Marco Cheung Paul Louris Minal Sawant Dan Elftmann

RTSX-S and RTSX-SU Reliability Test Vehicles Daniel K. Elftmann Director Product Engineering Richard...

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