Robert W. Brodersen EECS140 Analog Circuit...
Transcript of Robert W. Brodersen EECS140 Analog Circuit...
ROBERT W. BRODERSEN LECTURE 1
EECS140 ANALOG CIRCUIT DESIGN INTRODUCTION
University of CaliforniaBerkeley
College of EngineeringDepartment of Electrical Engineering
and Computer Science
Robert W. BrodersenEECS140
Analog Circuit Design
ROBERT W. BRODERSEN LECTURE 1
EECS140 ANALOG CIRCUIT DESIGN INTRODUCTION
EECS 140ANALOG INTEGRATED CIRCUITS
Robert W. Brodersen, 2-1779, 402 Cory Hall, [email protected]
This course will focus on the design of MOS analog integrated circuits with extensive use of Spice for the simulations. In addition, some applications of analog integrated circuits will be covered which will include RF amplification and dis-crete and continuous time filtering. Though the focus will be on MOS implementations, comparison with bipolar circuits will be given.
Required Text Analysis and Design of Analog Integrated Circuits, 4th Edition, P.R. Gray, P. Hurst, S. Lewis and R.G. Meyer, John Wiley and Sons, 2001
Supplemental TextsB. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.Thomas Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press, 1998
The SPICE Book, Andre Vladimirescu, John Wiley and Sons, 1994
Prerequisites EECS 105: Microelectronic Devices and Circuits
I-1
ROBERT W. BRODERSEN LECTURE 1
EECS140 ANALOG CIRCUIT DESIGN INTRODUCTION
IC Design Course Structure at Berkeley
EE40
EE105
EE141EE142EE140
Linear/Analog DigitalNon-Linear
Linear Design
Sensors, Transducers
InterfaceCircuits
DigitalProcessing
Amplifiers, Filters, A/D & D/A’s
I-2
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 2
University of CaliforniaBerkeley
College of EngineeringDepartment of Electrical Engineering
and Computer Science
Robert W. BrodersenEECS140
Analog Circuit Design
Lectureson
MOS DEVICE MODELS
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 2
Assumed Knowledge
a) KCL, KVL - Kirchoff Laws
b) Voltage, Current Dividers
c) Thevenin, Norton Equivalents
d) 2-Port Equivalents
e) Phasors, Frequency Response
M-1
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 2
+- aν ν in⋅ν in +-Vs
Rs+
-Rin RL
Rout+
-
νout
i in iout
2-Port Equivalent Circuit
+- aν1 ν in1⋅νin1 +-Vs
+
-Rin1 Rin2
Rout1+
-
νout1
i in
Rinνin
iin
-----iout 0→
RL ∞→
=
Routνout
iout
-------RS ν in 0= =
=
Aν
νout
νin
-------RL ∞→
=
aν2 ν in2⋅+-
Rout2+
-
νout
iout
+
-
νin2
νout aν2 νin2⋅ aν2 νout1⋅ aν2 aν1 ν in1Rin2
Rout1 Rin2+------------------------
⋅ ⋅ ⋅= = =
(Voltage in - Voltage out)M-2
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 2
VDS
IDS
VDSAT
Linear
Saturation
Cutoff
n-channelD
G B
S
VGS
NMOS
IDS
n n
L
G
S D
p
B
MOS Large Signal EquationsM-3
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 2
MOS Large Signal Equations (Cont.)
VGS VT<
VGS VT>
VDS VDSAT< VGS VT–=
Cutoff :
Linear :
IDS k' WL----- VGS VT–
VDS
2-------–
VDS⋅⋅ ⋅=
Saturated :VGS VT>
VDS VDSAT> VGS VT–=
IDSk'2--- W
L----- VGS VT–( )2 1 λ VDS⋅+( )⋅ ⋅=
M-4
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 2
MOS Large Signal Equations (Cont.)
VT VTo γ 2 φ f⋅ VSB+( )12---
2 φf⋅( )12---
–[ ]⋅+=
VTo Threshold Voltage @ VSB≡ 0=
VSB 0>( )
φ f Fermi Potential 0.3≈≡
γ Body Effect Factor≡
λ Short Channel Effect≡
W Width of Device≡L Length≡
k' µ Cox⋅=
Oxide Capacitancemobility
E = VDS/L
E
µ
νε
M-5
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 2
MOS Large Signal Equations (Cont.)
VTo γ VSB
12---
⋅+VT
VTo
VBS
0
γ 1Cox
------ 2 q ε NA⋅ ⋅ ⋅⋅=
n n
G
S D
Body Effect :
+ + + + + + + +
M-6
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 2
MOS Large Signal Equations (Cont.)
Short Channel Effect (λ):
Ldrawn
S G D
XJ = Junction Depth
LD = Lateral Diffusion ~ 0.75 XJ
XD
L Ldrawn 2 LD⋅–=
LEFF L XD–=
XD f VDS( )=
M-7
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 3
MOS Large Signal Equations (Cont.)
IDA( ) k'
2--- W
LEFF
-------- VGS VT–( )2⋅ ⋅=
IDB( ) k'
2--- W
L----- VGS VT–( )2 1 λ VDS⋅+( )⋅ ⋅ ⋅=
VDS∂∂ID
B( )
λ IDS⋅=
Modeled as
VDS∂∂ID
A( ) k'2---– W
LEFF2
-------- VGS VT–( )2
VDSddLEFF⋅ ⋅ ⋅=
VDS∂∂ID
A( ) ID
LEFF
--------VDSd
dXD⋅ λ ID⋅= =
M-8
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 3
λ 1LEFF
--------VDSd
dXD
1
L---
VDSddXD
⋅≈⋅=
MOS Large Signal Equations (Cont.)
Weak function of VDS
XD2 ε VDS VDSAT–( )⋅ ⋅
q NA⋅-------------------------------------------
12---
≈
NA Substrate doping=
Fixed ε→ Dielectric constant of silicon=
VDSddXD 1
2--- 2 ε⋅
q NA⋅-------------
12--- 1
VDS VDSAT–------------------------
12---
⋅ ⋅=
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 3
VDS
IDS
Longer Channel(Increasing L)
λIDS
Ideal
MOS Large Signal Equations (Cont.)
L
W
G
DS
W/L is the parameter of interest
CG W L COX⋅ ⋅∝
M-9
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 3
MOS Small Signal Model (Low Frequency)
IDS
VGS
VSB
DG
S B
+
+
-
-
gmνgs
gmbsνbs
ro
IDS VGSddIDS νgs VBSd
dIDS νbs VDSddIDS νds⋅+⋅+⋅=
gm gmbs 1/ro
M-10M-11
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 3
MOS Small Signal Model (Cont.)
In Saturation :
gm VGSddIDS k' W
L----- VGS VT–( ) 1 λ VDS⋅+( )⋅ ⋅ ⋅= =
gm k' WL----- VGS VT–( )⋅ ⋅≈ k' W
L----- VDSAT⋅ ⋅ 2 k' W
L----- IDS⋅ ⋅ ⋅
12---
= =
IDSk'2--- W
L----- VGS VT–( )2⋅ ⋅ k'
2--- W
L----- VDSAT
2 and from above,⋅ ⋅= =
+
-VGS VT VDSAT+=
What is VDSAT ?
VDSAT2 IDS⋅
k' W L⁄⋅--------------------
12---
=
gm k' WL----- VDSAT so,⋅ ⋅=
G
S
M-12
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 3
MOS Small Signal Model (Cont.)
gmbs gmb VBSddIDS k– ' W
L----- VGS VT–( ) 1 λ VDS⋅+( )
VBSddVT⋅ ⋅ ⋅ ⋅= = =
gm
gmbs k' WL----- VGS VT–( ) 1 λ VDS⋅+( )⋅ ⋅ ⋅ χ⋅=
gmbs
gm
------- χ=
VBSddVT γ
2 2 φf VSB+⋅( )0.5⋅----------------------------------------- χ–≡–=
χγ
2 2 φ f VSB+⋅( )0.5⋅-----------------------------------------=
gmbs calculation :
M-13
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 3
MOS Small Signal Model (Cont.)
gmbs
gm
------- χ=
VBS
γ = 0.5φf = 0.3k’ = 90e-6λ = 0.01VTo=0.7
-5V 0V
0.1
0.23
n n
G
S D
Cjs
Cox
χCjs
Cox
------=
Qchannelduetovbs Cjs νbs⋅≈
Qchannelduetovgs Cox νgs⋅≈
M-14
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 3
MOS Small Signal Model (Cont.)
ro calculation :
1ro
--- gmds VDSddIDS
VDSdd k'
2--- W
L----- VGS VT–( )2 1 λ VDS⋅+( )⋅ ⋅ ⋅
= = =
1ro
--- k'2--- W
L----- VGS VT–( )2 λ⋅ ⋅ ⋅=
1ro
--- λ IDS⋅=
r0
1λ IDS⋅-------------=
M-15
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 3
MOS Small Signal Model (Cont.)Comparison with Spice Level 1:
KP k' µ Cox nmos 50 100µ AV2-----–→∼⋅= =
LAMBDA λ 0.01 0.1→∼=
PHI 2 φf 0.6∼⋅=
VTO VTo 0.5 1.0V→∼=
GAMMA γ 0.05 0.5→∼=
pmos 13---nmos≈
M-16
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE
ROBERT W. BRODERSEN LECTURE 4
MOS Small Signal Model (Cont.)Summary:
gm 2 k' WL----- IDS⋅ ⋅ ⋅
12---
≈ k' WL----- VDSAT⋅ ⋅
2 IDS⋅VDSAT
-------------= =
gmbs χ g⋅ m=
χγ
2 2 φ f VSB+⋅( )0.5⋅-----------------------------------------=
VDSAT2 IDS⋅
k' W L⁄⋅--------------------
12---
=
r0
1λ IDS⋅-------------=
IDS
gm
----- VGS VT–2
------------------ VDSAT
2----------= =
VDSAT VGS VT–=
VGS VT2 IDS⋅
k' W L⁄⋅--------------------
12---
+=
IDSk'2--- W
L----- VGS VT–( )2⋅ ⋅=
VT VTo γ 2 φ f⋅ VSB+( )12---
2 φ f⋅( )12---
–[ ]⋅+=
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE
ROBERT W. BRODERSEN LECTURE 4
University of CaliforniaBerkeley
College of EngineeringDepartment of Electrical Engineering
and Computer Science
Robert W. BrodersenEECS140
Analog Circuit Design
Lectureson
SPICE
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE
ROBERT W. BRODERSEN LECTURE 4
SP-1Spice Transistor Model :
M1 1 2 3 4 nch L=1µ W=10µ
AD=( ) AS=( ) PD=( ) PS=( ) NRD=( )
L
W
G
DS
area of drain
parasitic resistors
1
2
3
4
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE
ROBERT W. BRODERSEN LECTURE 4
SP-2
Initial Operationg PointDC currents and Voltages
LinearizeAround OP Point
Solve Eqn. DC Converge?
Increment Time
End of Time Interval
No
Yes
No
SPICE
New OperatingPoint
Yes STOP
Analysis Types :DC op point .opDC sweepsAC & Transient
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE
ROBERT W. BRODERSEN LECTURE 4
SP-3
+-
+ -
12
3
4
I4
I1 R1 R2 R3
R4
VB
VA
Gi = 1/Ri
G1 G4+( ) V1⋅ G1 V2⋅–
G4 V4 I4+⋅–G4 V1⋅–
I4–
G4– V4⋅ I1+Node 1 :G1 V1⋅– G1 G2 G3+ +( )+ V2 G3 V3⋅–⋅
G3 V2⋅– G3 V3⋅+
=
Node 2 :Node 3 :Node 4 :
VAV4–V3–
V1 =
=
=
=
= 0
0
0
0
VB
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE
ROBERT W. BRODERSEN LECTURE 4
G1+G4 -G1 0 -G4 1 0 V1 0 -G1 G1+G2+G3 -G3 0 0 0 V2 0 0 -G3 -G3 0 0 -1 V3 0 -G4 0 0 -G4 0 1 V4 0 1 0 0 0 0 0 I1 VB 0 0 -1 1 0 0 I4 VA
G F V C
B R I E
=
=Total # of EQNS N=n + nv + nl n = # of circuit nodesnv= # of independent voltage srcsnl= # of inductors
Current src
Votlage src
SP-4
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE
ROBERT W. BRODERSEN LECTURE 4
SP-5
a110( ) a12
0( ) a130( )
a210( ) a22
0( ) a230( )
a310( ) a32
0( ) a330( )
x1
x2
x3
b10( )
b20( )
b30( )
=
A x b=
e10( )
e20( )
e30( )
e31( ) e3
0( ) a310( )
a110( )
------ e10( )⋅–=e2
1( ) e20( ) a21
0( )
a110( )
------ e10( )⋅–=e1
1( ) e10( )=
Matrix Solution
we needSolve by Gaussian Elimination
(0) denotes iteration step
Eliminate a21,a31x x x0 x x0 x x
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE
ROBERT W. BRODERSEN LECTURE 4
Then eliminate a32(1)
e22( ) e2
1( )=e1
2( ) e11( )=
e32( ) e3
1( ) a321( )
a221( )
------ e21( )⋅–=
x x x0 x x0 0 x
Upper triangular matrixcan be solved
a112( ) a12
2( ) a132( )
0 a222( ) a23
2( )
0 0 a332( )
x1
x2
x3
b10( )
b21( )
b32( )
=
x3
b32( )
a332( )
------=
x2
b21( ) a23
1( ) x3⋅–( )a22
1( )---------------------------------=
x1
b10( ) a13
0( ) x3 a120( ) x2⋅–⋅–( )
a110( )
------------------------------------------------------=
Solution
SP-6
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE
ROBERT W. BRODERSEN LECTURE 4
SP-7Accuracy
Can’t divide by 0 or small numbers, so pivoting is usedto reorder eqn’s (Basically renumbering nodes). Puts maximum values on diagonal.
R1=1Ω
R2=10kΩ1A
1 1–1– 1.0001
V1
V2
10
=
11--- 1
10k---------– G1 G 2+=
If the computer only has 4digits of precision then we get,
1 1–1– 1
V1
V2
10
= V– 1 V2+ 0=V1 V2, ∞=
V1 10 001V,=
V1 V2– 1=
V2 10 000V,=
Actually,
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE
ROBERT W. BRODERSEN LECTURE 4
To control accuracy
.options PIVTOL = <values> (1018)
This sets the allowable range of conductance values.
*ERROR* : Maximum entry ......atSTEP ....... is less than PIVTOL
-Probably means you have an incorrect elementor floating node
SP-8
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE
ROBERT W. BRODERSEN LECTURE 4
SP-9Solution of the DC equations with non-linear models
ID IS eVD
VTH---------
1– ⋅=
IG G V⋅=
IG ID
VDIA G
+
-
Need to findthis point
ID,G
IG
ID
IA
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE
ROBERT W. BRODERSEN LECTURE 4
SP-10Newton-Raphson Iteration :
- Make guess of next operation point in iteration
Start at initial guess and linearize diode eqn.
ID0VD(0)
IA G GD0
+
-
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE
ROBERT W. BRODERSEN LECTURE 4
ID
Current value
Slope of GD0
Solution finds this point
VD
ID0
Solve for VD,
becomes VD(1) Linearize at this point
Find new point
SP-11
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON SPICE
ROBERT W. BRODERSEN LECTURE 4
SP-12Convergence
Keep iterating until all voltages and currents are within aa tolerance value. Vn
i( ) node voltage n at iteration i=
The convergence check is :
εVn REL V( ) max Vni 1+( ) Vn
i( ),( ) ABS V( )+⋅=
Vni 1+( ) Vn
i( )– εVn≤
REL V( ) 10 4– (Default 10 3– )∼
ABS V( ) 10 6– (Default 50µV )∼
ABS(V) should be at least two orders of magnitude belowrequired accuracy.These values would give 1 part in 104 accuracy down to100µV resolution
EECS140 ANALOG CIRCUIT DESIGN LECTURES ON MOS DEVICE MODELS
ROBERT W. BRODERSEN LECTURE 2
SP-13
Current convergence is broken into two types; MOS and NOT MOS
MOS ABSMOS ABSOLUTE 10 6–( )∼RELMOS RELATIVE 0.5( )∼
NOTMOSABSI ABSOLUTE 10 9–( )∼RELI RELATIVE 0.01( )∼
ITL = # of steps in iteration (200)When you get
*ERROR* no convergence in DC analysis and the last node voltagesThen it hasn’t converged in 200 times - something is probably wrong with your netlist