Robert Chau ICSICT Paper 101904
5
Advanced CMOS Transistors in the Nanotechnology Era for High-Performance, Low-Power Logic Applications (Invited Paper) Robert Chau*, Mark Doczy, Brian Doyle, Suman Datta, Gilbert Dewey, Jack Kavalieros, Ben Jin, Matthew Metz, Amlan Majumdar, and Marko Radosavljević Components Research, Logic Technology Development, Intel Corporation 5200 N.E. Elam Young Parkway, Mailstop: RA3-252, Hillsboro, OR 97124, USA *Email: [email protected] Abstract Sustaining Moore’s Law requires continual transistor miniaturization. Through silicon innovations and breakthroughs, CMOS transistor scaling and Moore’s Law will continue at least through early next decade. By combining silicon innovations with other novel nanotechnologies on the same Si platform, it is expected that Moore’s Law will extend well into the next decade. This paper describes the most recent advances made in silicon CMOS transistor technology and discusses the challenges and opportunities presented by the recent emerging nanoelectronic devices such as carbon nanotube field-effect transistors (FET), Si-nanowire FETs and III-V FETs for high-performance, low-power logic applications. 1. Introduction Moore’s Law states that the number of transistors per integrated circuit doubles every 24 months, and it has been the guiding principle for the semiconductor industry for over 30 years. In order to sustain Moore’s Law, the physical gate length (L g ) of the transistor has been scaled by ~30% every generation, as shown in Fig. 1. The current 90 nm generation technology node produces CMOS devices with L g of ~50 nm. It is projected that the L g of the transistor will reach ~10 nm in 2011 [1]. Through silicon technology innovations and breakthroughs such as metal-gate/high-K stacks [2]-[4], uniaxially strained Si channels [5], [6], biaxially strained Si and SiGe channels [7], [8], and the non-planar fully-depleted Tri-gate CMOS transistor architecture [9], [10], CMOS transistor scaling and Moore’s Law will continue at least through early next decade. Recently, tremendous progress has been made in the research of novel nanoelectronic devices such as carbon nanotube FETs [11], [12], Si-nanowire FETs [13], [14], and III-V compound semiconductor FETs [15], [16]. These novel devices present both challenges and opportunities for future nanoelectronics applications [17]. By combining Si innovations with the novel nanotechnologies onto the same Si platform, it is expected that circuit functionality can be greatly enhanced and Moore’s Law will be extended well into the next decade. 2. Si Breakthrough: High-K/Metal-Gate Stacks for High-Performance Si CMOS For more than 15 years the physical thickness of SiO 2 has been aggressively scaled for high-performance, low-power CMOS applications [2]. Recently SiO 2 with physical thickness of 1.2 nm has been successfully implemented in the 90 nm logic technology node [18]. In addition, SiO 2 with physical thickness of 0.8 nm [see Fig. 2(a)] has been demonstrated in the laboratory [1], [24], and has been integrated into 15 nm L g Si research transistor, whose TEM cross-section is shown in Fig. 2(b) and drain current vs gate voltage (I d -V g ) characteristics shown in Fig. 3. Continual gate oxide scaling, however, will require high-K materials since gate oxide leakage is increasing with decreasing SiO 2 thickness and since SiO 2 is running out of atoms for further scaling. So far, the most common high-K dielectric materials investigated are Hf-based and Zr-based [2], [3]. Technology Node 0.5µm 0.35µm 0.25µm 0.18µm 0.13µm 90nm 65nm 45nm 30nm Transistor Physical Gate Length 130nm 70nm 50nm 30nm 20nm 15nm 1995 2005 1990 2000 2010 1995 2005 1990 2000 2010 0.01 0.1 1.0 Micrometer Nanotechnology 10 100 1000 Nanometer 10 100 1000 Nanometer Transistor Scaling Year Figure 1. Scaling of transistor size (physical gate length L g ) to sustain Moore’s Law.
Transcript of Robert Chau ICSICT Paper 101904
Advanced CMOS Transistors in the Nanotechnology Era for High-Performance, Low-Power Logic Applications
(Invited Paper)
Robert Chau*, Mark Doczy, Brian Doyle, Suman Datta, Gilbert Dewey, Jack Kavalieros, Ben Jin, Matthew Metz, Amlan Majumdar, and Marko Radosavljević
Components Research, Logic Technology Development, Intel Corporation
5200 N.E. Elam Young Parkway, Mailstop: RA3-252, Hillsboro, OR 97124, USA *Email: [email protected]
Abstract Sustaining Moore’s Law requires continual transistor miniaturization. Through silicon innovations and breakthroughs, CMOS transistor scaling and Moore’s Law will continue at least through early next decade. By combining silicon innovations with other novel nanotechnologies on the same Si platform, it is expected that Moore’s Law will extend well into the next decade. This paper describes the most recent advances made in silicon CMOS transistor technology and discusses the challenges and opportunities presented by the recent emerging nanoelectronic devices such as carbon nanotube field-effect transistors (FET), Si-nanowire FETs and III-V FETs for high-performance, low-power logic applications. 1. Introduction Moore’s Law states that the number of transistors per integrated circuit doubles every 24 months, and it has been the guiding principle for the semiconductor industry for over 30 years. In order to sustain Moore’s Law, the physical gate length (Lg) of the transistor has been scaled by ~30% every generation, as shown in Fig. 1. The current 90 nm generation technology node produces CMOS devices with Lg of ~50 nm. It is
projected that the Lg of the transistor will reach ~10 nm in 2011 [1]. Through silicon technology innovations and breakthroughs such as metal-gate/high-K stacks [2]-[4], uniaxially strained Si channels [5], [6], biaxially strained Si and SiGe channels [7], [8], and the non-planar fully-depleted Tri-gate CMOS transistor architecture [9], [10], CMOS transistor scaling and Moore’s Law will continue at least through early next decade. Recently, tremendous progress has been made in the research of novel nanoelectronic devices such as carbon nanotube FETs [11], [12], Si-nanowire FETs [13], [14], and III-V compound semiconductor FETs [15], [16]. These novel devices present both challenges and opportunities for future nanoelectronics applications [17]. By combining Si innovations with the novel nanotechnologies onto the same Si platform, it is expected that circuit functionality can be greatly enhanced and Moore’s Law will be extended well into the next decade. 2. Si Breakthrough: High-K/Metal-Gate Stacks for
High-Performance Si CMOS For more than 15 years the physical thickness of SiO2 has been aggressively scaled for high-performance, low-power CMOS applications [2]. Recently SiO2 with physical thickness of 1.2 nm has been successfully implemented in the 90 nm logic technology node [18]. In addition, SiO2 with physical thickness of 0.8 nm [see Fig. 2(a)] has been demonstrated in the laboratory [1], [24], and has been integrated into 15 nm Lg Si research transistor, whose TEM cross-section is shown in Fig. 2(b) and drain current vs gate voltage (Id-Vg) characteristics shown in Fig. 3. Continual gate oxide scaling, however, will require high-K materials since gate oxide leakage is increasing with decreasing SiO2 thickness and since SiO2 is running out of atoms for further scaling. So far, the most common high-K dielectric materials investigated are Hf-based and Zr-based [2], [3].
TechnologyNode
0.5µm0.35µm
0.25µm0.18µm
0.13µm90nm
65nm45nm
30nm
TransistorPhysical Gate
Length 130nm70nm
50nm
30nm20nm
15nm
1995 20051990 2000 20101995 20051990 2000 20100.01
0.1
1.0
Mic
rom
eter
Nanotechnology
10
100
1000
Nanom
eter
10
100
1000
Nanom
eter
Transistor Scaling
Year
Figure 1. Scaling of transistor size (physical gate length Lg) to sustain Moore’s Law.
There are two fundamental problems in replacing poly-Si/SiO2 with poly-Si/high-K dielectric stack for high-performance CMOS applications. First, high-K dielectrics and poly-Si gates are incompatible due to Fermi level pinning at the poly-Si/high-K interface [2], [3], which causes high threshold voltages in MOSFETs. Fermi level pinning is most likely caused by defect formation at the poly-Si/high-K dielectric interface [3]. Second, poly-Si/high-K transistors exhibit severely degraded channel mobility due to the coupling of low-energy surface optical (SO) phonon modes arising from the polarization of the high-K dielectric to the inversion channel charge carriers [2]-[4], [7]. The above fundamental poly-Si/high-K problems can be solved by replacing the conventional poly-Si gate with metal gate electrodes with “correct” work functions. The use of metal gates is effective in screening the remote phonon-channel charge interaction and improves the transistor channel mobility, as shown in Fig. 4 [4]. To achieve the correct CMOS transistor threshold voltages, a n-type (n+) metal is needed for NMOS while a p-type (p+) metal is needed for PMOS, as shown in Fig. 5. Figure 6 shows the Id-Vg characteristics of the resulting high-K/metal-gate CMOS transistors with Lg = 80 nm,
PolySi
Silicon
Poly Si
Silicon
SiO2
25 nm
Lg = 15 nm
(a) (b)
Figure 2. TEM cross-section of (a) SiO2 gate oxide with physical thickness of only 0.8 nm and (b) 15 nm Lg transistor.
1E-08
1E-07
1E-06
1E-05
1E-04
1E-03
0 0.2 0.4 0.6 0.8
GATE VOLTAGE (V)
DR
AIN
CU
RR
ENT
(A
/µm
) Vd = 0.8 V
Vd = 0.05 V
S.S. = 95 mV/decadeDIBL = 100 mV/VIoff = 180 nA/µm
15 nm NMOS
1E-08
1E-07
1E-06
1E-05
1E-04
1E-03
0 0.2 0.4 0.6 0.8
GATE VOLTAGE (V)
DR
AIN
CU
RR
ENT
(A
/µm
) Vd = 0.8 V
Vd = 0.05 V
S.S. = 95 mV/decadeDIBL = 100 mV/VIoff = 180 nA/µm
15 nm NMOS
Figure 3. Id-Vg characteristics of Si NMOS transistor with physical gate length Lg of 15 nm and physical SiO2 of 0.8 nm.
0
200
400
600
800
1000
1200
0 0.5 1 1.5
TRANSVERSE ELECTRIC FIELD Eeff (MV/cm)
SUR
FAC
E P
HO
NO
N L
IMIT
ED M
OB
ILIT
Y(c
m2 /V
s)
471
P860
W019-BKM
T = 25 °CPoly-Si/High-K
Metal/High-K
Poly-Si/SiO2
0
200
400
600
800
1000
1200
0 0.5 1 1.5
TRANSVERSE ELECTRIC FIELD Eeff (MV/cm)
SUR
FAC
E P
HO
NO
N L
IMIT
ED M
OB
ILIT
Y(c
m2 /V
s)
471
P860
W019-BKM
T = 25 °CPoly-Si/High-K
Metal/High-K
Poly-Si/SiO2
Figure 4. The use of metal gates is effective in screening the remote phonon-channel charge interaction and improves the transistor channel mobility [4].
NDK
SDK
-1.1-1.0
-0.8
-0.6
-0.4
-0.2
0.00.1
N+p
oly
P+po
ly
P-m
etal
N-m
etal
Met
al A
Met
al B
Met
al C
Met
al D
Met
al E
Met
al F
Met
al G
Met
al H
Met
al I
Met
al J
Gate Electrode Materials
Tran
sist
or F
latb
and
Volta
ge (V
)
P-type Metal on High-K
N-type Metal on High-K
N+ PolySi/SiO2
P+ PolySi/SiO2
Mid-gap Metal on High-K
NDK
SDK
-1.1-1.0
-0.8
-0.6
-0.4
-0.2
0.00.1
N+p
oly
P+po
ly
P-m
etal
N-m
etal
Met
al A
Met
al B
Met
al C
Met
al D
Met
al E
Met
al F
Met
al G
Met
al H
Met
al I
Met
al J
Gate Electrode Materials
Tran
sist
or F
latb
and
Volta
ge (V
)
P-type Metal on High-K
N-type Metal on High-K
N+ PolySi/SiO2
P+ PolySi/SiO2
Mid-gap Metal on High-K
Figure 5. N-type (n+) metal gate electrode on high-K for NMOS and p-type (p+) metal gate electrode on high-K for PMOS have been engineered. Metal electrodes with the right work functions are necessary for CMOS transistors to achieve correct threshold voltages.
1E-09
1E-08
1E-07
1E-06
1E-05
1E-04
1E-03
1E-02
-1.4 -1 -0.6 -0.2 0.2 0.6 1 1.4
GATE VOLTAGE (V)
DR
AIN
CU
RR
ENT
(A/µ
m)
NMOSPMOS
Lg = 80 nmToxe = 14.5 Å
|Vds| = 0.05, 1.3 V
1E-09
1E-08
1E-07
1E-06
1E-05
1E-04
1E-03
1E-02
-1.4 -1 -0.6 -0.2 0.2 0.6 1 1.4
GATE VOLTAGE (V)
DR
AIN
CU
RR
ENT
(A/µ
m)
NMOSPMOS
Lg = 80 nmToxe = 14.5 Å
|Vds| = 0.05, 1.3 V
Figure 6. Id-Vg characteristics of the high-K/metal-gate CMOS transistors with Lg = 80 nm, EOT = 1.0 nm, “correct” threshold voltages, and negligible gate oxide leakage [4].
equivalent oxide thickness (EOT) of 1.0 nm, electrical oxide thickness of 1.45 nm at inversion, and negligible gate oxide leakage. The NMOS transistor achieves record-setting Ion = 1.66 mA/µm with Ioff = 37 nA/µm, while the PMOS transistor achieves record-setting Ion = 0.71 mA/µm with Ioff = 45 nA/µm at Vd = 1.3 V [4]. 3. Si Innovations: Uniaxial and Biaxial Strains to
enhance Si CMOS Transistor Performance Strain improves transistor performance by enhancing the channel mobility through reduced electron effective mass and intervalley scattering rate for NMOS, and reduced hole effective mass and interband scattering rate for PMOS [6]. There are two types of strain: uniaxial and biaxial strain. In the case of uniaxial strain, epi-SiGe is used to form the transistor source/drain regions to induce uniaxial compressive strain in the channel of the PMOS transistor [5], [6] as shown in Fig. 7(a), while a high tensile-stress silicon nitride cap is used to induce uniaxial tensile strain in the channel of the NMOS transistor [5], [6] as shown in Fig. 7(b). Uniaxial strain has been successfully implemented in production CMOS transistors in the 90 nm technology node [5]. In the case of biaxial strain, a layer of biaxially tensile-strained Si is formed on top of a relaxed SiGe
substrate for both NMOS [7] and PMOS [19], [20], as shown in Fig. 8. Figure 9 shows the channel mobility of the biaxially tensile-strained NMOS transistor increases with increasing Ge% in the SiGe layer. However, the use of biaxially tensile-strained Si is not as effective as the uniaxially compressive-strained Si in enhancing the
SiGe
PMOS
SiGe
(a)
SiGe
PMOS
SiGe
(a)
NMOS
High Stress Film(b)
NMOS
High Stress Film(b)
Figure 7. (a) A strained epitaxial SiGe film in the S/D region to induce compressive strain in the PMOS channel region [5], [6]. (b) NMOS device capped with a high tensile stress silicon nitride layer to induce tensile channel strain in NMOS [5], [6].
Relaxed SiGe(virtual substrate)
Strained Si
SiGe
Si
Bulk Si substrate
Graded SixGe1-x
Relaxed SiGeSi
Relaxed SiGe(virtual substrate)
Strained Si
SiGe
Si
Relaxed SiGe(virtual substrate)
Strained Si
SiGe
Si
Bulk Si substrate
Graded SixGe1-x
Relaxed SiGeSi
Bulk Si substrate
Graded SixGe1-x
Relaxed SiGeSi
Figure 8. Biaxially tensile-strained silicon on relaxed SiGe substrate for NMOS application.
0
100
200
300
400
500
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Eeff (MV/cm)
ELEC
TRO
N M
OB
ILIT
Y (c
m2 /V
s)
Universal Mobility Curve
High-K / MG on 15% Ge substrate
High-K / MG on 10% Ge substrate
High-K / MG on unstrained Si
0
100
200
300
400
500
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Eeff (MV/cm)
ELEC
TRO
N M
OB
ILIT
Y (c
m2 /V
s)
Universal Mobility Curve
High-K / MG on 15% Ge substrate
High-K / MG on 10% Ge substrate
High-K / MG on unstrained Si
Figure 9. Channel mobility of biaxially tensile-strained NMOS transistor increases with increasing Ge% in the SiGe layer. The transistors have high-K/metal gate stacks.
Si
Strained SiGe
Si
SiGe
Strained SiGechannel
Si
Metal-gate/High-Kgate stack
Si
Strained SiGe
Si
SiGe
Strained SiGechannel
Si
Metal-gate/High-Kgate stack
Figure 10. Biaxially compressive-strained SiGe layer formed on top of a Si substrate upon which surface-channel PMOS transistors can be made.
0
20
40
60
80
100
120
140
-1.4-1.2-1.0-0.8-0.6-0.4-0.20.0Eeff (MV/cm)
Hol
e M
obili
ty (c
m2 V-1
s- 1)
HfO2/TiN on SiGe (25% Ge)
HfO2/TiN on SiGe (20% Ge)
HfO2/TiN on SiGe (30% Ge)
HfO2/TiN on SiSiO2 Universal Mobility Curve
0
20
40
60
80
100
120
140
-1.4-1.2-1.0-0.8-0.6-0.4-0.20.0Eeff (MV/cm)
HO
LE M
OB
ILIT
Y (c
m2 /V
s)
High-K/MG on SiGe (25% Ge)High-K/MG on SiGe (20% Ge)
High-K/MG on SiGe (30% Ge)
High-K/MG on Si
SiO2 Universal Mobility Curve
0
20
40
60
80
100
120
140
-1.4-1.2-1.0-0.8-0.6-0.4-0.20.0Eeff (MV/cm)
Hol
e M
obili
ty (c
m2 V-1
s- 1)
HfO2/TiN on SiGe (25% Ge)
HfO2/TiN on SiGe (20% Ge)
HfO2/TiN on SiGe (30% Ge)
HfO2/TiN on SiSiO2 Universal Mobility Curve
0
20
40
60
80
100
120
140
-1.4-1.2-1.0-0.8-0.6-0.4-0.20.0Eeff (MV/cm)
HO
LE M
OB
ILIT
Y (c
m2 /V
s)
High-K/MG on SiGe (25% Ge)High-K/MG on SiGe (20% Ge)
High-K/MG on SiGe (30% Ge)
High-K/MG on Si
SiO2 Universal Mobility Curve
Figure 11. PMOS mobility gain induced by the biaxially compressive strain in SiGe increases with increasing Ge% in the SiGe layer. This mobility gain does not reduce at high transverse channel electric fields like in the case of the biaxially tensile strain in Si.
PMOS mobility because the mobility gain induced by the former reduces at high transverse channel electric fields [5], [6], [19], [20]. There is, however, another way of applying biaxial strain to the PMOS and not having the problem of losing the mobility gain at high transverse channel electric fields [8]. Figure 10 shows a biaxially compressive-strained SiGe layer formed on top of a Si substrate, upon which surface-channel PMOS transistors can be made [8]. Figure 11 shows the PMOS mobility gain induced by the biaxial compressive strain in SiGe increases with increasing Ge% in the SiGe layer, and that this mobility gain does not reduce at high transverse channel electric fields as in the case of the biaxial tensile strain in Si [8]. 4. Transistor Architecture Innovation: Non-planar
Tri-gate CMOS to Improve Device Electrostatics As the Lg of the transistor scales, its electrostatics and short channel performance become harder to control, and the transistor Ioff increases [1], [21]. Several promising device architectures have been proposed to improve the electrostatics and Ioff of the transistor in upcoming logic
generations, including the planar depleted-substrate transistor (DST) [22], the non-planar double-gate FINFET [23], and the non-planar Tri-gate transistor [9], [10], as shown in Fig. 12. All three devices utilize a fully-depleted body and can be used to improve short-channel performance. Of the three device architectures shown in Fig. 12, the Tri-gate transistor has the least stringent silicon body thickness (Tsi) and width (Wsi) requirement, as illustrated in Fig. 13. Hence, Tri-gate is the easiest to fabricate and is the most manufacturable [9], [10]. Figure 14 shows a top-down SEM image a Tri-gate transistor with multiple legs. Figure 15 compares the subthreshold slope of Tri-gate transistors versus conventional planar Si transistors with respect to Lg scaling. The data shows that non-planar Tri-gate transistors have much improved electrostatics over the conventional planar Si transistors. 5. Emerging Novel Nanoelectronic Devices for
Possible Future Logic Applications Recently, there has been rapid progress in the research of novel nanoelectronic devices such as carbon nanotube (CNT) FETs [11], [12], Si-nanowire FETs [13], [14], and
TSi
LG
WSi
TSiLG
(a)
(c)
TSi
(b)
LG
WSi
TSi
LG
WSi
TSiLG
(a)
(c)
TSi
(b)
LG
WSi
Figure 12. (a) planar single-gate DST, (b) non-planar double-gate FINFET, and (c) non-planar Tri-gate transistor.
0 20 40 60 80
Device Gate Length Lg (nm)
Silic
on B
ody
Thi
ckne
ss (
nm)
Tri-Gate(TSi, WSi)
0
10
20
30
40
50
60
3X
1.5X
Double-Gate(WSi)
Single-Gate(TSi)
0 20 40 60 80
Device Gate Length Lg (nm)
Silic
on B
ody
Thi
ckne
ss (
nm)
Tri-Gate(TSi, WSi)
0
10
20
30
40
50
60
3X
1.5X
Double-Gate(WSi)
Single-Gate(TSi)
Figure 13. Simulation results showing the silicon geometry requirements for planar single-gate DST, double-gate FINFET, and Tri-gate devices. Tri-gate requirements are the most relaxed allowing for improved manufacturability.
Gate
Source Drain
Gate
Source Drain
Figure 14. Top-down SEM image of a Tri-gate transistor with multiple Si legs.
Figure 15. Subthreshold slope versus transistor physical gate length. The non-planar Tri-gate shows significant improvement over the conventional planar Si MOSFETs.
III-V FETs (the transistor channel is made of an III-V compound semiconductor material) [15], [16]. To gauge the promise of these emerging devices, we have benchmarked them against state-of-the-art Si CMOS [17]. Figure 16 compares the PMOS intrinsic gate delay (CV/I) of CNTFETs, Si-nanowire FETs, and planar and non-planar Si MOSFETs. The CNTFETs show significant PMOS CV/I improvement, and at least 20x improvement in effective PMOS channel mobility over Si MOSFETs and Si nanowires. Figure 17 compares the NMOS intrinsic gate delay of CNTFETs, III-V FETs, and planar and non-planar Si MOSFETs. The data shows that the III-V FETs exhibit significant improvement in NMOS intrinsic gate delay over the Si MOSFETs. The improvement shown by the III-V FETs is due to its 50x improvement in effective NMOS channel mobility and its much lower operating supply voltage (Vcc = 0.5 V) compared to the Si MOSFETs [17]. While the scalability of these novel devices is unknown and many fundamental challenges exist, these devices do offer tremendous opportunities for future nanoelectronic applications.
6. Summary This paper summarizes the most recent Si breakthroughs and innovations made for advanced CMOS transistors in the nanotechnology era. Through Si breakthroughs and innovations, CMOS transistor scaling and Moore’s Law will continue at least through early next decade. By combining Si innovations with the other novel nanotechnologies onto the same Si platform, it is expected that Moore’s Law will be extended well into the next decade. References [1] R. Chau, et al., in Proceedings of Device Research
Conference, p. 123, June 2003. [2] R. Chau, et al., in Extended Abstract of
International Workshop on Gate Insulator, p. 124, 2003.
[3] R. Chau, et al., in Proceedings of AVS 5th International Conference on Microelectronics and Interfaces, p. 3, 2004.
[4] R. Chau, et al., IEEE Electron Device Letters, to be published in June 2004.
[5] T. Ghani, et al., IEDM Tech. Dig., p. 978, 2003. [6] S. Thompson, et al., IEEE Electron Device Letters,
vol. 25, p. 191, 2004. [7] S. Datta, et al., IEDM Tech. Dig., p. 653, 2003. [8] B. Jin, et al., to be presented in SiGe: Materials,
Processing, and Devices at the ECS Meeting in Honolulu, Hawaii in Oct. 2004.
[9] R. Chau, et al., in Proceedings Int. Conf. on Solid State Devices & Materials, Nagoya, Japan, p. 68, 2002.
[10] B. Doyle, et al., VLSI Symp. Tech. Dig., p. 133, 2003.
[11] M. Radosavljević, et al., Appl. Phys. Lett., vol. 83, p. 2435, 2003.
[12] A. Javey, et al., IEDM Tech. Dig., p. 741, 2003. [13] L.J. Lauhon, et al., Nature, vol. 420, p. 57, 2002. [14] Y. Cui, et al. Nano Lett., vol. 3, p. 149, 2003. [15] T. Ashley, et al., IEDM Tech Digest, p. 751, 1997. [16] Y. Royter, et al., IEDM Tech. Digest, p. 731, 2003. [17] R. Chau, in Proceedings of 4th IEEE Conference
on Nanotechnology, Munich, Germany, Aug. 2004. [18] S. Thompson, et al., IEDM Tech Digest, p. 61,
2002. [19] K. Rim, et al., VLSI Symp. Tech. Dig., p. 98, 2002. [20] K. Rim, et al., IEDM Tech Digest, p. 517, 1995. [21] R. Chau, et al., Physica E, Low-dimensional
Systems and Nanostructures, vol. 19, p. 1 , 2003. [22] R. Chau, et al., IEDM Tech. Digest, p. 621, 2001. [23] N. Lindert, et al., IEEE Electron Devices Letters,
vol. 22, p. 487, 2001. [24] R. Chau, et al., IEDM Tech. Digest, p. 45, 2000.
Figure 16. Gate delay (intrinsic device speed CV/I) versus transistor physical gate length of novel nanoelectronic PMOS devices and Si MOSFETs [17].
Figure 17. Gate delay (intrinsic device speed CV/I) versus transistor physical gate length of novel nanoelectronic NMOS devices and Si MOSFETs [17].
