2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology

ICSICT-2020Final Program

Nov. 3- Nov. 6, 2020, Kunming, China

2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology

Nov. 3- Nov. 6, 2020, Kunming, China

http://www.icsict.com==============================================================================

Sponsored byIEEE Beijing Section

Co-Sponsored byFudan UniversityPeking University Yunnan niversity

Organized byFudan University

Supported byIEEE, EDS IEEE,SSCSTektronix, Inc.ProPlus Design Solutions, Inc.CVena High Technology Co.,LtdAMEDACYingbo Science & InstrumentNational Natural Science Foundation of China

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Contents

Tutorials................................................................................................................................................................................Paper Presentation Information............................................................................................................................................Technical Sessions................................................................................................................................................................Keynote Session 1................................................................................................................................................................Keynote Session 2................................................................................................................................................................Session A1 SOC 1(ROOM A)..............................................................................................................................................Session B1 Analog Circuit 1(ROOM B)..............................................................................................................................Session C1 Process Technology 1(ROOM C)......................................................................................................................Session D1 Device Technology 1(ROOM D)......................................................................................................................Session E1 Focus session(ROOM E)...................................................................................................................................Session A2 SoC 2(ROOM A)...............................................................................................................................................Session B2 Analog Circuit 2(ROOM B)..............................................................................................................................Session C2 Process Technology 2(ROOM C)......................................................................................................................Session D2 Device Technology 2(ROOM D)......................................................................................................................Session E2 Focus session(ROOM E)...................................................................................................................................Keynote Session 3................................................................................................................................................................Special Session A3 AI Circuit & System 1(ROOM A)........................................................................................................Session B3 AI Analog Circuit 3(ROOM B).........................................................................................................................Session C3 Compound & Organic devices 1(ROOM C).....................................................................................................Session D3 Device Technology 3(ROOM D)......................................................................................................................Session E3 Special session 1(ROOM E)..............................................................................................................................Session B4 Analog Circuit 4(ROOM B)..............................................................................................................................Session C4 Compound & Organic devices 2(ROOM C).....................................................................................................Session D4 Photoelectron and TFT 1(ROOM D)................................................................................................................Session E4 Special session 2(ROOM E)..............................................................................................................................Special Session A5 Digital Circuit(ROOM A).....................................................................................................................Session B5 RF Circuit 1(ROOM B).....................................................................................................................................Session C5 Photoelectron and TFT 2(ROOM C).................................................................................................................Session D5 Power Device and Reliability 1(ROOM D)......................................................................................................Session E5 AI and IoT (Process & Device)(ROOM E).......................................................................................................Session Poster Session circuit designⅡ ...............................................................................................................................Panel Session........................................................................................................................................................................Session A6 Clock Circuit (ROOM A)..................................................................................................................................Session B6 RF Circuit 2 (ROOM B)....................................................................................................................................Session C6 Power Device and Reliability (ROOM C).........................................................................................................Session D6 Memory Technology (ROOM D)......................................................................................................................Session A7 EDA 1 (ROOM A)............................................................................................................................................Session B7 Data Converter 1 (ROOM B)............................................................................................................................Session C7 MEMS and Sensors (ROOM C)........................................................................................................................Session D7 Memory Technology (ROOM D)......................................................................................................................Session A8 EDA 2 (ROOM A)............................................................................................................................................Session B8 Data Converter 2 (ROOM B)............................................................................................................................Session C8 Device Simulation and Modeling (ROOM C)...................................................................................................Session D8 Device Simulation and Modeling (ROOM D)..................................................................................................Session Poster Session circuit designⅢ ..............................................................................................................................Paper Code Index Table(//)...................................................................................................................................................Conference Rooms...............................................................................................................................................................

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Tutorials

09:00-10:30, Nov. 3, 2020T-1 Electrostatic Discharge Design for Digital, Analog and Radio Frequency (RF) ApplicationsDr. Steven Voldman , Comcast, USA

10:45-12:15, Nov. 3, 2020T-2 CMOS Transceiver Realizing Terahertz Wireless Communication, The Key Technology of

Beyond 5GProf. Minoru Fujishima, Graduate School of Advanced Sciences of Matter, Hiroshima University, Japan

14:00-15:30, Nov. 3, 2020T-3 Fabrication and Applications of Bulk and SOI FinFETsDr. Rita Rooyackers ClaRoo, Leuven, Belgium

15:45-17:15, Nov. 3, 2020T-4 Physical Hardware Attacks with Machine LearningProf. Bah-Hwee Gwee, NTU, Singapore

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ICSICT 2020 Technical Program OverviewDate Time Room（A） Room （B） Room （C） Room （D） Room （E）Nov.

39:00:12:15 Tutorial Session T1 & T2

14:00-17:15 Tutorial Session T3 & T4

Nov.4

8: 30-9: 00 Opening 9: 00-10: 30 Keynote Session K1-1 & K1-2

10: 45-12: 15 Keynote Session K2-1 & K2-2

13: 30-15: 30Session A1 Session B1 Session C1 Session D1 Session

E1SoC 1 Analog Circuit 1 Process

technology Device

Technology Focus session

15: 45-17: 45Session A2 Session B2 Session C2 Session D2 Session

E2SoC 2 Analog Circuit 2 Process

technology Device

Technology Focus session17: 45-18: 45 Poster Session I device & process

Nov.5

8: 30-10: 00 Keynote Session K3-1 & K3-2

10: 15-12: 15Special

Session A3 Session B3 Session C3 Session D3 Session E3AI Circuit & System 1 Analog Circuit 3 Compound &

Organic devices Device

Technology Special session

13: 30-15: 30Special

Session A4 Session B4 Session C4 Session D4 Session E4AI Circuit & System 2 Analog Circuit 4 Compound &

Organic devicesPhotoelectron

and TFT Special session

Nov.5

15: 45-17: 45

Special Session A5 Session B5 Session C5 Session D5 Session E5

Digital Circuit RF Circuit 1 Photoelectron and TFT

Power Device and Reliability

AI and IoT (Process &

Device)17: 45-18: 45 Poster Session II circuit design

Nov.6

8: 30-10: 00 Panal Discussion Session Chair :

10: 15-12: 15Session A6 Session B6 Session C6 Session D6Clock Circuit RF Circuit 2 Power Device

and ReliabilityMemory

Technology

13: 30-15: 30Session A7 Session B7 Session C7 Session D7

EDA 1 Data Converter 1

MEMS and Sensors

Memory Technology

15: 45-17: 45Session A8 Session B8 Session C8 Session D8

EDA 2 Data Converter 2

Device Simulation and

Modeling

Device Simulation and

Modeling17: 45-18: 45 Poster Session Ⅲ circuit design

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Paper Presentation InformationThe 2020 IEEE ICSICT will have oral and poster sessions. All the papers included in the conference program should be presented in English by one of the authors at the arranged session.

1. Oral PresentationPresentation time:Invited paper (30 minutes): 30 min talk in video

Regular paper (15 minutes): 15 min talk in video30min upload video is required.

2. Poster PresentationPoster size: 120 cm (high) × 100 cm (wide)；5-10min talk in video

Poster Session 1:

Presentation time: 17:45‐18:45 on Nov. 4, 2020.

Display time: 8:30‐18:45 on Nov. 4, 2020.

Poster Session 2:

Presentation time: 17:45‐18:45 on Nov. 5, 2020.

Display time: 8:30‐18:45 on Nov. 5, 2020.

Poster Session 3:

Presentation time: 17:45‐18:45 on Nov. 6, 2020.

Display time: 8:30‐18:45 on Nov. 6, 2020.

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Technical Sessions

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Keynote Session 1Session Chair: Prof. Ru Huang (Peking University, China)

09:00 K1-1 Enabling 5G and EDGE AI advances in slowing Moore's Law eraNov.4 (Invited) Dr. Chidi Chidambaram

VP of Qualcomm, USA

09:45 K1-2 Technology Innovations: DRAM, NAND & Emerging MemoryNov.4 (Invited) Dr. Jeongdong Choe

Senior Technical Fellow at TechInsights, Canada (Abstract)

Keynote Session 2Session Chair: Prof. Wei Zhang (Fudan University, China)

10:45 K2-1Negative Capacitance in Ferroelectric-Gated MOSFETs: Is It Science Fact or Science Fiction?

Nov.4 (Invited) Prof. T.P. MaYale University, USA

11:30 K2-2Role of Implant and BASN Technologies in Enabling a Global-scale Deployment of Future Sensor-rich Telemedicine Paradigm

Nov.4 (Invited) Prof. Habib F RashvandWarwick University, UK

Session A1 SOC 1(ROOM A)Session Chair: Prof. J.F Kang (Peking University, China)

13:30 A1-1 Feeding Computation Units As NeededNov.4 (Invited) Yaohua Wang

School of Computer Science, National University of Defense Technology, Changsha, China

14:00 A1-2 SPAD Properties and the Implications on Signal Processing for SPAD-based LiDARsNov.4 (Invited) Tzu-Hsien Sang1*, TsungPo Yu1, and Ning-Kai Yang1

1Institute of Electronics, National Chiao Tung University, Hsin-Chu, Taiwan

14:30 A1-3HPME: A High-Performance Hardware Memory Encryption Engine Based on RISC-V TEE

Nov.4 Tianyu Yin1, Guozhu Xin1, Jun Han1

1State Key Laboratory of ASIC and System, Fudan University, Shanghai, China

14:45 A1-4Research and Development of QR Code Steganography Based on JSteg Algorithm in DCT Domain

Nov.4 Yanfei Sun1, Mengyuan Yu1, Junyu, Wang1,2*1State Key Laboratory of ASIC&System, Fudan University, Shanghai, China; 2Zhuhai Fudan Innovation Institute, Zhuhai Guangdong, China

15:00 A1-5Multi-channel signal processing heterogeneous microsystem based on FPGA and Application Processor

Nov.4 Fan Chang, Jun Cheng, Jianling Yang, Hanting Huang, Kuizhi Mei*School of Microelectronics, Xi’an Jiaotong University, Xi’an, China

15:15 A1-6A Novel Shortest-distance Path-based Multicast Routing Algorithm for Network-on-Chips

Nov.4 Yong Qin, Yi Liu*, Changqin Xu, Xiaodong WenDepartment of Microelectronics, Xidian University, Xian, China

Session B1 Analog Circuit 1(ROOM B)

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Paper Code Index TablePID SID PID SID PID SID PID SID

K1-1 K1-1 S0989 D6-2 S1046 C7-4 S1100 P1-2

K1-2 K1-2 S0990 B7-6 S1048 P2-10 S1101 P2-2

K2-1 K2-1 S0991 A6-1 S1052 D5-4 S1103 B8-4

K2-2 K2-2 S0992 P3-11 S1056 P1-13 S1104 D5-6

K3-1 K3-1 S0993 C1-2 S1057 C4-4 S1105 C8-4

K3-2 K3-2 S0994 D5-1 S1058 D6-6 S1106 C1-3

S0945 P2-19 S0995 A1-3 S1059 C8-2 S1107 B2-4

S0946 A5-3 S0997 B8-5 S1060 E4-1 S1108 B3-1

S0947 B8-6 S0998 P1-16 S1061 E3-4 S1109 P3-24

S0949 D5-2 S0999 P2-13 S1062 D4-4 S1110 B2-7

S0950 P1-12 S1002 P1-22 S1063 B5-4 S1111 D1-6

S0951 B7-2 S1003 B3-7 S1064 B2-3 S1112 C7-5

S0956 E5-1 S1004 P2-22 S1065 A1-1 S1113 P2-24

S0958 B6-1 S1008 P2-23 S1066 D4-5 S1115 A8-3

S0959 P2-20 S1009 D6-4 S1067 A1-2 S1116 D3-4

S0960 B8-1 S1010 E4-3 S1068 B6-2 S1117 B7-4

S0961 A7-1 S1011 A8-6 S1069 D5-5 S1118 P1-35

S0962 D6-1 S1012 P3-20 S1070 A1-5 S1119 D7-1

S0964 E1-4 S1014 P1-10 S1071 A8-5 S1120 E5-4

S0965 B1-1 S1015 C3-3 S1072 P1-33 S1121 C4-5

S0966 P2-21 S1016 P1-27 S1074 A2-3 S1122 C8-5

S0967 P3-19 S1017 D2-2 S1077 A5-4 S1123 E1-1

S0968 D1-3 S1019 P1-23 S1078 P2-1 S1127 D5-7

S0969 P1-32 S1020 P2-9 S1080 A5-2 S1128 P3-13

S0970 P2-8 S1021 B3-6 S1081 A4-4 S1129 P3-14

S0971 C1-1 S1022 D5-3 S1082 P3-23 S1130 P3-15

S0972 P2-11 S1025 P3-22 S1084 A2-4 S1131 P3-1

S0973 B4-6 S1026 A4-3 S1085 P1-34 S1132 P3-2

S0974 A3-1 S1028 P1-24 S1086 A8-7 S1133 A6-2

S0976 D6-3 S1029 C3-4 S1087 P1-5 S1134 C8-6

S0977 A4-2 S1031 E4-4 S1088 C4-1 S1135 B7-7

S0978 C3-1 S1032 P1-28 S1090 C8-3 S1136 A7-3

S0980 P1-26 S1033 C3-2 S1091 P3-21 S1137 B6-3

S0981 E5-2 S1036 P3-12 S1092 A2-5 S1138 B1-6

S0982 P2-25 S1038 B2-2 S1093 E5-3 S1139 P3-3

S0983 E3-3 S1040 C3-5 S1095 B1-3 S1141 B1-4

S0984 P1-1 S1041 C7-3 S1096 D1-5 S1143 P1-3

S0985 P2-12 S1042 D6-5 S1097 E4-2 S1144 E3-1

S0986 D4-1 S1044 A3-3 S1098 A6-6 S1145 D6-7

S0988 D1-4 S1045 A8-4 S1099 C1-4 S1146 B4-5

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PID SID PID SID PID SID PID SID

S1147 P3-4 S1197 D7-4 S1244 C6-4 S1291 B1-7

S1148 P1-29 S1198 P3-16 S1245 A8-2 S1292 A4-1

S1149 A4-6 S1199 B7-3 S1246 C6-2 S1293 C7-2

S1150 B3-3 S1200 D4-2 S1247 D1-1 S1294 D3-1

S1151 C2-1 S1201 B3-5 S1248 A6-5 S1295 D3-2

S1153 C2-4 S1202 B4-4 S1249 D8-2 S1296 D8-6

S1154 D5-8 S1203 B4-3 S1250 A6-3 S1297 P2-17

S1155 C7-6 S1204 B8-2 S1251 A6-4 S1298 P2-18

S1156 A7-4 S1205 A1-4 S1253 P1-31 S1300 B5-1

S1157 E2-2 S1206 P3-17 S1254 A7-5 S1301 P1-25

S1163 P3-5 S1207 A3-6 S1255 D8-3 S1302 P1-19

S1164 B3-2 S1208 P3-26 S1256 C2-5 S1304 C2-6

S1165 P2-14 S1209 C4-3 S1257 D1-2 S1308 P3-18

S1166 C2-2 S1210 A3-7 S1258 A7-6 S1309 C5-2

S1167 P1-30 S1211 D4-3 S1259 D8-4 S1314 C4-6

S1168 C4-2 S1213 P3-6 S1260 C5-3 S1317 B4-2

S1169 A1-6 S1214 B3-4 S1261 A8-1 S1318 E2-1

S1170 P1-6 S1215 A3-4 S1262 D2-4 S1319 E1-2

S1171 P3-25 S1217 B2-6 S1263 C7-1 S1322 E2-3

S1172 A4-7 S1218 D8-1 S1264 D7-6 S1324 E2-4

S1173 A3-5 S1219 B8-7 S1265 B1-2 S1327 A3-2

S1174 P3-7 S1220 E3-2 S1266 D7-7 S1331 C8-1

S1175 B8-3 S1221 A2-2 S1267 C6-5 S1335 D3-3

S1176 B7-5 S1222 A5-5 S1268 D8-5

S1177 P2-3 S1223 D7-2 S1269 C6-6

S1178 P2-4 S1224 P2-7 S1270 P1-18

S1179 D7-3 S1225 C5-1 S1271 P1-7

S1180 B6-4 S1226 A5-6 S1273 C6-7

S1181 B2-1 S1227 A5-7 S1274 P1-15

S1182 A2-6 S1231 D2-6 S1275 P1-8

S1183 P1-20 S1232 C6-1 S1276 P1-11

S1184 P1-4 S1233 A2-1 S1277 D2-5

S1185 B5-3 S1234 B7-1 S1280 P1-9

S1186 C6-3 S1235 P1-14 S1281 A5-1

S1187 P2-5 S1236 C2-3 S1282 E1-3

S1188 P3-8 S1237 B2-5 S1283 D3-5

S1189 P3-9 S1238 D2-3 S1284 P1-21

S1190 C8-7 S1239 P2-15 S1285 A5-8

S1193 B4-1 S1240 B5-2 S1286 P2-16

S1194 A4-5 S1241 B1-5 S1287 A7-2

S1195 P3-10 S1242 D7-5 S1289 D2-1

S1196 P2-6 S1243 P1-17 S1290 A2-7