Rev. A (2012 02/10) By: AY, SA, JB (OPAL-RT) PLECS or SPS (no interpolation), the required step size...

Rev. A (2012 02/10)

By: AY, SA, JB (OPAL-RT)

OPAL-RT Technologies reserves all rights in this document and in the information contained herein. Reproduction, use or

disclosure to third parties without express authority is strictly forbidden.

A. Solar Power Conditioner Using a Zigzag-Connected Chopper

Converter (Public)

1) Circuit

2) Time step Requirement

3) Test Results and Accuracy

4) Possible Solutions

5) Typical Model Separation5) Typical Model Separation

6) Real time simulation performance of the conditioner system

7) References

Copyright (C) OPAL-RT Technologies 2

HIL Simulator of Solar Power Conditioner


Solar Power Conditioner Using a Zigzag-Connected Chopper Converter



Refer to reference (1)

The circuit was simulated:

With PLECS

With Simulink, SimPowerSystems (SPS)

With Simulink, SimPowerSystems, with ARTEMIS, and TSB blocks for

power converters

Compared Simulation accuracy and Speed


The simulation of PLECS, SPS, and TSB models showed that

the waveforms exactly the same at very small time-step (1 us)

Results are given on the next 3 slides.

Therefore, in following tests, the model “SPS at 1 us” was

taken as reference for the comparison.


The following tests were made on the circuit:

SPS: at 1 us & 10 us

TSB: at 1 us & 10 us

PLECS: at 1 us & 10 us


If the (fixed) time step is increased then: both SPS and PLECS models loose their accuracy

SPS-TSB model retains very good accuracy

This is understandable because the simulation of switching converters in the circuit requires the use of interpolation when fixed step is used. And Interpolation is available only in OPAL-RT’s TSB

OPAL-RT studies show the following figures: With PLECS or SPS (no interpolation), the required step size needed for good accuracy is 1 to 2

% or the PWM period

With TSB (with interpolation), the required step size is higher, 10-20 % of PWM period

25 to 50 us is usually needed for other power system components 25 to 50 us is usually needed for other power system components

Example – PV conversion system switching at 20 kHz (PWM cycle of 50 us), the required time step is: PLECS or SPS: 0.5 to 1 us

OPAL-RT TSB: 5 to 10 us

Solutions: Either decrease the time step to a very low value FPGA implementation

Or increase the time step to a reasonable value CPU implementation using TSB converter models


Bad results with non-characteristic unreal harmonics when

no interpolation is used (PLECS & SPS)

Incorrect steady state results without interpolation (PLECS & SPS)

Good results when TSB blocks are used, because of

interpolation of switching

good steady state results with TSB

Bad staircase relation between Duty Cycle and steady-state Bad staircase relation between Duty Cycle and steady-state

output without interpolation (PLECS, SPS) and good linear

relation with interpolation (TSB)

Because TSB uses interpolation, it is able and does simulate

dead-time effect (impossible with PLECS, or SPS)


1 m H 0.1 Ω100 V

load current

upperIG B T

lowerIG BT

1 m H 0.1 Ω100 V

load current

upperIG B T

lowerIG BT

The load current should be linearly

dependent upon the chopper duty-cycle


dependent upon the chopper duty-cycle

0 5 10 150

50

100

150Variation of Duty Cycle with step 0.1µs

Load Current Vs Duty Cycle

Lo

ad

Cu

rre

nt

(A)

duty Cycle (%)

TSB 0.1us

PLECS 0.1us

SPS 0.1us

0 10 20 30 40 500

100

200

300

400

500Variation of Duty Cycle with step 1µs


Lo

ad

Cu

rren

t (A

)

duty Cycle (%)

TSB 1us

PLECS 1us

SPS 1us


0 10 20 30 40 50 60 70 80 90 1000

200

400

600

800

1000Variation of Duty Cycle with step 10µs


Lo

ad

Cu

rren

t (A

)

duty Cycle (%)

TSB 10us

PLECS 10us

SPS 10us

SPS 10us

PLECS 10SPS_TSB_10us Observation

steady state results are

totally incorrect & not

acceptable without

interpolation (PLECS or

SPS), resulting in this

staircase shape when

duty is increased slowly

Mixed Simulation Targets

Converters on FPGA, with OPAL-

RT’s converter model for FPGA

Power component on CPU with

PLECS or SPS

All-CPU Simulation

Converters model one CPU with

OPAL-RT TSB

Power component on a second

CPU with PLECS or SPS


FPGA CPU CPU 1 CPU 2

Real time simulation performance of the PV conditioner developed in Matlab using OPAL-RT software platform

This real time simulation ran on a dual-Xeon-based, 3.33 GHz and RT-LAB simulator with a time step of 10µs.

The overall system was run using two CPUs core out of 12 processor cores available.

The processors allocation and Real-Time Performance are summarized in Table bellow.Table bellow.


CPUs

Descript

ions

Components Content Model

Calculation

Time

Minimu

m time

step

Accelera

tion

factor

CPU 1:

(10 µs)

SS_PV_conditioner

(complete system in slide 5)2.5 µs

5 µs 23CPU 2:

(10us)

SM_PV_conditioner

(controller)1 µs

Real time simulation performance of the PV conditioner developed in PLECS

A PLECS circuit cannot contain more than 1024 = 210 possibletopologies [2] which is equivalent to 10 switches per PLECS circuit.

The solution of this problem is to divide the system into a number ofPLECS sub-circuits in order to reduce the number of switches to lessthan 10 switches per PLECS.than 10 switches per PLECS.

The other solution is to increase the possible topologies by PLECSCompany.

The PV conditioner given in slide 5 was separated into two PLECScircuits. Each circuit contains one of the two phases of the PVconditioner.

This separation introduces some delays to connect the two PLECScircuits which can in some cases, affect the accuracy and the stabilityof the system depending on the number of delays introduced toseparate the system.


Real time simulation performance of the PV conditioner developed in Matlab using PLECS

This real time simulation ran on a dual-Xeon-based, 3.33 GHz and RT-LAB simulator with a time step of 10µs.

The overall system was run using two CPUs core out of 12 processor cores available.

The processors allocation and Real-Time Performance are summarized in Table bellow.


CPUs

Descript

ions

Components Content Model

Calculation

Time

Minimu

m time

step

Accelera

tion

factor

CPU 1:

(10 µs)

SS_PV_conditioner

(complete system in slide 5)2.5 µs

5 µs 14CPU 2:

(10us)

SM_PV_conditioner

(controller)1 µs

The processors allocation and Real-Time Performance are summarized in Table bellow.

1) Hideaki Fujita, “A High-Efficiency Solar Power Conditioner

Using a Zigzag-Connected Chopper Converter”, The 2010

International Power Electronics Conference, Tokyo Institute

of Technology, Tokyo, Japan.

2) PLECS Manual: www.plexim.com/files/plecsmanual.pdf


Rev. A (2012 02/10) By: AY, SA, JB (OPAL-RT) PLECS or SPS (no interpolation), the required step size...

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Transcript of Rev. A (2012 02/10) By: AY, SA, JB (OPAL-RT) PLECS or SPS (no interpolation), the required step size...