RegistersLab 5

Mano and Kime

Sections 5-2, 5-3, 5-7

4-BitRegister

q(n-1 downto 0)

clk clr

load

d(n-1 downto 0)

reg

library IEEE;use IEEE.std_logic_1164.all; entity reg is generic(width: positive); port ( d: in STD_LOGIC_VECTOR (width-1 downto 0); load: in STD_LOGIC; clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (width-1 downto 0) );end reg;

A Generic Register

architecture reg_arch of reg isbegin process(clk, clr) begin if clr = '1' then for i in width-1 downto 0 loop q(i) <= '0'; end loop; elsif (clk'event and clk = '1') then if load = '1' then q <= d; end if; end if; end process; end reg_arch;

q(n-1 downto 0)

clk clr

load

d(n-1 downto 0)

reg

Infers a flip-flop for alloutputs (q)

debounce entity

entity debounce isport (inp, clk, clr: in std_logic;outp: out std_logic);

end debounce;

debounceinp outp

clk clr

clk

inp

delay1

delay3

delay2

outp

debounce

clk

inpdelay1

delay3delay2

outp

architecture rtl of debounce issignal delay1, delay2, delay3: std_logic;begin process(clk, clr) begin if clr = '1' then delay1 <= '0';

delay2 <= '0'; delay3 <= '0'; elsif clk'event and clk='1' then delay1 <= inp; delay2 <= delay1; delay3 <= delay2;end if;

end process; outp <= delay1 and delay2 and (not delay3);end rtl;

debounce architecture

Lab 5 – A Single-Cycle Processor

mux4g

Tregclk

clr

Nregclkclr

Funit1

T

N

tin

SW(1:8)

LD(1:8)

Fcode(5:0)

msel(1:0)

tloadnload

y

dig7seg

A(1:4) AtoG(6:0)

cclk

clr

T

Prom

Pcountclr

clk

M

P

M

a b

fcodemseltload

Ny ground

a cb d

nload

anode =“1111”

fcode (hex) Name y

10 + b + a

11 - b - a

12 1+ a + 1

13 1- a - 1

14 INVERT Complement all bits of a.

15 AND b and a

16 OR b or a

17 XOR b xor a

18 2* Logic shift left a.

19 U2/ Logic shift right a.

1A 2/ Arithmetic shift right a.

1B RSHIFT Shift b a bits to the right. SHR(b,a);

1C LSHIFT Shift b a bits to the left. SHL(b,a);

1D   Reserved for multiplication

1E   Reserved for division

Funit1

y(n-1:0)

fcode(5:0)

b(n-1:0) a(n-1:0)

Add:

20 TRUE Set all bits in a to ‘1’.

21 FALSE Clear all bits in a to ‘0’.

22 NOT0=

TRUE if all bits in a are ‘0’. 

23 0< TRUE if sign bit of a is ‘1’.

24 U> TRUE if b > a (unsigned), else FALSE

25 U< TRUE if b < a (unsigned), else FALSE

26 = TRUE if b = a, else FALSE

27 U>= TRUE if b >= a (unsigned), else FALSE

28 U<= TRUE if b <= a (unsigned), else FALSE

29 <> TRUE if b /= a, else FALSE

2A > TRUE if b > a (signed), else FALSE

2B < TRUE if b < a (signed), else FALSE

2C >= TRUE if b >= a (signed), else FALSE

2D <= TRUE if b <= a (signed), else FALSE

fcode (hex) Name y

Funit1

y(n-1:0)

fcode(5:0)

b(n-1:0) a(n-1:0)

Add:

clk_pulse.vhd

cclk

BTN4delay1

delay3

delay2

clk

Pcount.vhd

-- A 4-bit up-counterlibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all; entity Pcount is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (3 downto 0) );end Pcount;

architecture Pcount_arch of Pcount issignal COUNT: STD_LOGIC_VECTOR (3 downto 0);begin process (clk, clr) begin if clr = '1' then COUNT <= "0000"; elsif clk'event and clk='1' then COUNT <= COUNT + 1; end if; q <= COUNT; end process;end Pcount_arch;

Pcount.vhd (cont.)

dig1(3:0)

dig2(3:0)

dig3(3:0)

dig4(3:0)

anode(1:4)

Mux4g

Acode

seg7dec

dig7seg

cclk

AtoG(6:0)

A(1:4)Aen(1:4)

Asel(1:0)

a

by

sel

y1

bnbufq1(1:0)

A(1:4)

d

c

ctr2bitclk

clrq

dig7seg.vhd

Prom

nload fcodemseltload

9 8 7 6 5 4 3 2 1 0

Single-cycle microcoded instructions

Instruction Operation

DUP Duplicate T to N.

SWAP Swap the contents of T and N

S@ Load the 8-bit byte from SW(1:8) into T and push T to N

Additional Instructions

library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all; entity Prom is port ( addr: in STD_LOGIC_VECTOR (3 downto 0); M: out STD_LOGIC_VECTOR (8 downto 0) );end Prom; 

Prom.vhd

Prom

Pcountclr

clk

M

P

 architecture Prom_arch of Prom isconstant dup: STD_LOGIC_VECTOR (9 downto 0) := "1000010000";constant swap: STD_LOGIC_VECTOR (9 downto 0) := "1100010000";constant Sfetch: STD_LOGIC_VECTOR (9 downto 0) := "1110010000";constant plus: STD_LOGIC_VECTOR (9 downto 0) := "0101010000";constant oneplus: STD_LOGIC_VECTOR (9 downto 0) := "0101010010";constant invert: STD_LOGIC_VECTOR (9 downto 0) := "0101010100";constant orr: STD_LOGIC_VECTOR (9 downto 0) := "0101010110";constant twotimes: STD_LOGIC_VECTOR (9 downto 0) := "0101011000";constant lshift: STD_LOGIC_VECTOR (9 downto 0) := "0101011100"

Prom.vhd

nload fcodemseltload

9 8 7 6 5 4 3 2 1 0

Lab 5 – A Single-Cycle Processor

mux4g

Tregclk

clr

Nregclkclr

Funit1

T

N

tin

SW(1:8)

LD(1:8)

Fcode(5:0)

msel(1:0)

tloadnload

y

dig7seg

A(1:4) AtoG(6:0)

cclk

clr

T

Prom

Pcountclr

clk

M

P

M

a b

fcodemseltload

Ny ground

a cb d

nload

anode =“1111”

Lab5.whpHEX

S@ \ 0069S@ \ 0069 0008lshift \ 6900S@ \ 6900 0037or \ 69372* \ D26ES@ \ D26E 00A4+ \ D312invert \ 2CED1+ \ 2CEE

subtype rom_word is std_logic_vector(9 downto 0);type rom_array is array (NATURAL range <>) of rom_word);constant rom: rom_array := (

Sfetch, -- then set switches to 08 hexSfetch, lshift,Sfetch, orr,

twotimes,Sfetch, plus,invert, oneplus,X”0000”, X”0000”);

begin process(addr) variable j: integer; begin j := conv_integer(addr); M <= rom(j); end process; end Prom_arch;

Prom.vhd (cont.)