Record Final

7/27/2019 Record Final

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CHAPTER 1

INTRODUCTION

Microprocessors and Microcontrollers have traditionally been designed around

two philosophies: Complex Instruction Set Computer (CISC) and Reduced Instruction

Set Computer (RISC). The CISC concept is an approach to the Instruction Set

Architecture (ISA) design that ephasi!es doing ore with each Instruction using a

wide variety o" addressing odes# variable nuber o" operands in various locations in

its Instruction Set. As a result# the Instructions are o" widely varying lengths and

e$ecution ties thus deanding a very cople$ Control %nit# which occupies a large

real estate on chip.

&n the other hand# the RISC 'rocessor wors on reduced nuber o" Instructions#

"i$ed instruction length# ore generalpurpose registers# loadstore architecture and

sipli"ied addressing odes which aes individual instructions e$ecute "aster# achieve

a net gain in per"orance and an overall sipler design with less silicon consuption as

copared to CISC. This gives the RISC Architecture ore roo to add onchip

peripherals# interrupt controllers and prograable tiers. The above "eatures ae the

RISC design ideally suited to participate in a power"ul trend in the ebedded 'rocessor

aret * the +system-on-a-chip+.

&ur ain ob,ective is to design an -/it Microprocessor. The Instruction cycle

consists o" three stages naely "etch# decode and e$ecute. A"ter every instruction "etch#

Control %nit generate signals "or the selected Instruction. &ur architecture supports 0

instructions. They can be broadly classi"ied into Arithetic# 1ogical# Shi"ting and

Rotational Instructions.

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1.1 Aim of the Project

The ob,ective o" the pro,ect is to design a -bit 3loating 'oint RISC processor.

It is to be designed to per"or a coplete set o" -bit arithetic "loating pointoperations. This processor ust e$ecute all the operations in a single cloc cycle. The

processor ust incorporate a eory within it to restrict the peripheral interaction

between the design and the eory. This is to achieve "aster e$ecution o" cycles.

In order to Ipleent the -/it 3loating point RISC 'rocessor# the "ollowing

e$periental procedure has been adopted

2. 3or the devised logic 4561 code "or various odules lie Cloc 7enerator#

Resetter# C1%# A1%# 'C# IR# M%8 is developed.

. /y using Active 561 Siulation so"tware tool# the code developed has been

siulated.

1.2 Technical Approach

Architectural design o" a -bit "loating point RISC processor "ro Speci"ications.

9 /ehavioral odeling o" 6esign blocs.

9 6esign o" stiulus odules to test the "unctionality o" 6esign blocs.

9 Synthesi!e design to e$tract 7ate level net list.

This RISC 'rocessor is designed to incorporate 0 basic instructions

involving Arithetic# 1ogical# 6ata Trans"er# Control instructions and 3loating 'oint

arithetic operations. To ipleent these instructions the design incorporates various

design blocs lie Control 1ogic %nit (C1%)# Arithetic 1ogic %nit (A1%)#

Multiple$er# Accuulator# 'rogra Counter ('C)# Instruction Register (IR)# Meory#

Cloc 7enerator# Resetter and additional glue logic lie bu""er# &R gate.

The Instruction "orat contains "irst "ive MS/s as &'C&6; and reaining R# 6CR.

1ogical : A>6# &R# 8&R# 8>&R# 1S5I3T# RS5I3T# CMA

Control : ?%M'# S@I'# 51T

6ata trans"er : 16A# STA

3loating 'oint : 3A66# 3S%/# 3M%1# 36I4.

To suari!e# the RISC is designed to enhance processor per"orance by eeping the

"ollowing design goals in ind.

The RISC (Reduced Instruction Set Coputer) ust use siple constructs and

have sall instruction set copared to CISC (Cople$ Instruction Set Coputer)

'rocessors. It is designed to achieve "aster e$ecutions. The striing "eature o" a RISC is

that# it e$ecutes each instruction within one cloc cycle. This is achieved by carrying

out ost o" the operations within the 'rocessor and inii!ing the use o" operations

reuiring slower peripherals.

Its architecture sipli"ies the instruction set and encourages the optii!ation o"

register anipulation. Alost all instructions have siple Register addressing. An

iportant aspect o" the instruction set is that it is easy to decode (3i$ed length

instruction "orat). Thus the &pcode and Instruction Register "ields can be accessed

siultaneously. 6ue to the sipli"ication o" instructions and their "orat# control logic

design is "urther sipli"ied.

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1.3 Orani!ation of The"i"

This thesis is divided into "ive parts. Chapter 1 is introduction. Chapter 2 is -

/it RISC 'rocessor# here the concepts are discussed RISC "eatures# Introduction to

'rocessors and Coparative studies o" CISC and RISC. Chapter 3 is design aspectsB

this chapter presents indetail o" RISC 'rocessor i.e. /loc 6iagra o" RISC 'rocessor#

Cloc 7enerator# Resetter# Control 1ogic 6ecoder# IR# A1%# M%8# 'rogra Counter#

Meory# /u""er. Along these odules the 4561 Code included. Chapter 4 is

siulation results# introduction o" 4561 language# -/it RISC 'rocessor odule

results and description. Chapter 5 is conclusion and "uture scope o" the wor. And

"inally appendi$ and bibliography included.


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CHAPTER 2

32 # $IT RI%C PROCE%%OR

2.1 Intro&'ction

This chapter presents "eatures o" RISC processor# when they cae into real

environent and speed with accuracy. 6i""erences between RISC processor and CISC

processor and detailed description o" the -bit RISC processor. Advantages and

6isadvantages o" both RISC processor and CISC processor

2.2 RI%C (eat're")

'rocessors are uch "aster than eories. 3or e$aple# a processor cloced at

200 M5! would lie to access eory in 20 nanoseconds# the period o" its 200 M5!

cloc. %n"ortunately# the eory inter"aced to the processor ight reuire D0

nanoseconds "or an access. So# the processor ends up waiting during each eory

access# wasting e$ecution cycles.

To reduce the nuber o" accesses to ain eory# designers added instruction

and data cache to the processors. A cache is a special type o" high speed RAM where

data and the address o" the data is stored. Ehenever the processor tries to read data

"ro ain eory# the cache is e$ained "irst. I" one o" the addresses stored in the

cache atches the address being used "or the eory read (called a hit)# the cache will

supply the data instead.

Cache is coonly ten ties "aster than ain eory# so you can see the

advantage o" getting data in 20 nanoseconds instead o" D0 nanoseconds. &nly when we

iss (i.e.# do not "ind the reuired data in the cache)# does it tae the "ull access tie o"

D0 nanoseconds. /ut this can only happen once. Since a copy o" the new data is written

into the cache a"ter a iss. The data will be there the ne$t tie we need it. Instruction

cache is used to store "reuently used instructions.

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6ata cache is used to store "reuently used data. Ipleenting "ewer

instructions and addressing odes on silicon reduces the cople$ity o" the instruction

decoder# the addressing logic# and the e$ecution unit. This allows the achine to be

cloced at a "aster speed# since less wor needs to be done each cloc period.

RISC typically has large set o" registers. The nuber o" registers available in a

processor can a""ect per"orance the sae way a eory access does. A cople$

calculation ay reuire the use o" several data values. I" the data values all reside in

eory during the calculations# any eory accesses ust be used to utili!e the.

I" the data values are stored in the internal registers o" the processor instead# their access

during calculations will be uch "aster. It is good then to have lot o" internal registers.

Eith icroprocessors getting "aster every year# eory architectures ust also

iprove to enhance overall syste per"orance. Seiconductor based electronics is the

"oundation to the in"oration technology society we live in today. ;ver since the "irst

transistor was invented way bac in 2G=# the seiconductor industry has been growing

at a treendous pace.

Seiconductor eories and icroprocessors are two a,or "ields# which are

bene"ited by the growth in seiconductor technology. The technological advanceent

has iproved per"orance as well as pacing density o" these devices over the years

(i're 1) Increa"in *emor+ capacit+ o,er the +ear"

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7ordon Moore ade his "aous observation in 2GDF# ,ust "our years a"ter the

"irst planar integrated circuit was discovered. 5e observed an e$ponential growth in the

nuber o" transistors per integrated circuit in which the nuber o" transistors nearly

doubled every couple o" years. This observation# popularly nown as *oore-" a/# has

been aintained and still holds true today. @eeping up with this law# the seiconductor

eory capacity also increases by a "actor o" two every year.

(i're 2) *oore0" a/

2.3 Intro&'ction to Proce""or"

The 'C processor business shoo o"" a wea econoic cliate to grow -.2

percent in unit shipents in the ?une uarter# but intense price copetition drove

revenues down .F percent# according to the latest nubers "ro International 6ata

Corp. Intel Corp. drove ost o" the growth# I6C said. +IntelHs processor shipents alone

grew nearly .- percent uartertouarter and 0.= percent yearonyear# while AM6Hs

processor shipents were about "lat#+ said Shane Rau# director o" I6CHs 'C chip

research in a press stateent.

The second uarter is usually a low point "or the year# Rau added. >evertheless#

C'% shipents were up 2D.2 percent "ro the sae uarter a year ago# showing thestrength o" the deand in the current period. 1ooing "orward# I6C predicts 'C


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processor sales "or all 00= will grow by ,ust


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So"tware can also be de"ined as either 2Dbit# -bit or Dbit# you can probably

see that theoreticallyi" you are using Dbit so"tware with a -bit processor then it

would tae two cloc cycles (-bits at a tie) to process any one set o" Dbits# this is

re"erred to as a bottlenec. This 6esign veri"ication and ipleentation will be done

using ;6A tools "ro the "ollowing vendors.

Simulation Tools:Active 561 "ro A16;C Inc.

2. Comparati,e %t'&ie" of CI%C an& RI%C)

CI%C) CISC is an acrony "or cople$ instruction set coputer.

The rea"on" to ha,e the lare in"tr'ction "et are)

CISC systes are cople$ as the architecture and the instructions are odi"ied

as per the technology and hence there is a reuireent "or ore nuber o" instructions

and there"ore will have any addressing odes.

The ain "unction o" any icroprocessor is to "etch the data and process it. The

chip as such doesnt have any provision "or eory i.e.# eory is e$ternal. As

process needs to access data "ro a eory or "ro IK& peripherals there is a necessary

"or ore instructions.

Dra/ac4" ehin& ha,in the lare in"tr'ction "et)

The large instruction set is responsible "or a very coplicated control logic that

generates a host o" control signals and interrupts that are iportant "or the woring o"

the processor.

This large instruction set creates probles "or the copiler as it has to write

code "or each individual instruction. It becoes di""icult to debug i" there is any

istae in the code o" the copiler.

The 1arge instruction set has a very coplicated decoding logic which is

responsible "or a ore nuber o" stages or "or an increased propagation delay o" the

control logic. This is because an increase in the nuber o" stages leads to proportionateincrease in the nuber o" gates.

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Transistor has a rise tie# a "all tie contributing to the propagation delay o" the

signal. So at every gate the signal gets delayed and this cuulative delay in propagation

adds up# to decrease the processing speed o" the data.They have a variety o" instruction

"orats lie one byte# two byte# three byte. They have a large nuber o" addressing

odes.

In general the pipelining is used to increase the speed o" eory operations with

separate control over the bus. They are di""icult to handle i" there is a considerable

di""erence between instruction lengths and e$ecution cycle o" di""erent instructions then

the pipeline design will be uch ore coplicated.

RI%C) RISC is an acrony "or reduced instruction set coputer.

The a&,antae" of in"tr'ction "et of RI%C are a" follo/")

In the RISC based syste the "reuently used instructions are hardware reali!ed

and it is there"ore inii!es the eory access tie and the decoding tie. It is easy

to write code "or "i$ed instruction set# so the copiler supports "or e""icient translation

o" high level language progras into achine language progras.

As the architecture supports pipeline in di""erent segents# it ay be possible to

e$ecute nuber o" instructions in a single instruction cycle. Meory access is liited

to load accuulator and store accuulator instructions only.

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CHAPTER 3

DE%I5N A%CEPT%

3.1 Intro&'ction

This chapter ainly concentrating on the design o" -bit RISC 'rocessor

(Individual Modules lie# Cloc 7enerator# Resetter# Control 1ogic 6ecoder# A1%#

'rogra Counter# Instruction Register# Multiple$er# Meory# Accuulator and /u""er).

To design each odule# here used 4561 language and "or Siulation Active561 tool

used.

The RISC 'rocessor Consists o" the "ollowing Coponents:

2) Cloc 7enerator

) Resetter

-) Control 1ogic 6ecoder

) Arithetic 1ogic %nit

F) 'rogra Counter

D) Instruction Register


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(i're 3) $loc4 Diaram of 326it RI%C Proce""or

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3.2 Cloc4 5enerator)

The bloc diagra o" Cloc 7enerator Module is shown in 3igure.

(i're ) Cloc4 5enerator

Module Description:

;very processor has its own builtin cloc# this cloc dictates how "ast the

processor can process the data (0Hs and 2Hs)# you will see processors advertised as having

a speed o" say 75!# this easureent re"ers to the internal cloc.

A ethod and syste are provided "or sel"tied processing. An operation is

e$ecuted with a "unctional unit. A tiing o" the operation e$ecution is siulated with a

tracing eleent# and a tracing signal is output. A seuencing signal is varied to the

"unctional unit in response to the tracing signal.

These a,or clocs drive large grids over the instruction "etch# integer# "loating

point# loadKstore# and bus inter"ace units# as well as the pads. They also drive local

clocs and local conditional clocs. The reasons "or ipleenting this clocing

hierarchy are to iprove per"orance and to save power. Multilevel bu""ering in the

cloc path allows circuit designers to reedy critical paths and race probles by

ad,usting the nuber o" bu""ers between driving and receiving state eleents and thus

+borrow+ tie "ro teporally ad,acent cloc cycles.

The cloc hierarchy saves power through cloc driver placeent and conditional

clocs. The local cloc drivers can be placed near their loads# reducing the routing

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capacitance and peritting saller drivers. Conditional clocing reduces pea power

when e$ecution e$clusivity is e$ploited.

I" a processor is advertised as having a speed o" 75! this eans that it can

process data internally billion ties a second (every cloc cycle)# so i" the processor is

a -bit processor running at 75! then it can potentially process - bits o" data

siultaneously# billion ties a second.

The cloc generator is a cobinational circuit that generates cloc signals that

are responsible "or the "unction o" the entire processor. The cloc signal gets its input

"ro a crystal oscillator that is connected "ro an e$ternal source. This is not shown

in this odule. The connection is understood to be iplicit.

The three clocs are generated as per the "ollowing logic. The "irst cloc Cloc2

synchroni!es with the e$ternal crystal oscillator. Ehile Cloc changes at the negative

edge o" Cloc2. So it has a period twice that o" Cloc2 and changes "or the negative

edge o" Cloc2. The third cloc 3etch changes at the positive edge o" Cloc. So it has

a period twice that o" Cloc# or e""ectively it has a period ties that o" Cloc2# and

changes only "or every other negative edge o" the e$ternal crystal oscillator.This sort o"

pattern is generated so that# eight distinct control signals can be generated by taing

di""erent cobinations o" these clocs.

7HD Co&e for Cloc4 5enerator)

--*****************************************************************--Entity Name: ClkGen

--Entity Description: The Clock Generator generates Clock Signals that are

-- responsible or the unction o the entire !rocessor"

--******************************************************************

library I;;;Buse I;;;.stdLlogicL22D.allB

--***************Input and utput !eclarations*********************

entity Cl7en is

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port ( Cl2 : in stdLlogicBRst : in stdLlogicBCloc2 : out stdLlogicB

Cloc : out stdLlogicB3etch : out stdLlogic

)B

end Cl7enB

architecture Clgen o" Cl7en is

--*********************Si"nal !eclarations*************************

signal Cl#3etch2:stdLlogicB

begin Cloc2NCl2B ClocNClB 3etchN3etch2B

--*****************************************************************

--Cloc#1 is Synchroni$ed %ith Cl#1&

--Cloc#2 chan"es at the 'e"ati(e )d"e o Cloc#1&

--*****************************************************************

process(Cl2#Rst) begin

i" (RstNH0H)thenClNH0HB

elsi" (Cl2NH0H and Cl2Hevent)thenClNnot ClB

end i"Bend processB

--*****************************************************************

--*+etch chan"es at the ,ositi(e )d"e o Cloc#2&

--*****************************************************************

process(Cl#Rst)begin

i" (RstNH0H)then3etch2NH0HB

elsi" (ClNH2H and ClHevent)then3etch2Nnot 3etch2B

end i"Bend processB

end Cl7enB

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3.3 Re"etter)

The bloc diagra o" Resetter Module is shown in 3igure. F

(i're ) Re"etter

Module Description:

The Resetter is a coponent that generates the internal reset signal. In Rst taing

the e$ternal reset reuest "ro the e$ternal world. The output "ro this odule supplies

all the coponents with the reset signal that initiali!es all the hardware coponents in

the syste. %nder RISC &S -.< and earlier a nuber o" special types o" reset were

available to the user. ;ach o" these reset types was triggered by holding a ey during a

reset.

Eith RISC &S D.0 and later# the only operations o" these which reain are the

6elete# Shi"t and eypad9. In order to support ultiple displays# it is possible to

con"igure the display which the syste will start up using. This can be a proble i" the

display con"igured is no longer present ("or e$aple# because the odule has been

reoved). I" the 0 ey (not the eypad0) is held during startup# the display will ("or this

session) be "orced to display nuber 0.

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7HD Co&e for Re"etter)

--*******************************************************************

--Entity Name : #es

--Entity Description : This Module generates the internal #eset Signal taking-- the e$ternal #eset Signal

--*******************************************************************


--***************Input and utput !eclarations******************

entity Res is

port ( RstRe : in ST6L1&7ICB

Cl : in ST6L1&7ICB 3etch: in ST6L1&7ICB Rst : out ST6L1&7IC

)B

end ResB--*******************************************************************

--The Rst Si"nal initiali$es all the hard%are Components in the system&

--*******************************************************************

architecture Res o" Res isbegin

--*******************************************************************

--Resetter operates at 'e"ati(e )d"e o Cl#2&

--*******************************************************************

process(Cl)begin

i"(RstReNH0H)then

RstNH0HB else RstNH2HB

end i"B

end processBend ResB

3. Control oic Deco&er)

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The bloc diagra o" Control 1ogic 6ecoder Module is shown in 3igure. D

(i're 8) Control oic Deco&er

Module Description:

The Control 1ogic 6ecoder is the ost iportant part o" the RISC processor. It

is central nervous syste o" the entire processor as it outputs the critical control signals

that are responsible "or the "unction o" the processor. It has the three cloc signals and

the Fbit &pcode as inputs.

6epending on the &pcode generated an individual set o" control signals are

generated that aes the RISC processor wor lie it does. The end user speci"ies this

pattern o" control signals that decides how the processor should "unction.

The control logic is nothing but a decoder that generates di""erent cobinations

based on di""erent inputs given. The bitpattern o" the control signals is speci"ied in the

"ollowing page.

('nctionalit+

2=


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C1&C@ CJC1; Rd 1dir Inc'c 1d'c 1dAcc Er

Address Setup 2 0 0 0 0 0 0

Instruction 3etch 2 0 0 0 0 0

Instruction 1oad 2 2 0 0 0 0Idle 2 2 0 0 0 0

Address Setup 0 0 2 0 0 0

&perand 3etch

Add# 3add# 3ul 2 0 0 0 0 0

Sub# 3sub# 3div 2 0 0 0 0 0

A>6 2 0 0 0 0 0

8&R 2 0 0 0 0 0

16A 2 0 0 0 0 0

8>&R 2 0 0 0 0 0

?%M' 0 0 0 2 0 0

S@I' 0 0 2 0 0 0

All &thers 0 0 0 0 0 0

A1%

Add# 3add# 3ul 2 0 0 0 2 0

Sub# 3sub# 3div 2 0 0 0 2 0

&R 2 0 0 0 2 0

8&R 2 0 0 0 2 0

8>&R 2 0 0 0 2 0

16A 2 0 0 0 2 0

A>6 2 0 0 0 2 0

?%M' 0 0 0 2 0 0

S@I' 0 0 2 0 0 0

STA 0 0 0 0 0 2

All &thers 0 0 0 0 0 0

Tale 1) ('nctionalit+ of CD

7HD Co&e for Control oic Deco&er)

--*******************************************************************

--Entity Name : Control-%ogic

--Entity Description : Control %ogic is the Central Ner&ous System o the entire

-- !rocessor" 't produces si$ control signals that are

-- responsible or the (unction o the !rocessor"

--*******************************************************************


entity ControlL1ogic is

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--*******************************************************************

--Input and utput !eclarations :- It has three Cloc# Si"nals and 5 it pCode as

-- Inputs& .dIr/.d,c/.d0cc/Inc,c/Rd/r as ut,uts

--*******************************************************************

port ( Cl2 : in stdLlogicB Cl : in stdLlogicB

3etch : in stdLlogicB Rst : in stdLlogicB &pCode : in stdLlogicLvector( downto 0)B

1dIr : out stdLlogicB Inc'c : out stdLlogicB

1d'c : out stdLlogicB 1dAcc : out stdLlogicB

Rd : out stdLlogicB

Er : out stdLlogic )B

end ControlL1ogicB

architecture ControlL1ogic o" ControlL1ogic is

--*********************Si"nal !eclaration************************

signal Con :stdLlogicLvector ( downto 0)B

beginConN(Cl2OClO3etch)B

process(con#rst#opcode)

--*********************Constant !eclarations************************

constant A66R;SSLS;T%'2 : stdLlogicLvector( downto 0):N+022+Bconstant I>STR%CTI&>L3;TC5 : stdLlogicLvector( downto 0):N+222+Bconstant I>STR%CTI&>L1&A6 : stdLlogicLvector( downto 0):N+002+Bconstant I61; : stdLlogicLvector( downto 0):N+202+B

constant A66R;SSLS;T%' : stdLlogicLvector( downto 0):N+020+Bconstant &';RA>6L3;TC5 : stdLlogicLvector( downto 0):N+220+Bconstant A1% : stdLlogicLvector( downto 0):N+000+Bconstant ST&R;LR;S%1T : stdLlogicLvector( downto 0):N+200+B

--*******************************************************************

--!ependin" on the pCode "enerated an indi(idual set o

--Control Si"nals are "enerated

--*******************************************************************

constant A66 : stdLlogicLvector( downto 0):N+00000+B

constant S%/ : stdLlogicLvector( downto 0):N+00002+Bconstant I>R : stdLlogicLvector( downto 0):N+00020+B

0


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constant 6CR : stdLlogicLvector( downto 0):N+00022+Bconstant A>6L&' : stdLlogicLvector( downto 0):N+00200+Bconstant &RL&' : stdLlogicLvector( downto 0):N+00202+Bconstant 8&RL&' : stdLlogicLvector( downto 0):N+00220+B

constant CMA : stdLlogicLvector( downto 0):N+00222+Bconstant 1S5I3T : stdLlogicLvector( downto 0):N+02000+Bconstant RS5I3T : stdLlogicLvector( downto 0):N+02002+Bconstant 16A : stdLlogicLvector( downto 0):N+02020+Bconstant STA : stdLlogicLvector( downto 0):N+02022+Bconstant ?%M' : stdLlogicLvector( downto 0):N+02200+Bconstant S@I' : stdLlogicLvector( downto 0):N+02202+Bconstant 5A1T : stdLlogicLvector( downto 0):N+02220+Bconstant 8>&RL&' : stdLlogicLvector( downto 0):N+02222+Bconstant 3A66 : stdLlogicLvector( downto 0):N+20000+Bconstant 3S%/ : stdLlogicLvector( downto 0):N+20002+B

constant 3M%1 : stdLlogicLvector( downto 0):N+20020+Bconstant 36I4 : stdLlogicLvector( downto 0):N+20022+B

begin

i"(RstNH0H)then 1dIr NH0HB 1dAcc NH0HB Rd NH0HB

1d'c NH0HB Inc'c NH0HB Er NH0HB

elsecase Con is

--*******************************************************************

-- Initiali$in" all the Control Si"nals to $ero

--*******************************************************************

when A66R;SSLS;T%'2 NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH0HB Inc'c NH0HB

Rd NH0HBEr NH0HB

--*******************************************************************

--y ma#in" Rd as 1 Instruction can e +etched rom the emory

--*******************************************************************

when I>STR%CTI&>L3;TC5 NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

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--******************************************************************

-y ma#in" Rd and .dIr as 1 !ata is .oaded into the Instruction Re"ister*

--*******************************************************************

when I>STR%CTI&>L1&A6 NP 1dIr NH2HB 1dAcc NH0HB 1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

--*******************************************************************

--*'o peration is ,erormed and allo%s the processor to Connect

--*******************************************************************

when I61; NP 1dIr NH2HB

1dAcc NH0HB 1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

--*******************************************************************

--*y ma#in" Inc,c as 1 the ,ointer points to the next emory .ocation *

--*******************************************************************

when A66R;SSLS;T%' NP 1dIr NH0HB1dAcc NH0HB1d'c NH0HBInc'c NH2HBRd NH0HBEr NH0HB

--*******************************************************************

--*,)R0'! +)TC:-

--*ne o the perand is stored in the 0ccumulator and Result o an *

--*peration is also stored in 0ccumulator&

--*******************************************************************

when &';RA>6L3;TC5 NP

CAS; &'C&6; ISwhen A66 NP 1dIr NH0HB


Er NH0HB

when 3A66 NP 1dIr NH0HB

1dAcc NH0HB 1d'c NH0HB


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Inc'c NH0HB Rd NH2HB

Er NH0HB

when 3S%/ NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

when 3M%1 NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH0HB Inc'c NH0HB

Rd NH2HBEr NH0HB

when 36I4 NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

when S%/ NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

when A>6L&' NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH0HB

Inc'c NH0HB Rd NH2HBEr NH0HB

when &RL&' NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

when 8&RL&' NP 1dIr NH0HB

-


24/100


Er NH0HB

when 8>&RL&' NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH0HB


Er NH0HB

when 16A NP 1dIr NH0HB 1dAcc NH0HB

1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

--*******************************************************************

--*y ma#in" .d,c as 1 the ,ro"ram Counter is .oaded %ith the (alue on Irut*

--*******************************************************************

when ?%M' NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH2HB Inc'c NH0HB Rd NH0HB

Er NH0HB

--*******************************************************************

--*y ma#in" Inc,c as 1 the next Instruction is s#ipped *

--*******************************************************************

when S@I' NP 1dIr NH0HB


Er NH0HB

when &T5;RS NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH0HB Inc'c NH0HB Rd NH0HB

Er NH0HBend caseB


25/100

--*******************************************************************

--* --***0rithmetic .o"ic 6nit***--

--*******************************************************************

when A1% NP

CAS; &'C&6; IS when A66 NP 1dIr NH0HB


Er NH0HB

when 3A66 NP 1dIr NH0HB 1dAcc NH2HB


Er NH0HB

when 3S%/ NP 1dIr NH0HB 1dAcc NH2HB 1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

when 3M%1 NP 1dIr NH0HB 1dAcc NH2HB 1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

when 36I4 NP 1dIr NH0HB 1dAcc NH2HB


Er NH0HB

when S%/ NP 1dIr NH0HB 1dAcc NH2HB 1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

when A>6L&' NP 1dIr NH0HB

F


26/100


Er NH0HB

when &RL&' NP 1dIr NH0HB 1dAcc NH2HB 1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

when 8&RL&' NP 1dIr NH0HB 1dAcc NH2HB 1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

when 8>&RL&' NP 1dIr NH0HB 1dAcc NH2HB 1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

when 16A NP 1dIr NH0HB 1dAcc NH2HB 1d'c NH0HB Inc'c NH0HB Rd NH2HB

Er NH0HB

when ?%M' NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH2HB Inc'c NH0HB Rd NH0HB

Er NH0HB

--*******************************************************************

--Instructions li#e S7I,/0.T/I'R/!CR/C0/.SI+T/RSI+T directly %or# on

--0ccumulator and Result is stored in 0ccumulator only&

--******************************************************************* when S@I' NP 1dIr NH0HB

D


27/100


Er NH0HB

when 5A1T NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH0HB Inc'c NH0HB Rd NH0HB

Er NH0HB

when I>R NP 1dIr NH0HB


Er NH0HB

when 6CR NP 1dIr NH0HB 1dAcc NH2HB 1d'c NH0HB Inc'c NH0HB Rd NH0HB

Er NH0HB

when CMA NP 1dIr NH0HB 1dAcc NH2HB 1d'c NH0HB Inc'c NH0HB Rd NH0HB

Er NH0HB

when 1S5I3T NP 1dIr NH0HB 1dAcc NH2HB 1d'c NH0HB Inc'c NH0HB Rd NH0HB

Er NH0HB

when RS5I3T NP 1dIr NH0HB 1dAcc NH2HB 1d'c NH0HB Inc'c NH0HB

Rd NH0HB Er NH0HB


28/100

when &T5;RS NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH0HB


Er NH0HBend caseB

--*******************************************************************

--* --***STR)8R)S6.TS***--

--*******************************************************************

when ST&R;LR;S%1T NPcase &pCode IS when ?%M' NP 1dIr NH0HB


Er NH0HB

when S@I' NP 1dIr NH0HB 1dAcc NH0HB 1d'c NH0HB Inc'c NH2HB Rd NH0HB

Er NH0HB--*******************************************************************

-y ma#in" the Result is stored in emory location speciied y perand 0ddress

--*******************************************************************

when STA NP 1dIr NH0HB 1dAcc NH2HB 1d'c NH0HB Inc'c NH0HB Rd NH0HB

Er NH2HB

when others NP 1dIr NH0HB 1dAcc NH2HB 1d'c NH0HB Inc'c NH0HB Rd NH0HB

Er NH0HB

end caseB

when others NP 1dIr NH0HB 1dAcc NH0HB

=


29/100


Er NH0HB

end caseB end i"Bend processBend ControlL1ogicB

3. Arithmetic oic Unit)

The bloc diagra o" Arithetic 1ogic %nit Module is shown in 3igure. 6# &R# >&T# 8&R and other /oolean operations. The C'%Hs

instruction decode logic deterine which particular operation the A1% should per"or#

the source o" the operands and the destination o" the result. In soe processors# the

A1% is divided into two units# an arithetic unit (A%) and a logic unit (1%).

Coputer arithetic is coonly per"ored on two very di""erent types o"

nubers integer and "loating point. Coputer progras calculate both positive and

negative nubers. So a representation that distinguishes the positive "ro the negativeis reuired. ;very coputer today uses twoscopleent binary representation "or

copleent binary nubers.

In arithetic unit# -bit A1% (addition and subtraction) design will be

constructed based on 4561. The 4561 hardware description language is used to

provide a gate level odel and siulation o" each design. A nuber o" di""ering

con"igurations o" binary adders e$ist "or inclusion into A1% design.

-0


31/100

&ne o" the ost popular ethods to reduce delay is to use a carry looahead

echanis. /y using carry looahead echanis# the propagation delay is reduced to

"ourgate level irrespective o" the nuber o" bits in the adder.

The "loating point instructions in the processor are written in this odule as

"unctions. They dont involve the cloc or the reset signal. They are ,ust cobinational

circuits that are ipleented by internal registers# counters and other sall

cobinational circuits. The arithetic logic unit consists o" a teporary register that is

used "or operations between the Accuulator and the data on the data bus. This register

is later assigned to the Accuulator.

The A1% as in this odule can be prograed to wor in any "ashion desired.

Any application or control desired can be obtained by writing a "unction o" the

application and running it in the A1% odule with the appropriate control signals "ro

the Control 1ogic 6ecoder.

The 3'% is also an internal part o" odern processors# the 3'% is designed to handle

any "loating point calculations and lie the A1% it has its algoriths hard coded (stored

peranently) inside the unit. Eith the Intel "aily o" processors up until the =0=D68

the "loating point unit was an e$ternal unit (coonly called a ath coprocessor)#

subseuent processors such as the 'entiu have the 3'% built in.

3or e$aple i" you had the (now old) =0-=DS8 processor "ro Intel you would

be able to purchase the =0-=< coprocessor which was in "act the "loating point unit. The

&pcode developed "or each instruction is tabulated in Table ..2.

Tale 2) Corre"pon&in Opco&e for each In"tr'ction

6ecial;uivalent

&pcode Instruction

0

2

-

00000

00002

00020

00022

A66

S%/

I>R

6CR

-2


32/100

F

D

&R

3A66

3S%/

3M%1

36I4

7HD Co&e for AU)

--*******************************************************************--Entity Name : )lu )rithmetic %ogic +nit,

--Entity Description : This Module perorms olloing .perations"

--)rithmetic : )DD/S+0/'N#/DC#"

--%ogical : )ND/.#/1.#/%S2'(T/#S2'(T/CM)"

--Control : 3+M!/S4'!/2)%T"

--Data Transer : %D)/ST)"

--(loating !oint : )DD/S+0/M+%/D'5"

--*******************************************************************

library I;;;B

use I;;;.stdLlogicL22D.allBuse I;;;.stdLlogicLunsigned.allB

--****************** Input9utput !eclarations ************************

entity Alu is

port ( 6ata : in stdLlogicLvector(-2 downto 0)B Acc&ut : in stdLlogicLvector(-2 downto 0)B &pCode : in stdLlogicLvector( downto 0)B Cl : in stdLlogicB

Rst : in stdLlogicB

-


33/100

Aluout : out stdLlogicLvector(-2 6&E>T& 0) )B

end AluB

architecture Alu o" Alu is

--*******************************************************************

--This +unction perorms +loatin" ,oint 0ddition&

--*******************************************************************

3unction "loatLadd(Accout#6ata:in stdLlogicLvector(-2 downto 0))return stdLlogicLvector is

--*******************************************************************

--This +unction to con(ert -it inary to inte"er&--*******************************************************************

3unction toLinteger($:in stdLlogicLvector(D downto 0))return integer is

--******************(ariale !eclararions******************************

variable su :integer:N0Bvariable Tep :StdLlogicLvector(D downto 0)Bbegin

tep:N$B

--*********;eneratin" loop to con(ert -it inary to inte"er**********

$$$: "or i in 0 to D loop i" (tep(i)NH2H)then

su:NsuQ99iB else

Su:NSuB

end i"B end loopB return suB

end "unctionB

--*********************s : integerB >uber &" Shi"ts

--


34/100

variable Ma#Mb : stdLlogicLvector( downto 0)B Mangitude &" Two antissasvariable ;S : stdLlogicB Sign &" Resulant ;$ponentvariable a#b : stdLlogicB Sign &" Two e$ponentsvariable s2#s : stdLlogicB Sign &" Two antissas

variable Sign : stdLlogicB Sign &" Resultant Mantissavariable E# : stdLlogicLvector(2 downto 0)Bvariable 8 : stdLlogicLvector(-2 downto 0)B 3inal Result

begin

MaIn:NAcc&ut( downto 0)BMbIn:N6ata( downto 0)B;a :NAcc&ut(-0 downto -)B;b :N6ata(-0 downto -)Ba :NAcc&ut(-0)B

b :N6ata(-0)B :N(aOb)B

--*******************************************************************

--*)=uali$ation o )xponents includes t%o steps&

--*1&Sutraction o )xponents&

--*2&0li"nement o antissas&

--*******************************************************************

scase is

when +00+ NP Mb:NMbInBMa:NMaInB

i"((;a(D downto 0))(;b(D downto 0))) then >S:NtoLinteger(;b(D downto 0);a(D downto 0))B "or $ in 2 to >s loop

Ma :N (H0H O Ma( downto 2))B

end loopB

I;:N;b(D downto 0)B

;s:N;b(s loop

Mb:N(H0H O Mb( downto 2))B

end loopB

I;:N;a(D downto 0)B;s:N;a(S:N>sB Ma:NMaB

-


35/100

Mb:NMbB I;:NI;B ;S:N;a(s loop

Mb:N(H0H O Mb( downto 2))B end loopB

I;:N;a(D downto 0)B ;S:N;a(S:NtoLinteger(;b(D downto 0)Q;a(D downto 0))B "or $ in 2 to >s loop

Ma:N(H0H O Ma( downto 2))Bend loopB

I;:N;b(D downto 0)B;S:N;b(s loopMb:N(H0H O Mb( downto 2))B

end loopBI;:N;a(D downto 0)B;S:N;a(s loop

Ma:N(H0H O Ma( downto 2))Bend loopBI;:N;b(D downto 0)B;S:N;b(S:N>sB

Ma:NMaBMb:NMbBI;:NI;B;S:N;a(


36/100

end caseB

--******************0ddition o antissas******************************

IR:NMaQMbB

--***********.o"ic or the Si"n o the antissa***************************

s2:NAcc&ut(-2)B s:N6ata(-2)B

E :N(s2Os)Bcase E is

when +00+ NP sign:NH0HBwhen +22+ NP sign:NH2HBwhen +02+ NP i"(;aP;b) then

sign:NH0HB elsi"(;a;b) then

sign:NH2HB elsi"(;aN;b) then i"(MaPMb) then

sign:NH0HB elsi"(MaMb) then

sign:NH2HB elsi"(MaNMb) then

sign:NH0HB else

sign:NsignB end i"B else sign:NsignB

end i"B

when +20+ NP i"(;aP;b) thensign:NH2HB

elsi"(;a;b) thensign:NH0HB

elsi"(;aN;b) then i"(MaPMb) then

sign:NH2HB elsi"(MaMb) thensign:NH0HB

elsi"(MaNMb) thensign:NH0HB

elsesign:NsignB

end i"B else sign:NsignB

end i"B

when others NP nullB

-D


37/100

end caseB

--***********+inal Result 0ter 0ddition*******************************

8:N(sign O ;S O I; O IR( downto 0))B return 8B

end "unctionB

--*******************************************************************

- This +unction perorms +loatin" ,oint Sutraction&

--*******************************************************************

3unction "loatLsub(Accout#6ata:in stdLlogicLvector(-2 downto 0)) return stdLlogicLvector is

--************+unction to con(ert -it inary to inte"er**************

3unction toLinteger($:in stdLlogicLvector(D downto 0))return integer is--*********************s : integerB >uber &" Shi"tsvariable Ma#Mb : stdLlogicLvector( downto 0)B Mangitude &" Two Mantissasvariable ;S : stdLlogicB Sign &" Resulant ;$ponentvariable a#b : stdLlogicB Sign &" Two ;$ponents

variable s2#s : stdLlogicB Sign &" Two Mantissasvariable sign : stdLlogicB Sign &" Resultant Mantissa

-


38/100

variable E# : stdLlogicLvector(2 downto 0)Bvariable 8 : stdLlogicLvector(-2 downto 0)B 3inal Result

begin

MaIn:NAccout( downto 0)BMbIn:N6ata( downto 0)B;a :NAccout(-0 downto -)B;b :N6ata(-0 downto -)Ba :NAccout(-0)B

b :N6ata(-0)B :N(aOb)B

--*******************************************************************

--*)=uali$ation o )xponents includes t%o steps&--*1&Sutraction o )xponents&

--*2&0li"nement o antissas&

--*******************************************************************

case is


i"((;a(D downto 0))(;b(D downto 0))) then >S:NtoLinteger(;b(D downto 0);a(D downto 0))B

"or $ in 2 to >s loop Ma:N(H0H O Ma( downto 2))B

end loopB

I;:N;b(D downto 0)B ;S:N;b(s loop Mb:N(H0H O Mb( downto 2))B end loopB

I;:N;a(D downto 0)B ;S:N;a(S:N>sB Ma:NMaB

Mb:NMbB I;:NI;B

;S:N;a(


39/100


>S:NtoLinteger(;a(D downto 0)Q;b(D downto 0))B "or $ in 2 to >s loop

Mb:N(H0H O Mb(downto 2))B

end loopB I;:N;a(D downto 0)B

;S:N;a(S:NtoLinteger(;b(D downto 0)Q;a(D downto 0))B

"or $ in 2 to >s loop Ma:N(H0H O Ma(

downto 2))B end loopB I;:N;b(D downto 0)B

;S:N;b(s loop

Mb:N(H0H OMb( downto 2))B

end loopB I;:N;a(D downto 0)B

;S:N;a(s loop

Ma:N(H0H O Ma(downto 2))B end loopB I;:N;b(D downto 0)B

;S:N;b(S:N>sB Ma:NMaB

Mb:NMbB I;:NI;B

;S:N;a(


40/100

when others NP nullBend caseB

--******************Sutraction o antissas***************************

IR:NMaMbB--***********lo"ic or the si"n o the mantissa************************

s2:NAccout(-2)B s:N6ata(-2)B

E:N(s2Os)Bcase E is

when +00+NP sign:NH0HBwhen +22+NP sign:NH2HB

when +02+NP i"(;aP;b)then sign:NH0HB

elsi"(;a;b) then sign:NH2HB

elsi"(;aN;b) then i"(MaPMb) then

sign:NH0HBelsi"(MaMb) then

sign:NH2HBelsi" (MaNMb) then

sign:NH0HBelse

sign:NsignBend i"B

elsesign:NsignB

end i"B

when +20+NP i" (;aP;b)thensign:NH2HB

elsi" (;a;b) thensign:NH0HBelsi" (;aN;b) then

i"(MaPMb) thensign:NH2HB

elsi"(MaMb) thensign:NH0HB

elsi" (MaNMb) thensign:NH0HB

elsesign:NsignB

end i"Belse

0


41/100

sign:NsignB end i"B

when othersNP nullB

end caseB

999999999993inal Result A"ter Subtraction9999999999999999999999999999

8:N(sign O ;S O I; O IR( downto 0))Breturn 8B

end "unctionB

--*******************************************************************

-- This +unction perorms +loatin" ,oint !i(ision&

--*******************************************************************

3unction "loatLdiv(Accout#6ata:stdLlogicLvector(-2 downto 0))return stdLlogicLvector is

--*********************


42/100

when +22+NP s:NH0HBwhen othersNP s:NH2HB

end caseB

--*******************************************************************--*+loatin" ,oint !i(ision includes +i(e steps&

--*1&Chec# or >eros&

--*2&)(aluate the si"n&

--*3&0li"n the !i(idend&

--*4&Sutraction o )xponents&

--*5&!i(ide the antissas&

--*************************1&Chec#in" or >eros********************

i"((2N+00000000000000000000000+) and(N+00000000000000000000000+)) then

report +>on Arithetic >ubers:'lease 4eri"y Inputs+B elsi"(N+00000000000000000000000+) then

report +>on Arithetic >ubers:'lease 4eri"y Inputs+Belse

2:N2B:NB

end i"B

--*****************************************************************

--*!i(idend 0li"nment :-

--*I !i(idend is "reater than or e=ual to the !i(isor/then

--*the !i(idend raction is Shited to the Ri"ht and

--*its )xponent is incremented y 1

--*****************************************************************

r2:N2Br:NB

i" (2P) thenr2:Nr2( downto 2)OH0HB;a:N;aQ2BTep:N(r2 O +00000000000000000000000+)BTep2:NTep(F downto -)B

--*******************************************************************

--;eneratin" the loop:-

--1&I !i(idend is smaller than the !i(isor then let shit until

-- it ecomes "reater or e=ual /#eep those many $eros in ?uotient&

--2&nce !i(idend ecame "reter then sutract !i(isor rom the

-- !i(idend and #eep 1 in ?uotient&

--3&Continue the procedure until numer o its in ?uotient ecome

-- 23/ecause the Remainder ne(er ecomes >ero&

--*******************************************************************

"or i in downto 0 loop i"(Tep2Pr) then


43/100

Rei:NTep2rB Rei:N(Rei(2 downto 0) O H0H)B

Rei(0):NTep(i)B(i):NH2HB

elsi"(Tep2r) then

Rei:NTep2+00000000000000000000000+B Rei:NRei(2 downto 0)OH0HB

Rei(0):NTep(i)B(i):NH0HB

elseTep2:NReiB

end i"B end loopB

elsi"(2Nr) then999Since /oth 6ividend and 6ivisor are ;ual uotient is ade H2H99

:N+00000000000000000000002+B elsi"(2)then

--*******************************************************************

--;eneratin" the loop:-

--1&I !i(idend is smaller than the !i(isor then let shit until

-- it ecomes "reater or e=ual /#eep those many $eros in ?uotient&

--2& nce !i(idend ecame "reter then sutract !i(isor rom the

-- !i(idend and #eep 1 in ?uotient&

--3& Continue the procedure until numer o its in ?uotient ecome

-- 23/ecause the Remainder ne(er ecomes >ero&

--*******************************************************************

Tep:N(r2 O +00000000000000000000000+)BTep2:NTep(F downto -)B

"or i in downto 0 loop

i"(Tep2PNr) thenRei:NTep2rBRei:N(rei(2 downto 0) O H0H )BRei(0):NTep(i)B(i):NH2HB

elsi"(Tep2r) then

Rei:NTep2+00000000000000000000000+BRei:N(rei(2 downto 0) O H0H)BRei(0):NTep(i)B(i):NH0HB

end i"BTep2:NReiB

-


44/100

end loopBend i"B

--**************.o"ic or the Si"n o )xponent****************

;a:Ne2(D downto 0)B;b:Ne(D downto 0)B

a :Ne2(


45/100

c:NH2HBe:N;bQ;aB

elsec:NH0HB

e:N+0000000+Bend i"B

when othersNP nullBend caseB

--***********+inal Result 0ter !i(ision***************************

8:N(S O C O e(D downto 0) O( downto 0))Breturn 8B

end "unctionB

--*****************************************************************

- This +unction perorms +loatin" ,oint ultiplication

--*****************************************************************

3unction "loatLul(Accout#6ata:in stdLlogicLvector(-2 downto 0))return stdLlogicLvector is

--*********************(ariale !eclarations***********************

variable e2#e : stdLlogicLvector(< downto 0)B Two ;$ponents Icluding Sign variable 2# : stdLlogicLvector(20 downto 0)B Magnitude & Two Mantissas variable s : stdLlogicB Sign &" Resultant Mantissa variable a#b : stdLlogicB Sign Two ;$ponents variable s2#s : stdLlogicB sign Two Mantissas variable ;a#;b : stdLlogicLvector(D downto 0)B Magnitude &" Two ;$ponents variable c : stdLlogicB Sign &" Resultant ;$ponent variable e : stdLlogicLvector(D downto 0)B Resultant e$ponent variable : stdLlogicLvector(2 downto 0)B Resultant Mantissa variable carry : stdLlogicB Carry

variable E# : stdLlogicLvector(2 downto 0)B variable $ : stdLlogicLvector(-2 downto 0)B 3inal Resultbegin

Carry:NH0HB e2 :NAccout(-0 downto -)B e :N6ata(-0 downto -)B 2 :NAccout(20 downto 0)B :N6ata(20 downto 0)B

--*****************************************************************

--+loatin" ,oint ultiplication includes T%o steps--1&0ddtion o )xponents

F


46/100

--2&ultiplication o antissas

--*****************************************************************

s2:NAccout(-2)B s:N6ata(-2)B

:N(s2Os)B

--************lo"ic or the si"n o the antissa*******************

case iswhen +00+ NP s:NH0HBwhen +22+ NP s:NH0HBwhen othersNP s:NH2HB

end caseB

--************lo"ic or the si"n o the exponent*******************

;a:Ne2(D downto 0)B;b:Ne(D downto 0)B

a :NAccout(-0)Bb :N6ata(-0)BE :N(aOb)B

case E is

when +00+ NP c:NH0HB e:N;aQ;bB

when +22+ NP c:NH2HBe:N;aQ;bB

when +02+ NP i"(;aP;b) then c:NH0HB e:N;a;bB

elsi"(;a;b) then c:NH2HB

e:N;b;aB else

c:NH0HB e:N+0000000+B end i"B

when +20+ NP i"(;aP;b) then c:NH2HB e:N;a;bB

elsi"(;a;b) then c:NH0HB e:N;b;aB

else

c:NH0HB e:N+0000000+B

D


47/100

end i"B


--*************lo"ic or multiplication**********************************

:N29B--***********+inal Result 0ter ultiplication*****************************

$:N(s O c O e(D downto 0) OCarry O (2 downto 0))Breturn $B

end "unctionB

beginprocess(Cl#Rst)

begin i" (RstNH0H) then

Alu&utN+00000000000000000000000000000000+B

--*******0.6 is .oaded at the 'e"ati(e )d"e o Cl#***************

elsi"(ClHevent and ClNH0H)then

--*************0.6 perorms around 2@ instructions***************

case &pCode isEhen +00000+ NP Alu&ut N Acc&utQ6ataBEhen +00002+ NP Alu&ut N Acc&ut6ataBEhen +00020+ NP Alu&ut N Acc&utQ+00000000000000000000000000000002+BEhen +00022+ NP Alu&ut N Acc&ut+00000000000000000000000000000002+BEhen +00200+ NP Alu&ut N Acc&ut and 6ataBEhen +00202+ NP Alu&ut N Acc&ut or 6ataBEhen +00220+ NP Alu&ut N Acc&ut $or 6ataBEhen +00222+ NP Alu&ut N not Acc&utBEhen +02000+ NP Alu&ut N (Acc&ut(-0 downto 0)OH0H)BEhen +02002+ NP Alu&ut N (H0HOAcc&ut(-2 downto 2))BEhen +02020+ NP Alu&ut N 6ataB

Ehen +02022+ NP Alu&ut N Acc&utBEhen +02200+ NP Alu&ut N Acc&utBwhen +02202+ NP Alu&ut N Acc&utBEhen +02220+ NP Alu&ut N Acc&utBEhen +02222+ NP Alu&ut N Acc&ut $nor 6ataB

--************************************************************

--The +loatin" ,oint Instructions in the processor are %ritten as +unctions

--************************************************************

when +20000+ NP Alu&ut N 3loatLAdd(Acc&ut#6ata)BEhen +20002+ NP Alu&ut N 3loatLsub(Acc&ut#6ata)B

when +20020+ NP Alu&ut N 3loatLul(Acc&ut#6ata)BEhen +20022+ NP Alu&ut N "loatLdiv(Acc&ut#6ata)B


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end i"Bend processB

end AluB

3.8 Proram Co'nter)

The bloc diagra o" 'rogra Counter Module is shown in 3igure.=.

(i're :) Proram Co'nter

Module Description:

The progra counter is one o" the essential parts o" the RISC processor. It eeps

on increenting the address o" the ne$t address location. It is nothing but a siple

counter that eeps on increenting when the control signal I>C'C appears at the input.

Ehen the 16'C signal is given# the progra counter is loaded with the value or

IR&%T. This taes place at the negative edge o" the 3etch signal.

=


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The 'rogra Controller was originally developed as a seuential control device

to replace electroechanical replays. 'Cs are reuired to use a ainly bit type data

structure# in general Microprocessors are used to handle byte or word type data. The 'C

reads# interprets and e$ecutes 'C instruction by "irware subroutines that are ade o"

the instructions o" the general icroprocessors.

The RISC architecture is a draatic "ro the historical trend in C'%

architecture. The RISC systes have a liited and siple instruction set through

analysis o" progra e$ecution characteristics# and ephasi!e on optii!ing theinstruction e$ecution pipeline "or iproveent o" the per"orance.

The 'Cs "unction is to put the ne$t instructions address on the e$ternal

eory device address port. The 'C also contains the echanis reuired to per"or

the ,up instruction (one o" the instructions which are not e$ecuted by the A1%) and

"or increenting the address.

7HD Co&e for PC)

--*******************************************************************

--Entity Name : !c !rogram Counter,

--Entity Description : !rogram Counter keeps on incrementing the address

-- register contents ater etching the 'nstruction rom memory"

--********************************************************************


use I;;;.stdLlogicLunsigned.allB

--***************Input and utput !eclarations***************************

entity 'c is port( Irout: in stdLlogicLvector(D downto 0)B

Rst : in stdLlogicB Inc'c: in stdLlogicB 1d'c : in stdLlogicB 'cout: out stdLlogicLvector (D downto 0)

)Bend 'cB

G


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architecture 'c o" 'c isbeginprocess(Rst#Inc'c)

--*********************(ariale !eclarations****************************

variable 'out:stdLlogicL4ector(D downto 0)B

begin

i"(RstNH0H)then 'out:N+000000000000000000000000000+B

'coutN'outB

--*******************************************************************

--,ro"ram Counter increments at the ,ositi(e )d"e o Inc,c--*******************************************************************

elsi" (Inc'cHevent and Inc'cNH2H)then i" (1d'cNH2H)then

'out:NIroutB 'coutN'outB

else 'out:N'outQ+000000000000000000000000002+B

'coutN'outB end i"B

end i"Bend processB

end 'cB

3.9 In"tr'ction Rei"ter)

The bloc diagra o" Instruction Register Module is shown in 3igure.G

F0


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(i're ;) In"tr'ction Rei"ter

Module Description:

The instruction register is a -bit register that is used to store the instruction

address a"ter it is "etched "ro the eory. This is used to go to the address location in

the eory that contains the &pcode and the operand. This synchroni!es with the

cloc 2 and InRst. 3or the positive edge o" the Cloc 2 when 16IR is one# the

instruction is loaded into the instruction register.

IR Consists o" two registers * one "or storing the opcode and the second "or

storing the operand. The RiSC2D is an =register# 2Dbit coputer. All addresses are

short wordaddresses (i.e. address 0 corresponds to the "irst two bytes o" ain eory#

address 2 corresponds to the second two bytes o" ain eory# etc.).

1ie the MI'S instructionset architecture# by hardware convention# register 0will always contain the value 0. The achine en"orces this: reads to register 0 always

return 0# irrespective o" what has been written there. The RISC2D is very siple# but it

is general enough to solve cople$ probles.

7HD Co&e for IR)

--*******************************************************************

--Entity Name : 'r'nstruction #egister,

F2


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--Entity Description : 'nstruction #egister stores the instruction address ater it is

-- : etched rom the Memory"

-- : 'nstruction #egister synchroni6es ith Clk7 8 #st

--*******************************************************************


--***************Input and utput !eclarations***************************

entity Ir isport ( 6ata : in stdLlogicLvector(-2 downto 0)B

Cl2 : in stdLlogicB 1dIr : in stdLlogicB Rst : in stdLlogicB Irout : out stdLlogicLvector (D downto 0)B

&pCode : out stdLlogicLvector( downto 0) )B

end IrB

--*******************************************************************

--Instruction address is used to "o to the address location in the emory

--that contains the pCode and perand&

--******************************************************************

architecture Ir o" Ir isbegin process(Cl2#Rst)

--*********************(ariale !eclarations************************

variable Iout : stdLlogicLvector(D downto 0)Bvariable &code : stdLlogicLvector( downto 0)B

begin i" (RstNH0H)then

Iout :N +000000000000000000000000000+B

&code :N +00000+BIr&utNIoutB &pCodeN&codeB

elsi" (Cl2Hevent and Cl2NH2H)then i" (1dIrNH2H)then

&code:N6ata(-2 downto


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&pCodeN&codeBend i"B

end i"B end processB

end IrB

3.: *'ltiple


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Module Description:

The Multiple$er is used to ultiple$ the outputs o" the instruction register and

progra counter i.e. IR&%T and 'C&%T respectively. This is done as# during the saecloc cycle (3etch) the eory is accessed by both these registers. As a result we need

to ultiple$ both o" the.

7HD Co&e for *'ltiple


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end Mu$B

3.; *emor+

The /loc diagra o" Meory Module is shown in 3igure. 22

(i're 11) *emor+

Module Description:

The Meory in the RISC processor is located inside the processor. This

decreases the eory access ties and iproves the speed o" the syste. There are

only two instructions that are used to access the eory# the load and Store

accuulator instructions. This is basically a RAM that is present inside the eory.

The RISC &S achines wor with two di""erent types o" eory lo"icaland

physical. The logical eory is the eory as seen by the &S# and the prograer.

Jour application begins at O=000 and continues until O$$$$$. The physical eory is

the actual eory in the achine.

FF


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%nder RISC &S# eory is broen into pages. &lder achines have a page o"

=K2DK-@ (depending on installed eory)# and newer achines have a "i$ed @ page.

I" you were to e$aine the pages in your application worspace# you would ost liely

see that the pages were seeingly rando# not in order. The pages relate to physical

eory# cobined to provide you with $$$$ bytes o" logical eory.

The eory controller is constantly shu""ling eory around so that each tas

that coes into operation HbelievesH it is loaded at O=000. Erite a little application to

count how any wip polls occur every second# youHll begin to appreciate how uch is

going on in the bacground.

7HD Co&e for *emor+)

--*******************************************************************

--Entity Name : Mem

--Entity Description : The Memory in the #'SC !rocessor is located inside the

-- !rocessor" This decreases the Memory access times

-- and impro&es the speed o the system"

--*******************************************************************


--***************Input9utput !eclarations******************************

entity Me is

port ( Address : in stdLlogicLvector(D downto 0)B Rd : in stdLlogicB

Er : in stdLlogicB 6ata : inout stdLlogicLvector(-2 downto 0) )B

end MeB

--*******************************************************************

--The only t%o Instructions that are used to access the emory are .oad

--and Store 0ccumulator&

--*******************************************************************

architecture Me o" Me is

type eory is array (0 to F00) o" stdLlogicLvector(-2 6&E>T& 0)B

FD


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--******************************************************************

--+unction to con(ert 2-it inary to inte"er

--*******************************************************************

"unction toLinteger($ : in stdLlogicLvector(D downto 0))

return integer is

--********************(ariale !eclararions*****************************

variable Su : integer :N 0Bvariable Tep : StdLlogicLvector(D downto 0)B

begin Tep:N$B

--*******************************************************************

--;eneratin" the .oop to con(ert 2-it inary to inte"er

--*******************************************************************$$$: "or i in 0 to D loop i" (Tep(i)NH2H)then

Su :N SuQ99iB else

Su:NSuB end i"B

end loopBreturn SuB

end "unctionB

--*******************************************************************

--The emory di(ided in to t%o sections&

--ne section is or storin" the Instructions and another is or !ata&

--Results are also stored in !ata section only&

--*******************************************************************

Instruction 6ecial "orsignal e :eory:N( 8+F00000-+# 16A F0 8+000000--+# A66 F2 8+F=0000D+# STA 6 F2

8+F=0000


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8+F00000-+# 16A F0$+0000000+# 1S 8+=000000+# RS

8+F=0000A+# STA R $+2=000000+# 6CR 8+2=000000+# 6CR

$+F=0000C+# STA


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8+2=0000F+# Fa,eform

The above wave"or re"ers to the Cloc 7enerator. 3or the Cloc 7enerator the

inputs are Cl2 and Reset Reuest (Rst). The output ainly depends upon the Rst.

De"cription)

Ehenever Rst is high# a"ter one cloc pulse Cloc and 3etch is high# at the

sae tie 3etch2 and Cl is also sae as that o" Cloc and 3etch. Ehenever cloc ishigh the 3etch is going to be 3etch the instruction# and send to the instruction register.

Ehenever Rst is low# a"ter one cloc pulse Cloc and 3etch is low# at the sae

tie 3etch2 and Cl is also sae as that o" Cloc and 3etch (i.e.# 1ow).

.3 Re"etter %im'late& >a,eform

DG


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(i're 1) Re"etter >a,eform

The above wave"or re"ers to the Resetter Eave"or. 3or the Resetter the

inputs are Cl# 3etch and Reset Reuest (Rst). The output ainly depends upon the

RstRe.

De"cription)

Ehenever RstRe is high# a"ter one cloc pulse o" Cl# then only Rst is high. It

doesnt depends on the 3etch signal. Ehenever RstRe is low# a"ter one cloc pulseCl# then Rst is low.

. Control oic Deco&er %im'late& >a,eform


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(i're 18) Control oic Deco&er >a,eform

The above wave"or re"ers to the Control 1ogic 6ecoder Eave"or. 3or the

C16 the inputs are Cl2# Cl# 3etch# &pcode and Reset(Rst). The output ainly

depends upon the Rst and &pcode.

De"cription)

Ehenever Cl2# Cl# Rst and 3etch is high# then the instruction is going to be

load into the Instruction Register. Ehen the 3etch is low# whatever the value is "etched#

that value is going to be loaded in the Accuulator continuously.

. Arithmetic oic Unit %im'late& >a,eform


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(i're 19) Arithmetic oic Unit /a,eform

The above wave"or re"ers to the Arithetic 1ogic %nit Eave"or. 3or the

A1% the inputs are 6ata# Accout# Cl# &pcode and Reset(Rst). The output ainly

depends upon the Rst and &pcode.

De"cription)

%ser asserting the values on 6ata# Accuulator out# Cl and &pcode# wheneverRst is high# then the instruction is going to be e$ecuted by the &pcode Instruction# then

the data will be appeared in Arithetic 1ogic %nit out.


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.8 Proram Co'nter %im'late& >a,eform

(i're 1:) Proram Co'nter >a,eform

The above wave"or re"ers to the 'rogra Counter Eave"or. 3or the 'C the

inputs are Ir&ut# Rst# Inc'c# and 1d'c. The output ainly depends upon the Rst# Irout

and Inc'c.

De"cription)

Ehenever Irout# Inc'c and Rst is high# then 'cout is increented by one

location. I" Rst is low the 'cout is going to be previous state (i.e.# initial position o"

'cout).


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.9 In"tr'ction Rei"ter %im'late& >a,eform

(i're 1;) In"tr'ction Rei"ter >a,eform

The above wave"or re"ers to the Instruction Register Eave"or. 3or the Ir the

inputs are 6ata# Cl2# 1dir and Rst. The output ainly depends upon the Rst and 1dir.

De"cription)

5ear input is -bit data# in this -bit data


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.: *'ltiple


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.; *emor+ %im'late& >a,eform

(i're 21) *emor+ >a,eform

The above wave"or re"ers to the Meory Eave"or. 3or the Meory the

inputs are Address# Rd and Er. The output ainly depends upon Rd.

De"cription)

Ehenever the Address value is given# Rd value is high# then the Address value isassigned to the 6ata and Meory input. The output will be stored in Meory location#

and the result will be displayed in 6ata.


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.1= Acc'm'lator %im'late& >a,eform

(i're 22) Acc'm'lator >a,eform

The above wave"or re"ers to the Accuulator Eave"or. 3or the Accuulator

the inputs are Aluout# Rst# 1dAcc and Cl2. The output ainly depends upon Rst and

1dAcc.

De"cription)

Ehenever the Aluout value is given# Rst# 1dAcc and Cl2 value is high# then the

Aluout value is assigned to the Accout. The Accuulator is behave lie as Aluout data

pointer a"ter all the states is satis"ied and one cloc pulse. Ehen the Reset value is low

the Accout value will go to initial state (i.e.# assigned !ero value).


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.11 $'ffer %im'late& >a,eform

(i're 23) $'ffer >a,eform

The above wave"or re"ers to the /u""er Eave"or. 3or the /u""er the inputs

are ;nb and Aluout. The output ainly depends upon ;nb.

De"cription)

Ehenever the ;nb value is high# then the Aluout value is assigned to the 6ata.

The /u""er will stores the data "or teporarily. Ehen the ;nb value is 1ow# then the

6ata will be shows as 5igh Ipedance value (i.e.# ).


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.12 Top *o&'le %im'late& >a,eform

(i're 2) Top *o&'le >a,eform

The above wave"or re"ers to the Top Module Eave"or. 3or the Top Module

the inputs are Cloc2# Cloc# 3etch and RstRe. The output ainly depends upon

RstRe.

De"cription)

Ehen Cloc2N0# ClocN0# RstReN2 and 3etchN2# then Rd is high# 1dir is

high and at the sae tie the data will be appear on the 6ata bus.

Ehen Cloc2N2# ClocN2# RstReN2 and 3etchN2# then Rd is high# 1dir is low

and at eh sae tie the previous data will be appear on the Irout. I" RstRe is low even

though other signals are high# the output will be initial state(i.e.#all are !eros).


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CHAPTER

CONCU%ION% ? (UTURE %COPE

.1 Concl'"ion

In this pro,ect it is observed that the RISC based syste is siulated using

4561. The overall syste is siulated and synthesi!ed# a"ter synthesi!ing the syste

we could get a statistical data about the nuber o" inputoutput bu""ers# the nuber o"

registers# nuber o" "lip"lops and latches were used in the usage o" 3'7A tool. The

odules siulated are Accuulator# /u""er# Cloc 7enerator# Instruction Register#

Multiple$er# 'rogra Counter# Resetter# Control 1ogic 6ecoder# Arithetic 1ogic %nit

and the overall syste. 3ew instructions were e$ecuted and their tiing seuences were

analy!ed. It is "ound that an each instruction taen 0ns.It shows that the di""erent

operations o" the instruction including the decoding and e$ecution coes to 0ns in the

overall syste. There"ore we conclude that the behavior shows# the syste is woring

as RISC as instruction will be e$ecuted within a single cloc cycle.

=0


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.2 ('t're %cope of the Project

The "loatingpoint ultiplication is not a coplete -bit operation as it

incorporates only an 22bit antissa. This can be iproved by ultiple$ing the result

or# by using the concept o" pipelining. A copiler to this processor can be reali!ed in

so"tware to "acilitate easy input and output to this processor. The -bit processor can be

ade to a Dbit processor aing inor odi"ications to the code. This increases the

data handling capability o" the A1%. It also increases the range o" nubers that can be

operated by the processor. The e$ception cases in the arithetic operations can be

"lashed to the user using seven segent displays. %sing the copiler can "acilitate these

operations.

=2


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APPENDI@ A

Intro&'ction to 7HD)

It is noticed "ro the available literature that the %nited States organi!ed a

worshop in 2G=2 to search "or a standard design and docuentation tool "or the very

highspeed integrated circuits (45SIC). In 2G=-# 6epartent o" 6e"ense (6&6)

established a standard 4561 based on the recoendation o" the worshop.

;""orts "or de"ining the new version o" 4561 started in 2GG0 by a tea o"

volunteers woring under the I;;; 6ASC (6esign Autoation Standards Coittee).

In &rder o" 2GG# a new 4561 re"erred as 4561 G- was copleted and released "or

review. A"ter inor odi"ications# this new version was approved by the 4561

balloting group ebers and becae the new 4561 language standard.

4561 is an acrony "or 4ery 5igh Speed Integrated Circuits 5ardware

6escription 1anguage. The language can be used to odel a digital syste at any

levels o" abstraction ranging "ro the algorithic level to the 7ate level. Thecople$ity o" the digital syste being odeled would vary "ro that o" a siple gate to

a coplete digital electronic syste. The 4561 1anguage can be regarded as an

integrated aalgaation o" seuential language# concurrent language# net list language#

tiing speci"ications and wave"or generation language.

The cople$ and laborious anual procedures "or the design o" the hardware

have paved the way "or the developent o" languages "or high level description can

serve as docuentation "or the part as well as an entry point into the design process.

The high level description can be processed through various steps in order to siulate

the hardware in the "or o" layout# printed circuit board or gate arrays using the

synthesis tools o" hardware description languages.

The I;;; standard 4561 hardware description language is such a language.

4561 was designed as a solution to provide an integrated design and docuentation to

counicate design data between various levels o" abstraction.

=


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De"in Unit" in 7HD)

4561 provides "ive di""erent types o" priary constructs called design units. They are:

2. ;ntity declaration

. Architecture body

-. Con"iguration declaration

. 'acage declaration

F. 'acage body

An entity is odeled using an entity declaration and at least one architecture

body (A hardware abstraction o" the digital syste is called an entity).

The ;ntity declaration speci"ies the nae o" the entity being odeled and lists

the set o" inter"ace ports. 'orts are signals through which the entity counicates with

the other odels in its e$ternal environent. So entity declaration describes the

e$ternal view o" the entity.

The architecture body contains the internal description o" the entity. 3or

e$aple# as a set o" concurrent or seuential stateents that represents the behavior o"

the entity. ;ach style o" representation can be speci"ied in a di""erent architecture body

or i$ed within a single architecture body. There"ore an architecture body using any o"

the "ollowing odeling styles speci"ies the internal details o" an entity. 3ig. 2.2 shows

an entity and one possible odel.

A con"iguration declaration is used to create a con"iguration "or an entity. It

speci"ies the binding o" one architecture body "ro the any architecture bodies that

ay be associated with the entity. It ay also speci"y the bindings o" coponents used

in the selected architecture body to other entities. An entity ay have any nuber o"

di""erent con"igurations.

A pacage declaration encapsulates a set o" related declarations# such as type

declarations# subtype declarations and subprogra declarations# which can be shared

across two or ore design units.

=-


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A pacage body contains the de"initions o" sub progras declared in a pacage

declaration.

(i 3) Pac4ae Declaration

A&,antae" of 7HD)

The "ollowing are the a,or capabilities that the language provides along with

the "eatures that di""erentiate it "ro other hardware description languages.

2) The language can be used as a counication ediu between di""erent

Coputer Aided 6esign (CA6) and Coputer Aided ;ngineering (CA;) tools.

) The language supports hierarchy i.e.# a digital syste can be odeled as a set o"

inter connected coponents# each coponent in turn can be odeled as a set o"

inter connected sub coponents.

-) The language supports "le$ible design ethodologies i.e.# topdown# bottoup

or i$ed.

) The language is technology independent and hence the sae behavior odel can

be synthesi!ed into di""erent vendor libraries.

F) It supports both Synchronous and Asynchronous tiing odel.

=


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D) 4arious digital odeling techniues such as "initestate achine descriptions#

algorithic descriptions and /oolean euations can be odeled using the

language.

SI standard. There"ore odels described using these

languages are portable. The governent also has strong interest in aintaining

this as standard so that reprocureent and second sourcing ay becoe easier.

=) There are no liitations that are iposed by the language on the si!e o" the

design. The sae odel can be synthesi!ed into di""erent vendor libraries.

G) The language has eleents that ae largescale design odeling easier. 3or

e$aple coponents# "unctions# procedures and pacages.

20) The language supports three basic di""erent description styles i.e.# structural#

data "low and behavioral. A design ay also be e$pressed in any cobination

o" these three descriptive styles.

22) It supports a wide range o" abstraction levels ranging "ro abstract behavioral

descriptions to very precise gate level descriptions.

(loatin Point ('nction")

2) 3loating 'oint 3unctions are incorporated into the design by writing the into

A1%. They are written as "unctions and are called at the beginning o" the

odule.

) Care should be taen that all the inputs given should be in the I;;;


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F) The carry generated in operations is displayed through essage and it is ad,usted

in the result by increenting the e$ponent value and right shi"ting the antissa

part by one.

(loatin Point IEEE # 9 %tan&ar& (ormat")

A "loating * point nuber is the one# which is capable o" representing real and

decial nubers. The "loatingpoint operations are incorporated into the design as

"unctions. The logic "or these is di""erent "ro the ordinary arithetic "unctions.

The nubers in convention have to be "irst converted into the standard I;;; N(2)S ;2< (2.M)

The "loating * point representation "or a standard single precision nuber is.

A single precision nuber is a -bit nuber that is segented to represent the

"loating * point nuber. The above representation is the I;;;


87/100

(loatin Point A&&ition)

2) The real nuber is "irst represented in the I;;;ow the nubers "ro the eory are loaded into two registers# naely

Accuulator and the Tep register that loads the value appearing on the data

bus.

) These nubers are distinct. So to add their antissas# we have to "irst norali!e

their e$ponents.

F) So# we copare the e$ponents and increent the e$ponent o" the lower

e$ponent while right shi"ting its antissa. This is done till the lower e$ponent

becoes eual to the higher one.

D) &nce the e$ponents are norali!ed. The antissas are then added to each other

and the result is then stored in a teporary register.


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(i 18) (loatin Point A&&ition or %'traction

==


89/100

(loatin Point %'traction)

2) The real nuber is "irst represented in the I;;;ow the nubers "ro the eory are loaded into two registers# naely

Accuulator and the Tep register that loads the value appearing on the data

bus.

) These nubers are distinct. So to subtract their antissas# we have to "irst

norali!e their e$ponents.

F) So# we copare the e$ponents and increent the e$ponent o" the lower

e$ponent while right shi"ting its antissa. This is done till the lower e$ponent

becoes eual to the higher one.

D) &nce the e$ponents are norali!ed. The antissas are then subtracted and the

result is stored in a teporary register.


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(loatin Point *'ltiplication)

2) 5ere the e$ponents and antissas o" the nubers in convention dont have to be

norali!ed.

) In ultiplication the operations are done siultaneously and separately on the

antissa and the e$ponent.

-) /inary ultiplication is de"ined "or single bit nubers in 4561# so the

e$ponents are ,ust added and the individual bits in the antissas are ultiplied

to get the "inal result.

) The "inal output is obtained by concatenating the product o" the antissas# the

resulting e$ponent and the sign o" the result that is calculated separately.

F) There is however a liitation to this operation. I" two nubers o" >bits are

ultiplied then the resulting nuber will be o" >bits thereby decreasing the

nuerical scope o" the inputs.

D) So each input should not e$ceed 2bits in length# so that the result is restricted

to not ore than bits.

G0


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(i 19) (loatin Point *'ltiplication

G2


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(loatin Point Di,i"ion)

2) This is ore coplicated than Multiplication# owing to the "act that apart "ro

taing care o" the e$ponent we have to consider the cases o" dealing with the

antissa.

) The logic "or "loating point division is as "ollows.

-) 3irst the e$ponents are directly added or subtracted depending on which is

bigger. Apart "ro that the "inal sign o" the division is calculated separately.

) >ow both the nubers in the I;;;ow since the greater o" the two nubers is decided# i" the >uerator is less

than the 6enoinator then we proceed to append the value o" the nuerator to !eros and load it into an internal register say Tep that consists o" Gbits.

>ow the "irst bits "ro the MS/ are copared with the divisor.

D) I" the divisor is ore than the dividend then we le"t shi"t the dividend by 2 and

add it to the twos copleent o" the divisor.


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(i 1:) (loatin Point Di,i"ion

G-


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a A&&re"" %et'p 1)

5ere all control signals load Accuulator (16ACC)# 1oad 'rogra Counter (16'C)#

Increent 'rogra Counter (I>'C)# 1oad Instruction Register (16IR)# Read (R6)#Erite (ER) are initiali!ed to ero.

In"tr'ction (etch)

In this stage UR6 control signal is ade high so that opcode and operand address are

placed on the data bus i.e.# reading an instruction "ro the eory which eans

"etching o" an instruction is over.

c In"tr'ction oa&)

At the positive edge o" the cloc 2 and when both R6 and 16IR are ade high the -

bit instruction is "etched "ro the eory and is loaded into Instruction Register. 3irst

"ive MS/ acts as &pcode which is connected to both A1% and Control 1ogic 6ecoder#

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f Operan& (etch)

%nder noral conditions the output o" the A1% is always connected to the

Accuulator. So# that the second operand is loaded into Accuulator "or "urtheroperation.

3or ;$aple the instructions lie A66# S%/# 3A66# 3S%/# 3M%1# 36I4# A>6# &R#

8&R# 8>&R# etc. second operand is loaded into Accuulator by aing the control

signals such as 1oad Accuulator 16ACC and Read R6 as high as possible. 3or

special instructions such as ?up# Sip# 51T the "ollowing are the procedures adopted

to e$plain the operation.

i BU*P In"tr'ction)

/y aing load progra counter (16'C) signal as unity# the value present in the output

o" the Instruction Register# IR&%T is loaded into the progra counter. The address o"

the progra counter is changed to the ,up address where the current instruction to be

e$ecuted.

ii %IP In"tr'ction)

7enerally progra counter eeps on increenting by aing Increent 'rogra

Counter Signal# I>C'C as unity in Address setup stage. &nce again when the I>C'C

is ade unity during the operand "etch stage the iediate ne$t location is sipped and

points to the ne$t address location.

iii HT In"tr'ction)

The processor is halted "or soe tie and no operation is per"ored during that tie.

The &pcode "or the 51T operation is U02220 (;).

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Arithmetic an& oic Unit AU)

3ew instructions were tried and e$ecuted using the A1%. The "loating point "unctions

are also carried out to siulate the test signals. Two operands "etched "ro the eoryare stored in Accuulator and Teporary Register o" A1%. 'articular operation is

per"ored on these two operands depends upon the &pCode given. The result is always

stored in Accuulator only. Suppose "or every instruction i" new operand is not given#

then the operation will be per"ored on the previous value stored in the Accuulator.

h %tore Re"'lt")

/u""er is inter"ace between the output o" the A1% (A1%&%T) and 6ata /us. %nless

and otherwise it is speci"ied the results will be in the Accuulator. &therwise the

results will be stored in eory via bu""er by aing write (ER) control signal as high.

There is a necessity to access the eory location siultaneously by both 'rogra

Counter and Instruction Register during the 3etch Cycle. There"ore we need the

ultiple$er "or both the &utput o" 'rogra Counter and Instruction Register. The

selection o" IR&%T and 'C&%T depends upon the 3etch Cycle.

/y way o" siulating the di""erent odules and the overall circuit results were obtained

and the sae was reali!ed by synthesis tools and the synthesis results also tabulated at

the end.

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APPENDI@ $

CISC Cople$ Instruction Set Coputer

RISC Reduced Instruction Set Coputer

C1% Control 1ogic %nit

A1% Arithetic 1ogic %nit

M%8 Multiple$er

'C 'rogra Counter

IR Instruction Register

45SIC 4ery 5ighSpeed Integrated Circuits

6&6 6epartent o" 6e"ense

6ASC 6esign Autoation Standards Coittee

CA6 Coputer Aided 6esign

CA; Coputer Aided ;ngineering

16ACC 1oad Accuulator

16'C 1oad 'rogra Counter

16IR 1oad Instruction Register

I>'C Increent 'rogra Counter

R6 Read

ER Erite

C'% Coputer 'rocess %nit

A% Arithetic %ni

Record Final

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