Rasit Onur Topaloglu and Alex Orailoglu {rtopalog | alex}@cse.ucsd.edu University of California at...

Rasit Onur Topaloglu and Alex Orailoglu {rtopalog | alex}@cse.ucsd.edu University of California at San Diego Computer Science and Engineering Department

La Jolla, CA, 92093, USA

On Mismatch in the Deep Sub-Micron Era: from Physics to Circuits

Outline-A Brief Overview of Mismatch-Challenges

-Design Flow Impact-Estimation of High Level Parameters

-Random Variation Effects-Accurate Mismatch Modeling

-Previous Work -Contributions

-Mismatch Prediction Techniques -Incorporation to Design Flow

-Experimental Verification-Insights for Future Modeling-Conclusions

A Brief Overview of MismatchMismatch = the difference of parameters in matched transistors

Iref

Vb1 Vb2

Vb3

60 60

60 60

300 300

60

60

120

120

60

60

30

30

1:1

= Δ(global + local + random transistor parameter variations)

Proper circuit operation requires high precision matching for certain transistors

1:2

Impact of Mismatch on VLSI Design

-Mismatch caused soft errors (reduction in gain, higher output R) -Critical mismatch necessitates re-design

Yield loss

Increased time to market

* Design for mismatch

* Estimate effects of mismatch during design to reduce iterations

-keeping standard analog design flow intact -early handling of mismatch

-estimating effects of mismatch on high level circuit parameters -correlation-sensitive methods -propagation of mismatch effects between circuit blocks

Traditional Challenges

DSM Challenges-consideration of random effects -accurate mismatch modeling

Analog Design Flow

Manual design

SPICE simulations

Select architecture and technology

Optimizations

Test & diagnosis after production

Behavioral level design and simulations

Costly redesign needed due to late observation of mismatch effects

SPICE simulations

Optimizations

Analog Design Flow

Manual design

SPICE simulations


Optimizations



Essential to help emulate experienced designers so as to accomplish heavy reduction in iterations by early exploration

Costly redesign needed due to late observation of mismatch effects

Manual design



Current Challenges


Propagation of Mismatch

Iref

Current mirror

Vb1

Vb2

Vb3

OpAmp

99 % falls in this range

actual pdf

*Worst-case propagation between blocks causes unrealistic accumulation of errors

*Designing while considering such large variations impossible in DSM

*Correlations between parameters accentuate this error

Bandgap reference circuit

Iref



Current Challenges


Fabrication accuracy cannot keep up with feature size shrinkage rate, as:

*Random effects do not scale proportional to parameter scaling

Wafer radius

tox (x40nm)

Wafer radius

tox (x4nm) newer technology

The Increasing Importance of Random Effects

*Mismatch groups closer than ever before, therefore: REs assume increased importance compared to previous technology

PVE

RE



Current Challenges


Modeling Mismatch Sources

Iref

Vb2 Vb2

Vb1

60 60

60 60

300 300

60

60

120

120

60

60

30

30300+2+1300+2+-2

300 303

*Process variations w/o mismatch tend to effect linearly; mismatch effects non-linearly

*Similar reasoning applies to other physical parameters of matched transistors

GOAL: predict effects of mismatch on high level circuit parameters

PVE and mismatch effects on circuit gain:WM1 WM2 GNominal :300 300 100PVE+RE w/o mismatch:303 303 102297 297 98PVE+RE with mismatch:303 300 99297 300 90

PVE RE PVE RE

Layout Optimizations -Effective for local variations, but of limited relevance to random variations

-Balancing interconnect between two transistors still an open issue

-Suffers linear optimization limitations as transistors rectangular, yet physical parameter distributions have curvesCommon centroid layout style

Mismatch Compensation MethodsCircuit Optimizations -Circuit specific and not easily

generalizable-Usually process variations compensated instead of REs

*Each method may require prediction of high level parameters, hence necessitating mismatch models

iso-parameter lines for a physical parameter such as tox

tox=4.0nm

tox=4.1nmtox=4.2nm

Previous Work on Mismatch Modeling

BSIM parameter based models [M. Ismail et. al., ISCAS, 1993]

-PCA used to assign weights, which represent a degree of influence to mismatch

Electrical and/or empirical parameter attributed models

[M. Pelgrom et. al., JSSC, 1989]

-first order Taylor expansion

Physics based models [Drennan et. al., IEDM, 1999]

-relates mismatch constituents to physical attributes such as W, L, tox,

VFB, μ0

Previous Work on Mismatch Modeling

Physics based models

- Current models overlook random effects and block communication

+ Mismatch is a physical phenomenon

BSIM parameter based models -Dependence between parameters considered only by using first order correlations-Parameter inaccuracies due to extraction from wafer magnified through PCA-Successful use of PCA in image processing stems from parameters being physical sources

Electrical and/or empirical parameter attributed models

-Errors due to first order Taylor expansion

-Pessimistic due to assumption of equal separation around nominal

Equal separation from nominal values?

Improved predictions?

Support for behavioral modeling?

-Need to consider physical parameter based modelingRealistic models?

Necessary Improvements to Mismatch Modeling Work

-Causes non-optimal (pessimistic) mismatch prediction, yet same direction deviations from nominal should also be accounted for

-Need to consider random effects both for manual design and CAD

-Need statistical and accurate estimation

Propagation between circuit blocks?

-Need efficient and accurate techniques for inter-block propagation

Meeting current mismatch modeling challenges necessitates:

-relating physical parameters to circuit parameters

-imposition of hierarchy on parameters

-measurement of the relationships between parameters

*dependence graph

*parameter levels

*sensitivities

Proposed Techniques

-reduction of correlations between parameters *heuristic approach capable of correlation handling

Level 0: NSS NSUB : physicalLevel 1: egap Cox : physical /electrical/mathematicalLevel 2: PHIms GAMMA : physical/electrical/mathematical . . Level n: CMRR : electrical/mathematical

Pi,n = f i (P1,0,P2,0, P3,1 …,Pj,n-1)

(n-1)’st level

j’th parameter

Levelization

All parameters can be written as functions of parameters from previous levels.

Classification of Parameters into Levels

gm

Independent Normal

Correlated?

pdf?Level1

Level4

Level0

Level0 parameters independent, have Gaussian pdf

Level Decomposition Example nVFBNSUBLW

Vth Cox

tox

ID

k Level2

Level3

Correlated?

pdf?

Correlated?

pdf?

Correlated?

pdf?

Connectivity Graphs

Sensitivity determination at each edge suffices to construct sensitivities between transitively connected nodes

Levels defined by maximum edge depth

Vth

VT0

NSUB

PHI

Vth=f3(PHI,VT0)Vth=f4(NSUB)

VT0=f2(PHI,NSUB)

PHI=f1(NSUB) L1

L0

L2

L3

SVth = SVth * SPHI + SVth * ( SVT0 + SVT0 * SPHI )NSUB PHI NSUB VT0 NSUB PHI NSUB

Bridging Physical Aspects to Circuit Parameters

circuit parameters

design parameters

SPICE parameters

L0

L1

L2

L3

L4

L5

L6

L7

L8

gm

CMRRrout

W LNSS T NSUB TOX

COX

GAMMA

PHI

egap

Vth

Id

PHIms

VFB

VT0

Connectivity Based Traversal-Proposed heuristic reduces the deteriorating effects of correlation in estimating an unknown sensitivity

Vth

VT0

NSUB

PHI

Vth=f3(PHI,VT0)Vth=f4(NSUB)

VT0=f2(PHI,NSUB)

VT0=f1(NSUB) L1

L0

L2

L3

SVth = SVth * SPHI + SVth * ( SVT0 + SVT0 * SPHI )NSUB PHI NSUB VT0 NSUB PHI NSUB

Proposed Methods for Various Design Steps

Manual Method

Simulation-based Method

Monte Carlo-based Method

Pdf from previous block included

*Early design estimation methods (manual&simulation-based) save valuable time by decreasing iterations

*Accurate simulations (simulation and MC-based) avoid lengthy design house – foundry iterations

Provides a pdf instead of worst-case values

Random effects considered

Mismatch EDA Tool Requirements

Manual design


SPICE simulations


Optimizations


Manual mismatch prediction method

Accurate simulation for mismatch

Mismatch Predictive models

Manual design


SPICE simulations


Optimizations


Manual method

Simulation and MC-based methods

Manual and MC-based methods

Mismatch EDA Tool Requirements

Mismatch Estimation Techniques

Manual

Simulation based

Monte Carlo based

Common Goal: Want to know the pdf of a circuit parameter

Estimation based on circuit design formulas

More accurate estimation based on simulations

Promising for test, diagnosis and behavioral modeling

*Methods cover a spectrum of design needs

*Improvement attained at the expense of considerable increase in time overhead

Mismatch cannot be effectively handled in terms of worst-case limits, as the pessimistic bounds do not consistently coincide

Can be automated using symbolic analyzers

ref

current mirror

M1 M2

1Pi + 1Pi-RE 2Pi + 2Pi-RE

2dep

Overview of the Manual Method

-Use analytic formulas and connectivity graphs to find sensitivities of each edge-Use these sensitivities to construct sensitivity of circuit parameters to physical parameters-Estimate pdf of the circuit parameter

M3

3Pi + 3Pi-RE

3dep

Idep Lref

. Wdep VGSdep- VT0

dep-γdep

.( 2PHIdep-VSBdep- 2PHIdep)

Iref Ldep

. Wref VGSref - VT0

ref -γref

.( 2PHIref -VSBref - 2PHIref)

How is pdf propagation achieved?

Signal from previous block (e.g. bandgap reference) also included

Application of the Manual Method

G

n1VFB1NSUB1L1W1

Vth1 Cox1

tox1

ID1

k1

gm1

n2VFB2NSUB2L2W2

Vth2 Cox2

tox2

ID2

k2

gm2

-Connectivity graph duplicated for each transistor in the mismatch group enabling the use of accurate symbolic formulas and accounting REs-Sensitivities calculated for each edge

S Ggm2

S ID2

gm2

NSUB1 gm1 ID1 k1 k1 n1 SG

= SG * ( Sgm1 * SI

D1 + Sgm1 ) * Sk1

-Other sensitivities calculated using connectivity based traversals


G

n1VFB1NSUB1L1W1

Vth1 Cox1

tox1

ID1

k1

gm1

n2VFB2NSUB2L2W2

Vth2 Cox2

tox2

ID2

k2

gm2

-Connectivity graph duplicated for each transistor in the mismatch group enabling the use of accurate symbolic formulas and accounting REs-Sensitivities calculated for each edge

-pdf of gain estimated while correlation effects substantially eradicated

S Ggm2

S ID2

gm2

NSUB1 gm1 ID1 k1 k1 n1 SG

= SG * ( Sgm1 * SI

D1 + Sgm1 ) * Sk1

-Other sensitivities calculated using connectivity-based traversals


G

n1VFB1NSUB1L1W1

Vth1 Cox1

tox1

ID1

k1

gm1

n2VFB2NSUB2L2W2

Vth2 Cox2

tox2

ID2

k2

gm2

* Independent probability distributions assumed physical parameters

* μ and σ of highest level parameter estimated using connectivity graphs. Connectivity based traversal substantially reduces correlation effects

σG = Σ SG* σPi

μG = Σ SG* μPi

where Pi is ith physical parameter

μi σi

μi σi

gm2

SGgm1

S ID2

gm2 ID2

gm2

ID2

Simulation Method*Use direct simulation to find sensitivities of circuit parameters to physical parameters for improved accuracy

G

n1VFB1NSUB1L1W1 tox1n2VFB2NSUB2L2W2 tox2

Vth1 Cox1

ID1

k1

gm1

Vth2 Cox2

ID2

k2

gm2

*Simulator-aided version of the manual method

Simulation Method*Use direct simulation to find sensitivities of circuit parameters to physical parameters for improved accuracy

*Simulator-aided version of the manual method

G

n1VFB1NSUB1L1W1 tox1n2VFB2NSUB2L2W2 tox2

*Improving over earlier physics based prediction methods:

SGtox2

Accounts for correlations from previous circuit blocks

Differential stage biased with current mirror

Iref

G1

Monte Carlo-Based Method*Assign independent physical parameter distributions to mismatch groups

*Activate groups separately; each group assigned own SPICE parameters

*Discard dominated groups; repeat for combinations of dominant groups to estimate pdf of a high level parameter

G2

G3

Experimental Verification-Use direct simulation to find sensitivities of circuit

parameters to physical parameters for improved accuracy

ID1

M1

ID2

pdf from previous block included

sim. methodMC results

Comparison of the Manual method with MC Simulations

bin probability vs. currentM2

S id2 id1

S id2 L1

0.7440 -0.6300 0.3333 -0.1780 -0.0400 0.1013 0.8600

S id2 W1

S id2 TOX1

S id2 UO1

S id2 XJ1

S id2 NCH1

S id2 L2

-0.7860 0.6480 -0.3466 0.1780 0.0433 -0.1013

S id2 W2

S id2 TOX2

S id2 UO2

S id2 XJ2

S id2 NCH2


Iref

G1

pdf of gain

Simulation Results


Iref

G2

G3

pdf of gain

Simulation Results


Iref

Simulation Results

G2

G3

G1

High level circuit parameters may not exhibit a Gaussian-like pdf when physical input parameters are assigned independent Gaussian distributions.

pdf of gain

Sense Amplifier

CLK M2

M3 M4

M5 M1

Dependence of gain to variations in M4 @800MHz

Higher level circuit parameters and large variations indicate highly non-linear relationships

Gain vs NCH

Gain vs TOX

Gain vs

W

Insights for Future Modeling

Sense Amplifier

CLK M2

M3 M4

M5 M1

Dependence of gain to variations in M3 @800MHz

Gain vs NCH

Gain vs TOX

Gain vs

W

Further improvements on Manual and simulation-based estimation methods include optimizations for larger perturbations and their effect on higher circuit parameters

Insights for Future Modeling

Concluding Remarks-Random effects involved in mismatch emphasized

-Accurate conveying of mismatch information through connectivity-based traversals from transistor level to high level circuit design parameters presented

-A manual mismatch prediction method discussed

-Simulation and Monte Carlo-based mismatch measurement methods outlined

-Conveying mismatch information between circuit blocks as a pdf signal introduced

Rasit Onur Topaloglu and Alex Orailoglu {rtopalog | alex}@cse.ucsd.edu University of California at...

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