Proposal for all-graphene monolithic logic circuitsJiahao Kang, Deblina Sarkar, Yasin Khatami, and Kaustav Banerjee

Citation: Applied Physics Letters 103, 083113 (2013); doi: 10.1063/1.4818462 View online: http://dx.doi.org/10.1063/1.4818462 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/103/8?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Thermoelectric effect in a graphene sheet connected to ferromagnetic leads J. Appl. Phys. 112, 073712 (2012); 10.1063/1.4757947 Transport in quantum spin Hall phase of graphene nanoribbons J. Appl. Phys. 112, 063713 (2012); 10.1063/1.4754427 Coherent transport of armchair graphene constrictions J. Appl. Phys. 107, 103706 (2010); 10.1063/1.3391273 Electron transport of folded graphene nanoribbons J. Appl. Phys. 106, 103714 (2009); 10.1063/1.3261757 Modeling charge transport in graphene nanoribbons and carbon nanotubes using a Schrödinger-Poisson solver J. Appl. Phys. 106, 024509 (2009); 10.1063/1.3174430

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Proposal for all-graphene monolithic logic circuits

Jiahao Kang, Deblina Sarkar, Yasin Khatami, and Kaustav Banerjeea)

Department of Electrical and Computer Engineering, University of California, Santa Barbara,California 93106, USA

(Received 4 June 2013; accepted 28 July 2013; published online 22 August 2013)

Since the very inception of integrated circuits, dissimilar materials have been used for fabricating

devices and interconnects. Typically, semiconductors are used for devices and metals are used for

interconnecting them. This, however, leads to a “contact resistance” between them that degrades device

and circuit performance, especially for nanoscale technologies. This letter introduces and explores an

“all-graphene” device-interconnect co-design scheme, where a single 2-dimensional sheet of

monolayer graphene is proposed to be monolithically patterned to form both active devices (graphene

nanoribbon tunnel-field-effect-transistors) as well as interconnects in a seamless manner. Thereby, the

use of external contacts is alleviated, resulting in substantial reduction in contact parasitics.

Calculations based on tight-binding theory and Non-Equilibrium Green’s Function (NEGF) formalism

solved self-consistently with the Poisson’s equation are used to analyze the intricate properties of the

proposed structure. This constitutes the first NEGF simulation based demonstration that devices and

interconnects can be built using the “same starting material” – graphene. Moreover, it is also shown

that all-graphene circuits can surpass the static performances of the 22 nm complementary metal-oxide-

semiconductor devices, including minimum operable supply voltage, static noise margin, and power

consumption. VC 2013 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4818462]

Graphene-based electronics has drawn tremendous

attention since its discovery in 2004.1 Graphene is the first

thermodynamically stable two-dimensional (2D) material

that is composed of a single layer of carbon atoms arranged

in a hexagonal lattice (Figure 1(a)) with zero bandgap (Eg)

(Figure 1(b)). Lithographically narrowed graphene (graphene

nanoribbon (GNR)) exhibits high potential for building

energy efficient devices such as GNR tunneling field effect

transistors (GNR-TFETs)2–4 because of its direct Eg (Figure

1(c)) and unique Eg tunability property via lithographic con-

trol of its width.5–9 Graphene has also been proposed as a

potential candidate to replace copper for next-generation

global interconnects due to its patternability and current-

carrying capacity.8–11 While separate analysis of GNR-based

devices and graphene interconnects have been reported in

the literature,2–11 the real benefits can be harvested through

an integrated device-interconnect co-design scheme.

In this paper, the prospects of “all-graphene” circuits

(Figures 1(d)–1(f)) are explored and evaluated. In such design

scheme, both devices (based on GNR-TFETs) and intercon-

nects (based on wider graphene ribbons) are proposed to be

concurrently fabricated by monolithically patterning a single

sheet of graphene, thereby significantly simplifying the fabri-

cation process. Moreover, this scheme of circuit design does

not require local interconnects made of a different material to

connect the devices within logic gates. Hence, the proposed

“all-graphene” circuit can lead to substantial reduction in con-

tact resistance and could potentially open up exciting pros-

pects for designing ultra-dense and thin integrated circuits

with unprecedented performance and energy-efficiency, and

subsequently higher reliability. It is to be noted that this work

is based on a paradigm integrating GNR-TFETs and graphene

interconnects on a single layer graphene and is not to be con-

fused with a previous work, which reported a circuit where

graphene FET and metal-based inductors were integrated12

FIG. 1. (a) The atomic structure of graphene. Armchair (ac) and zigzag (zz)

are two different chiralities; (b) band structure of graphene; (c) band structure

of armchair-GNR (ac-GNR); (d–f) Schematics showing proposed fabrication

steps of an “all-graphene” circuit (inverter chain): (d) monolayer graphene

sheet; (e) graphene interconnects and GNRs patterned by lithography; source

and drain regions are doped; (f) all-graphene circuit after deposition and pat-

terning of metal and dielectric; (g) Circuit schematic of (f). Inverter 2 is

double-sized using two GNR channels (hence fan-out of Inverter 1¼ 2).a)Electronic Mail: kaustav@ece.ucsb.edu

0003-6951/2013/103(8)/083113/5/$30.00 VC 2013 AIP Publishing LLC103, 083113-1

APPLIED PHYSICS LETTERS 103, 083113 (2013)

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using local metal interconnects and hence, cannot offer the

unique advantages of the proposed “all-graphene” circuit.

Figures 1(d)–1(f) show an all-graphene inverter chain

design together with its proposed fabrication process in 3

steps: (d) synthesis of monolayer graphene sheet; (e) pattern-

ing of the uniform graphene sheet and doping of GNRs to re-

alize graphene interconnects and GNR devices; (f) depositing

and patterning of gate dielectric, gate metal, isolation oxide,

via, pads and external interconnects.

The recent demonstration of graphene patterning down to

sub-10 nm dimensions with atomically smooth edges via both

top-down13,14 and bottom up15,16 processes lend sufficient credi-

bility to the feasibility of such approach. The doping of GNRs

can be achieved by chemical doping (via edge doping,17 interca-

lation doping,10 and defects18), substrate doping19 and electro-

static doping,20 of which substrate and electrostatic methods are

more controllable in small GNR areas. Hence, in this work, dop-

ing is considered to provide uniform charges in source and drain

regions and quantified as Fermi potential (jeUPj and jeUNj),defined as the energy difference between midgap energy Ei and

Fermi level EF (will be shown later, in Figure 2(b)).

Note that the widths of the channel regions in n- and

p-type devices are made equal in order to obtain the same

Eg. Hence, the sizing of all-graphene circuits is achieved by

using multiple GNR channels, as shown in the multi-channel

GNR-TFETs in Inverter 2 (Figures 1(f) and 1(g)). Because

of the bipolar behavior of TFETs (electron-hole duality21),

n- and p-type TFETs have almost the same tunneling cur-

rents, thereby n- and p-type devices can be made with identi-

cal sizing (unlike CMOS).

To understand the transport across various wide-narrow

graphene interfaces and GNR-TFETs, Non-Equilibrium

Green’s Function (NEGF) formalism22 along with tight-

binding (TB) modeling of graphene/GNR band structures is

employed. TB approach can provide consistent accuracy for

band structure of armchair-GNR (ac-GNR, chirality shown

in Figure 1(a)).23 Hence, the simulations in this work were

performed with the assumption of smooth ac-GNR edges. It

is to be noted that Eg modulation for zz-GNRs has also been

observed in experiments for sub-10 nm widths,24 and hence,

this work can be extended to any chiralities. Self-consistent

solution of Poisson’s equation (PE) and NEGF is used to

accurately account for the electrostatics. Transport in GNR-

TFETs, interconnects, and across interfaces are solved sepa-

rately in different NEGF modules (real space22 for intercon-

nects and interfaces, and mode space25 for GNR-TFETs) in

self-consistent NEGF-PE iteration loops. Subsequently, cir-

cuit performances are evaluated based on the lookup tables

from the simulation results. Comparisons are then made with

22 nm-CMOS high-performance (HP) and low-power (LP)

models.26

At first, the active devices (TFETs) in the all-graphene

circuit are designed. The GNR-TFETs are essentially reverse

biased P(þ)-i-N(þ) and N(þ)-i-P(þ) type source-channel-drain

structures where the source and drain regions are doped while

the gate-controlled channel remains intrinsic. GNR-TFETs

with symmetrically doped source and drain exhibit ambipolar-

ity (remain ON for both high and low gate voltages (VGS, or

VG if source is grounded)), which is detrimental for some

circuit applications. Asymmetric (unequal) doping in source

and drain of GNR-TFET25 can be used to reduce ambipolar-

ity. Hence, in this work, the n-type TFETs (NTFETs) with

Pþ-i-N doping and p-type TFETs (PTFETs) with Nþ-i-P dop-

ing are used. The structure of such an NTFET is illustrated in

the inset of Figure 2(a). The output characteristics (VGS-IDS

curve) of the NTFET (blue) is plotted in Figure 2(a) and com-

pared with that of a symmetrically doped GNR-TFET (red).

The TFETs consist of ac-GNR with NW¼ 40 (width of GNR

WGNR¼ 5 nm), Eg¼ 0.29 eV, channel length Lch¼ 22 nm, and

single gate with 1.2 nm-thick HfO2. Gate leakage is ignored.

Drain to source bias is VDS¼ 0.2 V. Asymmetric doping indu-

ces an OFF state around VGS� 0. Doping is jeUPj ¼ 0.24 eV

and jeUNj ¼ 0.11 eV. ION/IOFF for Pþ-i-N is 1.6� 103. The

band diagrams in various regions of input characteristics are

shown schematically in Figures 2(b)–2(d).

According to Figure 2(b), the interaction between doping

and supply voltage (VDD) is derived based on the criteria that

an ideal NTFET should be fully ON (when VG equals VDD) or

fully OFF (when VG is 0) under any VDS (0 to VDD). Figure

2(b) shows that in the OFF state, Ev,P�Ec,i, where Ec is the

bottom of the conduction band; Ev is the top of the valence

band; subscripts i, P, and N are for intrinsic, p-type, and n-type

regions. Another ON state where tunneling occurs between

channel and drain (Figure 2(d)) should be prevented by reduc-

ing the doping of drain so that Ev,i�Ec,N. Ech is defined as the

channel potential, which is Ech¼Ei,i� (�eVG), where

e¼þ1.6� 10�19 C. Since Ech¼ 0 eV in OFF state (VG¼ 0 V),

Ev,i�Ec,N and Ev,P�Ec,i can be expanded to

Ech � Eg=2 � EF;N � eVDD � je/Nj þ Eg=2 (1)

EF;P þ je/Pj � Eg=2 � Ech þ Eg=2; (2)

respectively, where jeUPj and jeUNj refer to the Fermi poten-

tials. EF,P is chosen as the 0 eV level. In the ON state,

Ech¼�eVDD and Ev,P�Ec,i, so that

EF;P þ je/Pj � Eg=2 � eVchþEg=2: (3)

From Eqs. (1)–(3), the interaction between doping and

VDD is roughly,

FIG. 2. (a) VGS-IDS curves of Pþ-i-Nþ and Pþ-i-N GNR-TFETs; Inset figure

in (a) shows the device structure; (b–d) Band diagrams of (b) OFF state; (c)

ON state and (d) ON state with tunneling at drain-channel junction. The

VGS-IDS points corresponding to (b–d) are marked in (a).

083113-2 Kang et al. Appl. Phys. Lett. 103, 083113 (2013)

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Eg � je/Pj � eVDD � Eg � je/Nj: (4)

For instance, for the asymmetrically doped GNR-TFET

simulated in Figure 2, a rough range of 0.05–0.2 V for VDD

can be determined.

Limitation of VDD and doping of an isolated TFET was

presented as Eq. (4). However, in the “all-graphene” circuit,

parameters become more constrained when the interfaces

between devices and interconnects are considered. In a typical

PTFET/NTFET stack, which is required for designing com-

plementary digital gates, drain-interconnect-drain (D-i-D)

structures become relevant (Figure 3(a)). The D-i-D region in

Figure 3(a) contains two doped drain regions and a graphene

interconnect region.

To evaluate the properties of the D-i-D regions, a small

D-i-D region is first simulated by real space NEGF for GNRs

with NW¼ 6 (WGNR¼ 0.8 nm) and an infinite width graphene

interconnect with 20 C atoms (2.1 nm) along the length

direction (with ac-chirality). Note that by TB approach, this

chirality and dimension retain the band structure of gra-

phene. The Fermi potential of drain (jeUP,Nj) is varied as 0.8,

0.6, and 0.5 eV.

Figures 3(b) and 3(d) show the band diagrams and local

density of states (LDOS) of this region and Figures 3(c) and

3(e) show their corresponding transmission spectrum (T(E)).

Its I-V characteristics are shown in Figures 3(f) and 3(g).

When drain regions are highly doped (Figure 3(b), large

jeUP,Nj ¼ 0.8 eV), the current is high due to the tunneling

window (TW) shown in Figure 3(c). When drain regions

have low doping (Figure 3(d)), the current is limited, since

the TW vanishes (Figure 3(e)).

Hence, when designing all-graphene circuits, doping is

limited by both Eq. (4) (upper bound) and the transmission

through the D-i-D structure (lower bound).

An inverter chain based on the all-graphene design is

shown in Figure 1(f). According to the analysis and simulations

above, the size parameters are optimized to: WGNR� 5 nm,

which allows a reasonable bandgap Eg� 0.29 eV; channel

length Lch¼ 22 nm, which is designed for comparison with

CMOS; length and width of interconnect regions are large

enough (Xint�Yint� 30 nm� 30 nm) (Figure 1(f)) to ensure

Eg¼ 0 and low resistance in graphene.8 TFETs are controlled

by single gates with 1.2 nm dielectric, where the permittivity

eox¼ 16. Doping values are optimized as jeUPj ¼ 0.24 eV and

jeUNj ¼ 0.12 eV for WGNR¼ 5 nm, which satisfy the limitation

from Eq. (4) and provide considerably high current through the

D-i-D region (I-V curves shown in Figure 3(g)).

Since the load inverter (Inverter 2) does not contribute

to the static performances, the following discussion focuses

on a single all-graphene inverter for simplicity. The working

processes of an all-graphene inverter are described with band

diagrams in Figure 4. Dashed lines are bands before charg-

ing/discharging (low-to-high/high-to-low transition) while

solid lines are charged/discharged bands. When toggling, the

output node (a D-i-D region including graphene interconnect

and drain regions of both NTFET and PTFET) is charged or

discharged by band-to-band tunneling currents at source-

channel interfaces. Subscripts i, P, and N for Ec and Ev are

omitted for simplicity, and EFS and EFD represent Fermi lev-

els for source for drain, respectively. When charging (or dis-

charging), the bands of the D-i-D region are shifted due to

the changing of EF of the output node (-eVout).

FIG. 3. (a) Schematic showing the simulated drain-interconnect-drain

region; (b, d) Local density of states (LDOS) and band diagrams of the simu-

lated region in (a) with: (b) high doped drains (jeUP,Nj ¼ 0.8 eV) and (d) low

doped drains (jeUP,Nj ¼ 0.5 eV). (c, e) Transmission spectrum (T(E)) of (b)

and (d), respectively. TW is transmission window. (f, g) I-V curves of D-i-D

regions for different drain doping levels: (f) NW¼ 6; (g) NW¼ 40, where NW

is the number of C atoms along the width of GNR. VF and IF denote the volt-

age and current from PTFET drain to NTFET drain, respectively. jeUP,Nj is

the Fermi potential in the drain regions. Note that both jeUP,Nj and VF affect

TW.

FIG. 4. Band diagram of an inverter showing (a) rising of output (Vout rises

from low to high; dashed lines and solid lines represent bands before and af-

ter rising of output, respectively; and (b) falling of output (Vout falls from

high to low; dashed lines represent bands before discharging and solid lines

are discharged bands) of the output node (Vout); red arrows represent current

directions.

083113-3 Kang et al. Appl. Phys. Lett. 103, 083113 (2013)

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Let the channel size be WGNR�Lch¼ 5 nm� 22 nm.

Source and drain lengths are set to 18 nm. Inverter voltage

transfer curves (VTCs) for different VDD are obtained by cir-

cuit level simulations based on lookup tables (I-V data for

NTFETs and PTFETs, which are calculated by self-

consistent NEGF-PE iteration loops). In Figure 5(a), solid

lines represent all-graphene inverters and dashed lines repre-

sent 22 nm-CMOS LP model with minimum sizes. Inset

plots are zoomed in around Vin� 0–0.1 V. Normalized static

noise margins (SNM/VDD) and gain (defined in Figure 5(b))

vs. VDD of CMOS and all-graphene inverters are listed in

Table I. SNMs shown are all low-noise-margins (¼NML

¼VIL-VOL) while high-noise-margins (¼NMH¼VOH-VIH)

are no less than NML, where VIH, VIL, VOL, and VOH are

defined in Figure 5(b).

When VDD� 0.2 V, output current Iout (the current flow-

ing to output node) is always �103 times the leakage (tunnel-

ing) current (Ileak) as shown in Figure 6. However, if

VDD> 0.2 V, when input is low (<0.05 V), PTFET is ON but

NTFET is not completely OFF due to ambipolar behavior,

which is an ON state as shown in Figure 2(d). Hence, Vout is

pulled down to 0.2475 V as shown in the inset plot of Figure

5(a). Thereby, the inverter suffers from an increased Ileak,

which is nearly a decade higher than expected, resulting in a

decade lower Iout/Ileak ratio, as shown in Figure 6. This effect

reflects the upper bound for VDD in Eq. (4). On the other

hand, a circuit level lower bound of VDD appears around

VDD� 0.05 V, where the SNM and jGainj are unacceptably

low (Table I).

The static power consumption for the all-graphene in-

verter is shown for different values of WGNR, and compared to

the 22 nm CMOS inverters. It can be observed that the static

leakage power Pstat of all-graphene inverter (WGNR¼ 5 nm) is

similar to that of 22 nm-CMOS HP model (Figure 7) with

default threshold voltages. However, by decreasing WGNR, Eg

is increased, and Ileak is reduced significantly resulting in

much lower Pstat than CMOS.

In conclusion, band gap tuning induced by lithographic

sketching of narrow/wide patterns on a single 2D monolayer

graphene is proposed for exploring “all-graphene” ultra

energy-efficient logic circuits based on GNR-TFETs. The pro-

posed scheme is unique to graphene since it can be employed

to fabricate both active and passive devices from the “same

material” in a seamless manner. It is shown that the “all-

graphene” circuit design scheme exhibits superior static per-

formances with up to 1.7X higher SNMs and 1–2 decades

lower static power consumption than that of LP as well as HP

22 nm-CMOS technology. Limitations on VDD scaling are

estimated theoretically and due to the smaller Eg of GNR, the

minimum achievable VDD is shown to be lower (0.1–0.2 V)

than that of 22 nm-CMOS, which performs poorly when VDD

decreases to �0.4 V. Combined with the superior thermal,

mechanical, and reliability properties of graphene, the “all-

graphene” design scheme is envisioned to provide an attrac-

tive pathway for future ultra-dense 2D-electronics. Moreover,

due to the flexible and transparent nature of graphene, such

scheme could pave the way for a completely new generation

of “wearable” and “invisible” electronics.

FIG. 5. (a) Inverter VTCs for all-graphene circuits and 22 nm-CMOS under

different VDD. Inset plot is zoom of (a) at Vin� 0–0.1 V. (b) definitions of

gain, VIH, VIL, VOL, and VOH for inverters.

TABLE I. Normalized SNM (SNM/VDD) and inverter gain vs. VDD. Note:

When jGainj< 1, SNM does not exist according to the definition in Figure 5(b).

22 nm-CMOS All-graphene

VDD (V) SNM/VDD jGainj SNM/VDD jGainj

0.25 0.336 3.81 0.390 4.65

0.20 0.290 2.59 0.375 3.87

0.15 0.205 1.46 0.348 2.95

0.10 … <1 0.290 1.99

0.05 … <1 … <1

FIG. 6. Plot of output current Iout (the current flowing to output node) vs.

VDD and static leakage current Ileak vs. VDD.

FIG. 7. Static leakage power for 22 nm all-graphene inverters with different

widths, in comparison with 22 nm-CMOS inverters with default threshold

voltages, plotted as a function of VDD.

083113-4 Kang et al. Appl. Phys. Lett. 103, 083113 (2013)

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This work was supported by the National Science

Foundation, Grant No. CCF-1162633.

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