Project D1427:Stand Alone FPGA Programmer

Midterm presentation

7/1/09Supervisor: Mony Orbach

Students: Shimrit Bar Oz

Avi Zukerman

High Speed Digital Systems Lab

Agenda

• Project characterization.• Work done since characterization.• Technical description.• User interface.• Blocks diagram.• .hexout format.• Test case.• Project’s tasks.• Schedule.

Project characterization

• Design a system for programming Altera FPGA directly from a PC.

• The system gets gate level burn ready software from PC in hexout format.

• Translate to JTAG format.• Burn the software onto an Altera FPGA.

hexout format JTAG formatFPGA

programmer

Work done since characterization

• Understanding the system requirements and choosing hardware.

• Learning the Quartus burn file formats.

• HDL designer and Quartus work environment.

• The project’s test case had been preformed on full Quartus flow.

Technical description

• The system is uses the MMC experiment card, which has a DLP for USB communication and Altera Cyclone FPGA.

• The system also includes software driver.

DLP CycloneUSB JTAG output

JTAG inputs

MMC experiment card

Driverhexout input

User interface

• The user interface will be a command line software.

• The command line will include the input which is a valid .hexout file.

• The software will output success message or failure errors.

Blocks diagram

• Software block transmits the .hexout file one Byte at a time to the DLP.

• Receiver block receives each byte from the DLP and store it.

• Transmitter block transmits the Byte bit by bit using JTAG format to the target FPGA.

Receiver

block

Transmitter

blockBinary ByteJTAG output

Software

blockhexout Byte

JTAG

output

transmit transmit

acknowledge acknowledgeacknowledge

.hexout format

• The input to the system should be a completely burn ready program from Quartus.

• The format usually used by Quartus is .sof or .pof.

• Quartus can convert each of the above into an .hexout format.

Test case

• The card from the digital system experiment has been chosen as a test case.

• The test case is a simple program that changes the card’s display.

• The test case is build from a state machine and a truth table.

• The test case had been completed successfully using full Quartus flow and .sof format.

Project’s tasks

• Block level design.

• VHDL coding of logical unit.

• C coding of software driver.

• Debugging.

• Create connector for JTAG outputs.

• Test case.

• Summary and final report.

Schedule

Schedule