Professional development tools

for RISC-V

Thomas Andersson, Product Manager

Agenda

• RISC-V introduction

• IAR Embedded Workbench for RISC-V– Compiler

• Optimizations

– Debug• I-jet

– Code quality and Safety• Static analysis

• Certified toolchain

RISC-V introduction

RISC-V introduction

• RISC-V is an open ISA that is maintained by the RISC-V

Foundation (https://riscv.org)

• The RISC-V Foundation, is a non-profit corporation is

controlled by its members

• Members of the RISC-V Foundation have access to and

participate in the development of the RISC-V ISA

specifications and related HW / SW ecosystem

RISC-V introduction

• To use the ISA you do not need to be a member

• Usage of the RISC-V trademark or the RISC-V logo is only permitted under the license granted within the RISC-V Foundation Membership Agreement

• Members

– The foundation now have well over 100 member organizations

– https://riscv.org/membership/?action=viewlistings

RISC-V introduction

• Completely open ISA that is freely available to academia and

industry

• Avoids “over-architecting" for a particular microarchitecture style

or implementation technology (e.g. full-custom, ASIC, FPGA), but

which allows efficient implementation in any of these

• Support for the revised 2008 IEEE-754 floating-point standard

• Supporting extensive user-level ISA extensions and specialized

variants

RISC-V introduction

• Both 32-bit and 64-bit variants for applications, operating system

kernels, and hardware implementations

• Optional variable-length instructions to both expand available

instruction encoding space and to support an optional dense

instruction encoding for improved performance

– Reserved opcodes allow for user extensibility

of the architecture without breaking standard

extensions or incurring software fragmentation

IAR Embedded Workbench for

RISC-V

Compiler

• Proprietary design based on over 35 years of experience

• Based on a platform that are common between different targets to handle global optimizations etc.

• Target unique backend for specific adaptations and optimizations

• RISC-V specifics

– Primary focus will be on adding standard extensions

– Initial prioritization is on code size

IAR C/C++ Compiler

The linker can

remove

unused code

Major functions of the

optimizer can be

controlled individually

Balance between size

and speed by setting

different optimizations

for different parts of the

code

Multi-file compilation allows the

optimizer to operate on a larger

set of code

Option to

maximize

speed with no

size

constraints

Well-testedCommercial test suites

• Plum-Hall Validation test suite

• Perennial EC++VS

• Dinkum C++ Proofer

In-house developed test suite

>500,000 lines of C/C++ test

code run multiple times

• Processor modes

• Memory models

• Optimization levels

Language standards• ISO/IEC 14882:2015

(C++14, C++17)

• ISO/IEC 9899:2012 (C11)

• ANSI X3.159-1989 (C89)

• IEEE 754 standard for

floating-point arithmetic

Multiple levels

of

optimizations

for code size

and execution

speed

Performance (1)

• Our main focus have always been to

supply the best code size and speed

on the market

• The RISC-V ISA is clean and straight

forward and that is probably one of

the major factors that have made it

successful

Performance (2)

• Compared to more complex instruction sets RISC-V have some challenges especially when it comes to size

– Arithmetic with higher resolution than the natural data size yields larger code

– Absence of carry flags is another example

• Speed

– When it comes to speed RISC-V compete well

• Our initial target will be reduced size for smaller embedded applications

Object Code

OptimizationsC Source

Parser

Intermediate Code High-Level Optimizer

Code Generator

Target CodeLow-Level

Optimizer

Assembler

Compiler

LW A0,-0x0(GP)

C.ADDI A0,-0xF

SW A0,-0x4(GP)

=

–

15y

x

x = y - 15;Function

inlining

Dead code

elimination

Loop

unrolling

Peephole

Crosscall

Scheduling

01001000111001101001

Linker

Link time

optimizations

Optimization settings

• Available high level settings

– Minimize code size (“size”)

– Minimize execution time (“speed”)

– Low, Medium, High

– Enable individual transformations

• Use highest settings!

• Settings only approximate

– There are always heuristics involved when doing optimizations so always make

sure to test several settings and check the results

– Enable the productive transformations

Speed, size or both?

Optimization

Common sub-expressions Speed ↑ Size ↓

Loop unrolling Speed ↑ Size ↑

Function inlining Speed ↑ Size ↑

Code motion Speed ↑ Size →

Dead code elimination Speed → Size ↓

Static clustering Speed ↑ Size ↓

Instruction scheduling Speed ↑ Size →

Peephole Speed ↑ Size ↓

Effect

Demonstration

Debug

• IAR Embedded Workbench for RISC-V will have a fully integrated debug solution

• This will reuse the C-SPY debugger interface that is used in many of our other products– This includes the possibility to write debug macros etc.

• Probes– Our I-jet probes will support RISC-V

– Support for major 3rd party probes will also be added

IAR C-SPY debugger overview

IAR Embedded

WorkbenchC-SPY

Simulator

driverSimulator

I-jet

driverI-jet

Target

HW

IAR C-SPY Debugger

3rd-party

driver

JTAG

Emulator

Target

HW

SDK

interface

Target system with application SW

IAR systems

3rd-party

RTOS

Awareness etc.

Integrated profiling tools

Function profiling • Based on simulator, sampled trace

or full trace

• Execution time per function

• Select time interval

Timeline window shows the

application’s profileInterrupt log, Data log, Event log, Call stack

Code coverage analysisWhich code has been executed?

Stack analysiscalculates maximum stack usage, helps find the optimal stack size, and checks stack integrity at runtime to detect overflow

Power debugging

Work fast, sleep a lot!

• Optimizations

• Efficient code

Detailed power logsPower breakpoints

Function-level

power profiling

• Integrated measuring of power consumption correlated to the

source code

• Tune the application to minimize power-consuming use of

hardware resources

• Enabled by I-jet or other hardware with power debugging support

I-jet in-circuit debugging probe• Supports RISC-V and ARM7/ARM9/ARM11 and Arm Cortex-M/R/A cores

• Hi-speed USB 2.0 interface (480Mbps)

• Target power of up to 400mA can be supplied from I-jet with overload

protection

• Target power consumption can be measured with ~200µA resolution at

200kHz

• JTAG and Serial Wire Debug (SWD) clocks up to 32MHz

(no limit on the MCU clock speed)

• Support for SWO speeds of up to 60MHz

• Unlimited flash breakpoints (To be added for RISC-V)

Demonstration

Code quality and

Functional Safety

CWE (the Common Weakness Enumeration): http://cwe.mitre.org/

CERT (Computer Emergency Response Team): http://www.cert.org/

Complete static analysis tool fully integrated in IAR Embedded Workbench

C-STAT static analysis

Intuitive and easy-to-use settings with

flexible rule selection

Support for export/import of selected

checks

Support for command line execution

Extensive and detailed documentation

List of messages and data base file

available

Checks compliance with MISRA C:2004,

MISRA C++:2008 and MISRA C:2012

Includes ~250 checks mapping to

hundreds of issues covered by CWE and

CERT C/C++

Functional safety

• Tools certified for functional safety

- Exceedingly well-tested

- Help you to focus on just your application

- Help speed the path to your certification

• Code analysis tools help prove your design’s

safety and integrity

Validated product versions

Validated version: IAR Embedded

Workbench for EWXXXFS x.xx.xValidated version y.yy

Validated service packs Validated service packs

Non-validated feature

releases x.xx.x

• For a certified product, a new certified version is released approximately

every 12-18 months

• A certified version is considered a ”frozen” version, on which bug fixes

are applied in terms of validated service packs

• No new product features are added to a certified version or the

corresponding service packs

Standards:IEC 61508

ISO 26262

EN 50128

IEC 62304

Solutions for safety-critical applications

Certified toolchain

A special functional safety edition of

IAR Embedded Workbench

Simplified validation

Functional Safety certificate from TÜV SÜD

Safety report from TÜV SÜD

Safety guide

Guaranteed support through the product life

cycle

Prioritized support

Validated service packs

Regular reports of known problems

Thank you for your attention!

www.iar.com