Presenting: Itai Avron Supervisor: Chen Koren Final Presentation Spring 2005 Implementation of...
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![Page 1: Presenting: Itai Avron Supervisor: Chen Koren Final Presentation Spring 2005 Implementation of Artificial Intelligence System on FPGA.](https://reader035.fdocuments.us/reader035/viewer/2022070412/56649d4e5503460f94a2e1b6/html5/thumbnails/1.jpg)
Presenting: Itai Avron
Supervisor: Chen Koren
Final Presentation
Spring 2005
Implementation of ArtificialIntelligence System on FPGA
![Page 2: Presenting: Itai Avron Supervisor: Chen Koren Final Presentation Spring 2005 Implementation of Artificial Intelligence System on FPGA.](https://reader035.fdocuments.us/reader035/viewer/2022070412/56649d4e5503460f94a2e1b6/html5/thumbnails/2.jpg)
Project Goals
• Creating a VHDL design of a Neural Network
• Comparison Vs. software implementation (Matlab)
![Page 3: Presenting: Itai Avron Supervisor: Chen Koren Final Presentation Spring 2005 Implementation of Artificial Intelligence System on FPGA.](https://reader035.fdocuments.us/reader035/viewer/2022070412/56649d4e5503460f94a2e1b6/html5/thumbnails/3.jpg)
Background• Neural Network is a Learning Machine
• It is build from Neurons (Perceptrons), which holds the knowledge of the system within their inter-connection strength
• Every Neuron Implement the Active Function:
0
1
wxw i
n
i
Ti
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System Interface
• Input: - Image (16x16 pixels) - Weights
• Output: - A number between 0-9 (4 bit vector)
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System Architecture
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Net Architecture
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Controller – Flow Diagram
![Page 8: Presenting: Itai Avron Supervisor: Chen Koren Final Presentation Spring 2005 Implementation of Artificial Intelligence System on FPGA.](https://reader035.fdocuments.us/reader035/viewer/2022070412/56649d4e5503460f94a2e1b6/html5/thumbnails/8.jpg)
Neuron Architecture
![Page 9: Presenting: Itai Avron Supervisor: Chen Koren Final Presentation Spring 2005 Implementation of Artificial Intelligence System on FPGA.](https://reader035.fdocuments.us/reader035/viewer/2022070412/56649d4e5503460f94a2e1b6/html5/thumbnails/9.jpg)
Hardware Requirements
• Neuron : ROM – 2^15*20 bit = 80KB 257 Multipliers (20 bit input)
256 Adders (40-48 bit input)
• Network : Memory – Used : 17*(256+1)*20 bit = 10.7KBIn Reality : 32 Lines => 20.1KB
• System : Image registers – 20*256 bit = 640B
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Simulations
Neuron:
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Neural Network
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Neural Network (Cont.)
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System
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System (Cont.)
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Synthesis
• Synthesis on 3 different FPGA
1. xc2v1000-5-bg575 -> 67.128MHz
2. xc2v1000-6-fg256 -> 80.540MHz
3. xc2vp20-6-fg676 -> 75.603MHz
Frequency = 80MHz
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Comparison
• Matlab : 114 errors out of 1000 pictures
Calculation time: 0.5970 sec
• VHDL : 114 errors out of 1000 pictures
Calculation time:
1000*43/80MHz = 0.5373 msec
The hardware is about 1000 times faster!!
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Improvement Suggestion
• Change numbers resolution to less than 18 bit(max input bits in Xilinx components)
• Implement learning is HW