Presentation Final Project name: Synchronization for Quantum Encryption System Project supervisor :...
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Transcript of Presentation Final Project name: Synchronization for Quantum Encryption System Project supervisor :...
PresentationPresentation FinalFinal
Project name: Synchronization for Quantum Encryption System
Project supervisor : Yossi Hipsh .Project performed by : Omer Mor, Oded Belfer.
Quantum Encryption System -Synchronization
Project GoalProject Goal
The Synchronization system is an integral part of a quantum encryption system. The system will allow transferring messages in a safe way that a third unauthorized person would not be able to decipher .
The Synchronization system is needed to control the detector so it would be able to identify a single photon in an optic cable at a given time .
Quantum Encryption System -Synchronization
System requirementsSystem requirements
Locate and place a single photon with 0.5nSec accuracy resolution, in a 3nSec window.
The system should be a “stand alone” system and not depended on other components of the encryption system. For that we will need to simulate the other systems.
The system should be capable to work with very fast pulses.
The system will receive an Optic Sync signal and transfer it to a delayed electric signal, according to the photon arrival.
Quantum Encryption System -Synchronization
General Block schemeGeneral Block scheme
Syncronization System
Transmitter
PC
Receiver Optic Sync
Our part
Feedback
Electric 3nSec Sync pulse
Optic Data (Photon)
End Start
Quantum Encryption System -Synchronization
Synchronization system – Synchronization system – General Block schemeGeneral Block scheme
5V Surface
3.3V Surface
Quantum Encryption System -Synchronization
General Block scheme –General Block scheme –5V Surface5V Surface
Optic Detector Board
Pulse stretcher
Splitter TTL
D.D.L TTL
D.D.L TTL
Ref – Test point
Computer
D.D.L TTL
FPGA
Splitter TTL
Ref – T.P
To 3.3V
SyncPhoton
τ ≤ 0.5μSecPulse width 35nSec
Optic syncFrom transmitter
5V Surface
Synchronization board.
NB3L553 NB3L553
3D7408_1
3D7408_1 3D7408_1
TTL To ECL
MC100ELT20
Quantum Encryption System -Synchronization
General Block scheme –General Block scheme –3.3V Surface3.3V Surface
Mono Stable
Splitter ECL
D.D.L ECL
D.D.L ECL
Balanced to Unbalanced
Splitter ECL
Ref – Test point
To Receiver
30pSec ≤ τ ≤ 10nSec
Pulse width 3nSecFrom 5V
Surface
3.3V Surface
Synchronization board.
Splitter ECL
Balanced to Unbalanced
Ref – Test point
MC100EP11
MC100EP195 MC100EP11
MC100EP11MC100EP195PECL To LVPECL
MC100LVEL92
Quantum Encryption System -Synchronization
Special components –Special components –Optic Detector BoardOptic Detector Board
Regulator9V Input Optic
Detector Transformator
Optic Sync. Input From transmitter
Pulse stretcher
Balanced Unbalanced
3.3V
Quantum Encryption System -Synchronization
Special components –Special components –StretcherStretcher
Splitter TTL 1:4
From Optic Detector
D.D.L ECL
Flip Flop
CLK
_Q
QS
D
R
'1'
'0'
TTL To ECL
ECL To TTL
TTL To ECL
MC100EP31MC100ELT20
MC100ELT20
MC100ELT21 NB3L553
3D7408_1
Quantum Encryption System -Synchronization
Special components –Special components –Mono StableMono Stable
Splitter ECL 1:2
D.D.L ECL
From TTL To ECL
D.D.L ECL
Flip Flop
CLK
_Q
QS
D
R
'1'
'0'
MC100EP11
MC100EP195
MC100EP195
MC100EP31
Quantum Encryption System -Synchronization
Special components – Bal-UNSpecial components – Bal-UN Balanced to Unbalanced
OUT
68Ω 68Ω68Ω68Ω
140Ω
140ΩIN
+
-
VTT
100nF
100nF
Quantum Encryption System -Synchronization
Special components –Special components –FPGA Input OutputFPGA Input Output
FPGA
Sync END
Computer
Sync START
D.D.L ECL
D.D.L TTL
“Photon” – from splitter #1 “Sync” – from splitter #2
ADD1 Enable ADD2 Enable STR1
Valid photon 1STR2
Valid photon 2
’ *Valid photon’ will be used only if STR is not available.
X4
X4
10 Bit Bus
LEN
LEN
Quantum Encryption System -Synchronization
Quantum Encryption System -Synchronization
Optic Detector BoardOptic Detector Board
The optic detector board will receive optic signal and translate it to a balanced electric pulse.
The board will supply the working needs for the Optic detector.
Input : Optic signal (Laser). Output : Balanced electric pulse.
Quantum Encryption System -Synchronization
Aspects in choosing componentsAspects in choosing components
Technological compatibility - (TTL/ECL, input and output voltage) – most of the components we chose works in TTL technology because we needed width pulse for the computer and to the long delay device.
System compatibility - (with the transmitter, receiver and computer) – the transmitter output is an optic pulse so we needed to add an optic detector. The receiver input is in ECL technology so we need to convert the output technology to ECL and to low voltage .
Short Trise and Tfall – because we deal with a short an accurate pulses.
Available for purchase.
Quantum Encryption System -Synchronization
System InputsSystem Inputs Optic Sync pulse from the transmitter – we will
simulate this pulse with a laser to test our system before integration with the transmitter.
STR1 & STR2 pulses from the receiver – feedback to check the photon arrival. We simulated this pulse as Valid Photon 1&2 in the FPGA to test our system before integration with the receiver.
SYNC_START from the PC – starting the calibration sequence. We also assigned a switch on the board to simulate SYNC_START command.
FPGA Control
Quantum Encryption System -Synchronization
System OutputsSystem Outputs
Delayed electric Sync to the receiver – the pulse will be delayed according to the photon arrival, we will be able to test this pulse with a scope in the reference test points.
D.D.L control from FPGA – controlling the D.D.L delay – a binary word that will translated to delay in the D.D.L.
MIX_Enable from FPGA – MIX Enable=‘1’ while calibrating the system, MIX Enable=‘0’after calibration is over - reactivate the MIX in receiver.
Sync_end form FPGA – Informing the computer that the calibration is over.
Quantum Encryption System -Synchronization
Hardware specification & NeedsHardware specification & Needs The Pulse input for the board should be at least 2V
high, because the optic detector board output levels are low we need an Amplifier between the him and the board input.
The chosen amplifier needs a 24V transformer . The optic detector board needs 9V transformer . 50 PIN flat cable for connecting the FPGA to our board Scope for checking the system performance .
Power Supply's specificationPower Supply's specification The board needs 5V power supply. The 5V input is inserted into 3 Voltage regulators that
will create the needed voltages for the 3 others voltage surfaces.
Every regulator has a variable resistor connected to him, so we will have a tolerance to the voltages we can supply to the rest of the board.
Quantum Encryption System -Synchronization
Power Supply's DistributionPower Supply's Distribution
Voltage Regulator
5V Input
3.3V
Voltage Regulator
3V
Voltage Regulator
1.3V
5V
PTH04000W
PTH04000W
PTH04000W
5V Surface VIA
3.3V Surface VIA
3V Surface VIA
1.3V Surface VIA
Variable Resistor 500 Ω
Variable Resistor 500 Ω
Variable Resistor 2K Ω
Quantum Encryption System -Synchronization
The Board DesignThe Board Design The board has 4 layers of power/GND, 3 different
layers in each part of the board, a surface for the FPGA control lines, and on top the transmission lines.
The two parts of the board are separated completely from one to another.
the two GND surfaces is connected to one another in the power input connector of the board, that way we will decrease the GND noise.
The data pulse is being converted to 3.3V levels before entering the 3.3V side surface.
The FPGA I/O lines are 3.3V LVTTL and can control all the component in our board (including the ones that work with 5V).
Quantum Encryption System -Synchronization
The board has a total of 7 layers, two of them are divided to two parts for different voltage levels so we have a total of 9 different surfaces.
Each part contains the same layers but connects to the right layers with via holes..
The two parts of the board are suppurated completely from one to another. The surfaces are:
– 5V VCC surface
– 3V VTT surface
– 5V GND surface
– 3.3V VCC surface
– 1.3V VTT surface
– 3.3V GND surface
– Transmission Lines on top surface
– Control lines 1
– Control lines 2
Board surfaces Board surfaces
Quantum Encryption System -Synchronization
Board surfaces From HyperLynx Board surfaces From HyperLynx
Quantum Encryption System -Synchronization
Board surfaces Board surfaces
Quantum Encryption System -Synchronization
The Board DesignThe Board Design
Quantum Encryption System -Synchronization
The Board DesignThe Board Design
Quantum Encryption System -Synchronization
The Board DesignThe Board Design
Quantum Encryption System -Synchronization
The Board Design - considerationThe Board Design - consideration Every Component Voltage input is protected and filtered with two
capacitors to stable the input voltage and protecting it. Technological matching was made so every component will connect
correctly to the one before him and the one after him, in special cases a pull-up resistor or a voltage level converter was inserted.
Power and currents levels was calculated according to the components specifications. – The total power that was calculate id: 5.54W– The total current needed from the power supply is: 1.5A (min)
Quantum Encryption System -Synchronization
The Board Design – The Board Design – High Speed considerationHigh Speed consideration In order to eliminate the high frequency noise we used
transmission lines on all the hi speed components. The transmission lines width were determined to be
200μm because of 2 reasons:1. The line will be about 50Ω Z0 impedance, and the connectivity to the
components will be possible.
2. The line should be small enough to be able to connect to the components legs.
The dielectric surface around the transmission line were chosen to be 115μm also to make sure the Z0 is about 50Ω (received the results from the HyperLynx)
Quantum Encryption System -Synchronization
The Board Design – The Board Design – High Speed considerationHigh Speed consideration
All the transmission lines needed to be shorter the a quarter of a wave length (L<λ/4) .
It was decided that the Tr of the board will be 0.5nSec at the worst case. All of the chosen ECL fast components fulfilling this decision and even much faster.
Tr = 0.5nSec, BW = 1/(Tr*π) => BW = 640MHz
λ=T*C = 1.57*10^-9 * 3*10^10 ~ 47cm To insure that L<< λ we designed the board to have
transmission line the size if L = λ /10 = 4.7cm
Quantum Encryption System -Synchronization
The Board Design – The Board Design – High Speed considerationHigh Speed consideration
In order to make our board smaller than 4.7cm we inserted all the hi speed components and the transmission lines ware inserted to a
32 mm X 22mm )approximately) “Metal Cage” .
The Cage was created by inserting VIA’s to the ground around the wanted area,
we inserted a via hole every 3.8mm so the distance between 2 holes will be far smaller then λ .
Inside every cage the wave length requirement is met.
Quantum Encryption System -Synchronization
The Board DesignThe Board Design
Quantum Encryption System -Synchronization
ECL ZOOM – Transmission lines
~3.8mm
The Board Design – The Board Design – High Speed Hyperlink SimulationHigh Speed Hyperlink Simulation In order to see the Transmission lines behavior in our
high speed system we simulated the high speed part of the board.
We simulated each transmission line separately and seen the change from the input of the line to the output of the line.
The result show that because we selected our high speed part to be smaller than the wave length and all our transmission lines are short, we don’t have a significant change in our pulse and we can assume the there is no loss or change in our data.
Quantum Encryption System -Synchronization
The Board Design – High Speed Hyperlink SimulationThe Board Design – High Speed Hyperlink Simulation
Transmission line simulation exampleTransmission line simulation example
Quantum Encryption System -Synchronization
The Board Design – High Speed Hyperlink SimulationThe Board Design – High Speed Hyperlink Simulation
Transmission line simulation exampleTransmission line simulation example
Vin*
Quantum Encryption System -Synchronization
The Board Design – High Speed Hyperlink SimulationThe Board Design – High Speed Hyperlink Simulation
Transmission line simulation exampleTransmission line simulation example
*Oscillator simulation 640MHz
1562.5 PS
Input to transmission lineOutput from transmission line
Quantum Encryption System -Synchronization
The Board Design – High Speed Hyperlink SimulationThe Board Design – High Speed Hyperlink Simulation
Transmission line simulation exampleTransmission line simulation example
*Edge simulation
Input to transmission lineOutput from transmission line
Quantum Encryption System -Synchronization
Synchronizer Board BOMSynchronizer Board BOM
Quantum Encryption System -Synchronization
Synchronizer Board BOMSynchronizer Board BOM
Quantum Encryption System -Synchronization
Logic design of the FPGA softwareLogic design of the FPGA software
IFValid_photon
Delay = Delay + 1nSec Count = Count + 1
IFCount = N
Count = 0Delay = 0
Mix_enable = ‘1’
Sync_start
Count = 0
YES
YESNO
NO
Accurate Delay in 10pSec
Next page
Quantum Encryption System -Synchronization
Quantum Encryption System -Synchronization
Placing the photon in the first 10pSec of the windowPlacing the photon in the first 10pSec of the window
IFValid_photon
Delay = Delay – 10pSec Count = Count + 1
Sync_Delay = DelayMix_enable = ‘0'
IFCount = N
Sync_DelaySync_END
YES
YESNO
YES
Delay = Delay + 10pSecCount = 0Pulse_start=1
IFPulse_start=1
NO
NO
Count = Count + 1
IFCount = N
NOYES
Count=0Pulse_start=0
We can set N - the number of iteration according to probability statistics for increasing the correctness of the system.
Quantum Encryption System -Synchronization
VHDL ImplementationVHDL Implementation
DDL_MONO1_LEN
DDL : (9:0)DDL_TTL1_AEDDL_TTL2_AE
Strecher_ENSplitter2_ENSplitter1_ENDDL_ECL1_EN
Sync_End
DDL_TTL3_AE
DDL_ECL2_ENDDL_MONO1_ENDDL_MONO2_EN
DDL_Strecher_AEDDL_ECL1_LENDDL_ECL2_LENDDL_MONO1_LENDDL_MONO2_LEN
Photonclk
sync_libSync_mainU_0
LED1
LED2LED3LED4LED5LED6LED7
DDL : (9:0)
DDL_TTL2_AE
DDL_ECL1_LENDDL_ECL2_LEN
DDL_TTL1_AE
DDL_Strecher_AE
LED11LED14LED15
LED8LED9
rstpush_button1
START_COMP
Valid_Photon2Valid_Photon1
DDL_TTL3_AE
LED1LED11LED14LED15
LED2LED3LED4LED5LED6
LED8LED7
LED9
sync_libSync_main_testerU_1
START_COMP
Valid_Photon1Valid_Photon2
rstpush_button1
Photon
sync_libPhoton_genU_3
Photon
sync_libClock_genU_2
clk
DDL_MONO2_LENStrecher_ENSplitter2_ENSplitter1_EN
DDL_ECL1_EN
DDL_MONO2_ENSync_End
DDL_MONO1_ENDDL_ECL2_EN
VHDL ImplementationVHDL Implementation
Quantum Encryption System -Synchronization
VHDL Implementation - INITVHDL Implementation - INIT
Clock_counter = 12 -- 20nsec
clk clk'EVENT AND clk = '1'
Idle
rst Idlerst = '0' Idle
push_button1='1' OR START_COMP='1'
Save_value
Initial_values
Clock_counter = 3 -- 20nsec
Mono_3nSec
18 -- 50nsec
Clock_counter = 21 -- 20nsec
Strecher_35nSec
9 -- 50nsec
12
27 -- 50nsec
3
End_Init
End_Sync
Sync_End = '1'
Quantum Encryption System -Synchronization
VHDL ImplementationVHDL Implementation – Long Delay – Long Delay
Quantum Encryption System -Synchronization
Check_Photon
clk clk'EVENT AND clk = '1'
rst Idle
Idle
rst = '0'
Idle
Photon = '1' AND Init_End = '1' AND Long_Delay_End_int ='0' AND Error_delay ='0'
Init_End = '1'
Change_Delay
Increase the first DDL
Not_Valid_counter
Clock_counter >= 60 -- 0.6uSec
DDL_long1 < "0011111111"
No_Photon_counter >= 5
Need to Delay the signal
The photon is not in the window
Valid_counter
Valid_Photon1 = '1' ANDValid_Photon2 = '1'
Valid_Photon_counter >= 5
The photon is in the window
Inc_TTL2
New_delay2
1
DDL_long1 >= "0011111111"
2
DDL_long2 >= "0011111111"
The first DDL is in MaxIncrease the secound DDL
End_Long
Inc_TTL1
New_delay1
Save_delay
Clock_counter >=3 -- 20nsecErrorClock_counter >=3 -- 20nsec
VHDL ImplementationVHDL Implementation – Short Delay CH1 – Short Delay CH1
Quantum Encryption System -Synchronization
clk clk'EVENT AND clk = '1'
Idle
Check_Photon
Long_Delay_End = '1'rst Idle
Idle
rst = '0'
Photon = '1' AND Long_Delay_End = '1' AND Short_Delay1_End_int <= '0'
Not_Valid_counter
Clock_counter >= 60 -- 0.6uSec
The photon is not in the window
Valid_counter
Valid_Photon1 = '1'
The photon is in the window
Valid_Photon_counter >= 5 AND wanted_position1 = '1'
Need to change the Delay
Less_Delay More_Delay
No_Photon_counter >= 5 Valid_Photon_counter >= 5 AND wanted_position1 /= '1'
The photon is in the beginning of the window
Need to change the DelayThe photon is in the beginning of the window
End_Short1
Write_delay
Save_delay
Clock_counter >= 3 -- 20nsec
VHDL ImplementationVHDL Implementation – Short Delay CH2 – Short Delay CH2
Quantum Encryption System -Synchronization
Check_Photon
More_Delay
Valid_Photon_counter >= 5 AND wanted_position2 /= '1'
Short_Delay1_End='1'
Write_delay
Save_delay
Clock_counter >= 3 -- 20nsec
Not_Valid_counter
rst = '0'
clk'EVENT AND clk = '1'
Need to change the DelayThe photon is in the beginning of the window
rst
clkIdle
Idle
Idle
Clock_counter >= 60 -- 0.6uSec
Less_Delay
No_Photon_counter >= 5
The photon is not in the window
Valid_counter
Valid_Photon2 = '1'
Need to change the Delay
Photon = '1' AND Short_Delay1_End='1' AND Sync_End_int <= '0'
Valid_Photon_counter >= 5 AND wanted_position2 = '1'
The photon is in the window
The photon is in the beginning of the window
End_Short2
VHDL design verification – Init blockVHDL design verification – Init block
Quantum Encryption System -Synchronization
• Initializing all DDL to minimum delay (at 60-120 nSec).• Initializing the DDL stretcher to 35nSec (at 160-220 nSec).• Initializing the DDL mono to 3nSec (at 250-320 nSec).
VHDL design verification – Long delayVHDL design verification – Long delay
Quantum Encryption System -Synchronization
The long delay block finishes his process when the photon is inside the window (5 times in a row) the window is 3nSec and the next figure shows the long delay finish state.
VHDL design verification – Short delay channel 1VHDL design verification – Short delay channel 1
Quantum Encryption System -Synchronization
The short delay channel 1 start his process after the long delay finished working => the photon is inside the window. As shown in the next figure the process finishes his work when the wanted_delay1 is equal to the total_delay1 => the photon is in the beginning of the window.
VHDL design verification – Short delay channel 2VHDL design verification – Short delay channel 2
Quantum Encryption System -Synchronization
The short delay channel 2 start his process after the short delay channel 1 finished working => the photon in channel 1 is inside the beginning of the window. As shown in the next figure the process finishes his work when the wanted_delay2 is equal to the total_delay2 => the photon is in the beginning of the window. The system can sync the 2 channels to a different delay so each of them will arrive at the beginning of the window. At the end of this process the system send a signal to the computer (sync_end) indicates the end of the
synchronization and Enables the ADD function in the receiver .
VHDL design verification – Error reportingVHDL design verification – Error reporting
Quantum Encryption System -Synchronization
When the system cannot insert the photon inside the window or there is a problem in the sync – all the red LEDs on the FPGA board will light and the process will stop with an error signal .
Added valueAdded value
Quantum Encryption System -Synchronization
The project gave us a glimpse of how a big project in the industry might take place. We had to take under consideration all the time that we are part of a big project and have to make our system compatible with the other system.
The project gave us experience in board design, taught us some of the designing aspects we need in order to make a good board. Also gave us some experience working with design and simulation tools such as Orcad and HyperLynx
The project gave us experience in FPGA design and digital way of designing a system that needs to control other system digitally (with the FPGA board)
Improving point & future continuing optionsImproving point & future continuing options
Quantum Encryption System -Synchronization
The project was mostly theoretical ,by experimenting the components in an early stage we could have seen their actual behavior and be sure of our design, in order to make these experiments possible, a generic board needs to be designed and manufactured. The board will supply the components working needs and samples has to be ordered in an early stage.
Part of the project was to design the layer properties of the board, and to give instructions to the editor. A meeting with an editor and consulting him would make our instructions better, and more focused.
For continuing the project a board needs to be manufactured and the VHDL design needs to be tested on the real system, in order to make sure that the design fully functions.