1 Pulse Generator High Speed Digital Systems Lab Semestrial project – Winter 2007/08 Final...
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1
Pulse Pulse GeneratorGenerator
High Speed Digital Systems LabHigh Speed Digital Systems LabSemestrial project – Winter 2007/08Semestrial project – Winter 2007/08
Final PresentationFinal Presentation
Instructor: Instructor: Yossi HipshYossi Hipsh
Students: Students: Lior Shkolnitsky, Lior Shkolnitsky, Yevgeniy LobanovYevgeniy Lobanov
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TopicsTopics The Challenge OverviewThe Challenge Overview I/O schemeI/O scheme Block DiagramBlock Diagram General ViewGeneral View Electrical SchemeElectrical Scheme Stack Layout Stack Layout Bill Of MaterialsBill Of Materials MeasurementsMeasurements
GeneralGeneral Set UpSet Up ResultsResults
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The Challenge The Challenge OverviewOverview
The main goal is to design an The main goal is to design an Adjustable Pulse Generator.Adjustable Pulse Generator.
This Generator will be integrated into This Generator will be integrated into an existing lab experiment, that teaches an existing lab experiment, that teaches about High Speed Systems Phenomena: about High Speed Systems Phenomena: reflections, skew, jitter, etc. reflections, skew, jitter, etc.
The Generator will create a very short The Generator will create a very short (0.5-1 nsec) and a longer (10-13 nsec) (0.5-1 nsec) and a longer (10-13 nsec) pulsepulse signal into transmission line.signal into transmission line.
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I/O schemeI/O scheme
Adjustable
Pulse
Generator
Power supply
Pulse width selection
Short pulse
Long pulse
5
Power Supply
6 V
10 nsec0.5-1 nsec3.3 V 700 mA
Block DiagramBlock Diagram
SplitterAND
Manual Selector
AdjustableDelay
AdjustableDelay
1-shot
Translator
TTL Diff LVPECL
100 nsec
10 nsec 10 nsec
Translator
TTL Diff LVPECL
1.3V Voltage
Regulator
3.3V Voltage
Regulator
Oscillator
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SplitterAND
Adjustable
Delay
Adj. Delay
1
shot
Translator
TTL
Diff LVPECL
Translat.
TTL
Diff LVPECL
Osc.
General View
• Each Switch – 16 states
• Each Delay Unit – 8 (of 10) wires of control
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Electrical Scheme (1/2)
C50.01n
U2A
D2
CP3
Q5
Q6
Vcc
_3.3
v14
SD4
GN
D7
CD1
C81n
C70.01n
Vcc_3.3v
C101n
Vcc_3.3v
C90.01n
C121n
C110.01n
C13120pF
U1
CO1025-10.000-3.3
14VCC
8OUT
7GND
U5
MC100EPT20
GN
D5
D7
Vcc
_3.3
v8
Q2
Q3
U4
MC100EPT20
GN
D5
D7
Vcc
_3.3
v8
Q2
Q3
D1 D1N4002D2 D1N4002
Q2
Q2'
R25
R1121
C210u
C110u
6v Vtt Vcc_3.3v6v
C410u
C310u
Q1
Q1'
U7
LM1895 IT-3.3
3IN
2OUT
GND
1
Vtt = Vcc_3.3v-2v = 1.3v
U3
MPC94551
Q12
Vcc
_3.3
v7
ICLK1
GN
D6
OE8
Q23
Q34
Q45
MC74LCX74DG
U6
LM1895 IT-ADJ
3IN
2OUT
ADJ
1
Title
Size Document Number Rev
Date: Sheet of
Designed by: Lior Shkolnitsky , Yevgeniy Lobanov 6
Pulse Generator - LEFT part
A
1 2Monday, April 07, 2008
High Speed Digital Systems Lab - Technion - Winter 2007/08
C61n
8
D2
D2
D[2:5]
D[6..9]
D6
D6
D7
D8
D8
D8
D9
D9
D9
D6
D7
D6
U8
Q20Q21
GN
D28
VBB6
EN16
IN4
IN5
LEN10
SETMIN11
SETMAX12
GN
D9
GN
D24
CSCD15
CSCD14D0
23
D125
D226
D327
D429
D530
D631
D732
D81
D92
D103 Vef
7
Vcf8
EC
L13
Vcc
_3.3
v18
Vcc
_3.3
v19
Vcc
_3.3
v22
N.C.17
D7
Q1'
Q2
50 ohm
D4
Q2'
D`[6..9]
D3
D3
MC100EP195
MC100EP195
D`9
U10MC100EP05
17
85
6
2
34
C211n
C200.01n
R5
50
R4
50
Vtt
Vtt
Vtt
R1250
Differential Pulse
D4
C271n
D4
Output
C260.01n
R650
R1350
D`7
R750
D`9
D`3
D`8
D`6
D`2
D`9
D`2
D`5
D`8
D`4
D`6
D`4
D`5
50 ohm
Vcc_3.3v
J3
CON5
12345
R141k
D4
J4
CON5
12345
J1
CON5
12345
Vcc_3.3v
R31k
J2
CON5
12345
D`[2..5]
Vtt
R1150R10
50
Vtt
R8
50
R9
50
D`8
C191n
C180.01n
C171n
C160.01n
C151n
C140.01n
C251n
C24
0.01n
D`6
D`7
D`2
D`3
D`4
D`5
C231n
C220.01n
D`7
D5
D5
D2
D`2
D`7
D5
D`3
U9
Q20Q21
GN
D28
VBB6
EN16
IN4
IN5
LEN10
SETMIN11
SETMAX12
GN
D9
GN
D24
CSCD15
CSCD14D0
23
D125
D226
D327
D429
D530
D631
D732
D81
D92
D103 Vef
7
Vcf8
EC
L13
Vcc
_3.3
v18
Vcc
_3.3
v19
Vcc
_3.3
v22
N.C.17
D5
D`4
D`6
Q1
D`8
D8
D`9
D`5
D9
D`3
D2
D3
D7
D3
Electrical Scheme (2/2)• All The 50 ohm
Resistors – Close to receiver
• Each Red line –– fast signal – Upper Layer
• Bypass Capacitors – Close to the Power Pins
• All 4 lines have the same length
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Stack LayoutSIGNAL
FR 4
GND
Vcc (ECL) = 3.3 V
GND 2
FR 4
FR 4
each metal layer –Copper
each dielectric layer: er=4.3
Control
FR 4
Vtt = 1.3 V
FR 4 250um thickness
50um thickness
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Bill Of Materials # Name Part Number Quant
ityIn lab
1 Voltage Regulator LM1085 – 3.3V 1 Yes
LM1085 – ADJ 1 Yes
2 10MHz Oscillator CO1025-10-3.3 1 Yes
3 Flip Flop (One Shot) MC74LCX74DG
1 No
4 Splitter (Fan Out Buffer)
MPC94551 1 No
5 TTL to LV PECL Translator
MC100EPT20 2 No
6 Adjustable Delay MC100EP195 2 No
7 AND Gate MC100EP05 1 No
8 Pair of Manual Selectors PA-G-A-3-2-00 2 No
9 Connector for Manual Selector
C2KF-P109 4 No
10
Resistors /Capacitors/ Diodes
Yes
Appendix 1(click to jump)
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Measurements
We did measurements, as if after production.
Those measurements are for validating the generator’s functionality, and for debug.
The Pulse Generator Device was simulating the designed Pulse Generator Card.
The Pulse Generator sent a pulse, similar to the expected pulse from the Card.
General
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Measurements
Instruments used: Pulse Generator – HP 8133A – emulated
the DUT 50 GHz Sampling Scope – HP 83480A,
54752A Attenuators – 6dB, 18 GHz BW
Set Up
Pulse Generator
Signal
Trigger
Scope
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MeasurementsMeasurements
All the Measurements may be observed right now in lab…
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MeasurementsMeasurements
Measured Parameters: Timing:
Pulse width 475 psec Time jitter (p-p) 11.6 psec Rise time, fall time 44.4, 43.6
psec Voltage
Pulse amplitude 381 mV Voltage jitter (p-p) 1.3 mV
Results (1/4)Results (1/4)
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Scope screenshot, started to capture:
MeasurementsMeasurementsResults (2/4)Results (2/4)
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Scope screenshot, after 1 hour of capture:
גדלjitterה-
MeasurementsMeasurementsResults (3/4)Results (3/4)
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Zoom on rising and falling edges:
MeasurementsMeasurementsResults (4/4)Results (4/4)
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Questions / AnswersQuestions / Answers
Thank you!Thank you!
19
Appendix 1Appendix 1Resis. [Ω]
Role Quan.
1 50 Termination to Vtt 10
2 5 Voltage Regulator for Vtt
1
3 121 Voltage Regulator for Vtt
1
4 1000 Switches protection 2
ResistorResistorss
CapacitorCapacitorss
Capac. [μF]
Role Quan.
1 10 Voltage Regulators
4
2 0.1 Bypass Capacitors
7
3 0.001 Bypass Capacitors
7
4 TBD Monostable feedback
1
Go back…
DiodesDiodesPart No.
Role Quan.
1 1N4002 Protection of the PS and Voltage Regulators
3
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Future Plans – Time Future Plans – Time TableTable
End date 24/1 31/1 7/2 14/2 23/2
Making the board Making the board
Building the prototype Building the prototype
The test setup – The test setup – designing, debuggingdesigning, debugging
Writing the report Writing the report
Final PresentationFinal Presentation
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Time Table
Task \ WeekTask \ Week 11 22 33 44 55 66 77 88 99 1010 1111 1212 1313 1414
Exploring the problem Exploring the problem 22-10
Definition presentation Definition presentation 22-11
Block diagram Block diagram consolidation consolidation
Finding suitable Finding suitable components components
Designing the board Designing the board
Design presentation Design presentation 19-12
Ordering components Ordering components and board and board
Writing the booklet Writing the booklet
Designing a test setup Designing a test setup
Building the project Building the project 15-01
Building the test setup Building the test setup
Test and Debug Test and Debug
Final presentationFinal presentation 30-01
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The SignalThe Signal
0.5 nsec
2V
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Input Calculation For example – 3 nsec delay 10-3= 7 nsec (shift of the left delay
unit) 7 nsec – 1010111100 (700*10psec) 1010 __ 1111__00 Left switch – AF Right switch - 00