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Chapter 3

Instruction Set ArchitecturesObjectives

1. Design an instruction set architecture for a processor needed to accomplish a given task.

2. Classify instructions based on their function3. Correctly identify different addressing modes and

generate their effective addresses.

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Instruction Set Architecture

• The Programmer’s interface to the CPU• Describes:

– CPU programmable functional components– CPU Instructions– Interrupts– Memory Management

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Assembly Language Instructions

• Instruction Types• Data Types• Addressing Modes• Instruction Format

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Instruction Types

• Data Transfer Instructions : move data from one location to another w/out change.– Load Data from Memory to CPU registers– Store Data from CPU registers to Memory– Move Data between CPU registers– Input Data from an Input Device to a CPU register– Output Data from a CPU register to an Output Device

• Data Operations: Data may be altered– Arithmetic Instructions( e.g. ADD, SUB, MULT, DIV, …etc.)– Logic Instructions( e.g. bitwise AND, OR, XOR, NOT, Compare

…etc.)– Shift Instructions (e.g. Shift left/right, Rotate left/right

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Instruction Types “Cont’d”

• Program Control Instructions:– Jump (Branch) Instructions: Absolute vs. Conditional– Call & Return Instructions– Software Interrupts– Halt

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Data Types

• Numeric Data

– Unsigned Integers: 0 to 2n -1

– Signed Integers: -2(n-1) to 2(n-1) -1– Floating Point

• Boolean Data (True ≠0, False=0)– Special Instruction (not bitwise)

• Character Data– ASCII, EBCDIC, UNICODE

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@R

Stores

Addressing Modes

a) Directb) Indirectc) Register directd) Register indirecte) Immediatef) Implicitg) Relativeh) Indexed

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Instruction Format: Computing “A= B + C” Using aa) 3-Operand CPU b) 2-Operand CPU

c) 1-Operand CPU d) Zero-Operand CPU

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Design of an Instruction Set Architecture

• Completeness:– Design meets, and not exceed, the application requirements– General-Purpose vs. Special-Purpose microprocessors.

• Orthogonality:– Minimize redundancy in the Instruction Set.

• Register Set:– More registers leads to faster performance.– Register Size: 16-bit, 32-bit, 64-bit, or 128-bit registers.– Integer and Floating-Point registers/instructions

• Backward Compatibility• Data types and sizes for the intended use of the CPU.• Need for Interrupts

– Special registers and instructions to deal with interrupts• Need for conditional Instructions:

– E.g. conditional jumps and calls– Need special “flag” registers.

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1. Memory Model:– Address Space: 64KB ( = 216 Bytes). One byte = 8 bits.– Uses I/O ports

• I/O device access require separate I/O instructions2. Register Model: This is a one-operand CPU

– Three Programmer Accessible registers:• AC: The 8-bit Accumulator. Acts as one of the operands of

ALU operations, and as a store for the result• R: A general-purpose 8-bit register. • Z: A 1-bit zero-flag register. Indicates whether the most

recent ALU operation resulted in a Zero.– Other registers for internal CPU use. Not part of the ISA.

3. Instruction Set: shown in the next slide.• 16 Instructions: 8-bit operation code plus a possible 16-bit

address.

A Relatively Simple Instruction Set Architecture

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Instruction Set for the Relatively Simple CPU

Γ is a 16-bit address

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Instruction Format for the Relatively Simple CPU

a) 3-Byte format b) 1-Byte format

e.g. “JUMP 1234H” is coded as “05 34 12”

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Computing ∑=

n

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1Shortcomings

1. Small 8-bit data values

2. Few registers, many memory access operations

3. Instruction Set inadequate for general purpose CPU

• No Floating-Point

• Missing arithmetic ops

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Execution Trace of the Loop Summation Program

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Register Model

– AC: The 8-bit Accumulator. Acts as one of the operands of ALU operations, and as a store for the result

– B,C,D,E,H,L: 6 general-purpose 8-bit registers. Could be paired as three 16-bit BC, DE and HL registers.

– SP: The Stack Pointer– Flag Register: 5 flag bits for Sign, Zero, Parity, CarrY,

Auxiliary Carry– Other registers for internal CPU use. Not part of the ISA.

Intel 8085 Instruction Set Architecture

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Intel 8085 Data Movement Instructions

r, r1, r2: 8-bit regs (A,B,C,D,E,H, or L) M[HL] : memory whose addr. in HL

rp: reg. pair (BC, DE, HL) Γ: 16-bit address n: 8-bit immediate value

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Intel 8085 Instruction Format

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I-8085’s Data Operation Instructions

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I-8085’s Program Control Instructions

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Chapter 3 Homework

• Practice problems 1-14• Submit #9. One submission per project-group

Skip• Sections 3.1

Self-Study• Section 3.5