Present Uses of the Fermilab Digital Signal Receiver

VXI ModuleBrian Chase,Paul Joireman, Philip Varghese

RF Embedded Systems (LLRF) Group

• 8 Channel Digital Receiver VXI Module

• 65 MSPS AD6644 ADCs with AD6620 DDC

• ADSP21062 Floating Point DSP

• Sync modes in 2 channel pairs

• External sample trigger, front panel or back-plane for TBT mode

• Differential inputs on DB15 connectors or SMB option

• Daughter card for each channel pair with DAC and digital control

• 4 12 bit DAC front panel outputs

• 130 dB dynamic range at /square root Hz

Digital Signal Receiver (DSR)

VXI BUS

Trigger Bus

VXI Interface

Control and Interface Logic

Local Bus (A&C)

32 bit Data bus

20 bit Addr bus

40 bit Floating Point Digital Signal Processor

Link Ports

ADSP-21062

Serial Port Host Port

DSR Block Diagram

1 of 8 - 65 MSPS Single Channel Digital Radios16 bit I

16 bit Q

DSR Block Diagram

I LatchMicroport

16

AD8138

AD6644AST-65

14-bit, 65-MSPS ADC

+

-

14 Data

Data Ready

AD6620ASDigital Down Converter

Q Latch

Clock16

Addr & Control

8 data

32

12 bit DAC Analog Control

Digital Control Line

Front Panel

SMB

DB15

DSR Single Channel

Ecool BPM Signal Flow Diagram

Digital Down Converter

65MSPS 14 bit 3 Stage LP Filter and Decimator 1kHz BW

AD6644AD6620

ADSP21062 SHARC DSP

65MSPS

Digital Radio ReceiverAnalog to Digital Converter

Analog Preprocessing Daughter Card

Coax or twisted pair input. Analog and digital control line.

14 IQ

32 bit NCO

Gain and Decimation Controls

DC to 5 MHz BWPosition Calculator

Front Panel DAC Monitor

14 IQ

Gain and Decimation Controls

Four twisted pair shielded

cable

Low Noise Current Preamp

NCOs frequency set to F(electron) or F(Pbar)

802 SPS

21.66 kSPS800 Hz BW

1 Hz BW

Orthogonal Position Mapping Coefficients

Calibration Coefficients

40 bit Floating Point Calculations

V152 Slot 0 Controller

SS

Offset

Preamp Gain Select

DSR Function List DsrReset() DsrLdr() DsrLdFilter() DsrSetNCOFreq() DsrSetNCOPhase() DsrSetCIC2Gain() DsrSetCIC5Gain() DsrSetRCFGain() DsrLdDetMap() DsrLdCalCoeff() DsrSetPreampGain() DsrMapDac() DsrSetDacGain() DsrSetDacOffset()

Acnet/MOOC Interface AN_ARRAY Fast Time Plotable Devices

Ethernet

DSR VXI Module 1 of 11

DSR Channel Pair 1 of 4

Ecool BPM VXI Crate

BPM Calibration System CalSetFreq() CalSetAmplitude() CalSetWaveshape()

Ethernet Generator 1 Generator 2

DSR Operational Status• Main Injector

– 53 MHz and 2.5 MHz radial position and beam phase detection for LLRF beam control loops

• ECBPMD (Recycler) - Development System

– H=1 (89 kHz) BPM processing on four detectors for over one year.

• ECBPM (Wideband) - Operational System

– 32 kHz and pulse mode processing on 19 BPMs

MI DSR RPOS Measurements

Beam/Gain Changes

Pbar/high Elec/high Elec/low Pbar/high

Intensity Changes

Pulsed Mode v. Pbar

Pulsed mode Pbar

Stretched Wire MeasurementsMove BPM Wire Along X-axis

-25

-20

-15

-10

-5

0

5

10

15

20

25

-25 -20 -15 -10 -5 0 5 10 15 20 25

Wire Position (mm)

DS

R R

ead

ing

(m

m)

Actual

Measured

Differential Non-linearityDifferential Nonlinearity along X-axis

-0.1

-0.06

-0.02

0.02

0.06

0.1

-25 -20 -15 -10 -5 0 5 10 15 20 25

Position (mm)

Dif

fere

nti

al e

rro

r (~

2mm

ste

ps)

Integral Non-linearityIntegral Nonlinearity along X -axis

-0.5

-0.3

-0.1

0.1

0.3

0.5

-25 -20 -15 -10 -5 0 5 10 15 20 25

Position (mm)

Inte

gra

l E

rro

r (m

m)

Noise Measurements

Beam

Type

PreampGain

3 X axis

(m)

3 Y axis

(m)

Electron Low 34 37

High 15 9

Pbar Low 23 27

High 16 14

100 Hz Bandwidth position data

Noise Measurements

Beam

Type

PreampGain

3 X axis

(m)

3 Y axis

(m)

Electron Low 5 2

High 2 1

Pbar Low 3 1

High 1 1

5 Hz Bandwidth position data

ECBPM Hardware/Software Block Diagram

VXI Backplane comm., IRQs, TRIGs

V152 controller

(MVME-2401)

PPC 750 VXI support PMC-UCD

lib*.out

libdsr.out

Application code (lib*.out) Select high-level operational mode Implement and install Acnet callbacks Communicate with DSR using shared

library functions (libdsr.out) Connect FTP data to Acnet

DSR Shared Library (libdsr.out) Represent DSR hardware as a software

object Provide interface to download DSP

code Reconfigure operating parameters of

DSR using vector interrupts SetNCOFreq Set*Gain Provide interface to get FTP variable

information from DSP

DSP Code (*.ldr) Provide low-level communication with

AD6620 DDC Retrieve and optionally filter incoming

signal Calculate engineering variables, posi-

tions, intensities, other ... Switch between operational modes

NORMAL, PULSED, (TBT?)

Console PA/SA R39, E54 ...

VXI DSR Module

DSP AD-21062 , 40Mhz, 32-bit

DSP CODE *.ldr

FTP ~720 Hz

VXI-UCD

TCLK, MDAT, BSCLK

TRIG IRQ

TRIG VIRPT

CLOCK = 65 MHz

BPM PREAMP

15 Signal

PREAMP Gain Control

1 of 11 DSRs

ADC AD6644 14 bits

DDC AD6620

NCO CIC2 CIC5 RCF

1 Of 8

ECBPM/DSR Software FunctionalityFront End Application (VxWorks) Operational Modes Anti-proton beam position Electron beam position ALT (pbar-electron) position Pulsed Electron Beam Additional Functionality Acnet Communication Hardware reconfiguration Calibration System Information Error Logging

DSR Shared Library (VxWorks) Represent DSR as a software object Provide interface to download DSP code Reconfigure operating parameters of DSR

using vector interrupts SetNCOFreq Set*Gain Provide interface to get FTP variable infor-

mation from DSP System Information Error Logging

DSP Code Provide low-level communication with

AD6620 DDC hardware Retrieve and optionally filter incoming

signal Calculate engineering variables, posi-

tions, intensities, other ... Switch between operational modes

NORMAL, PULSED

Console PA/SA R39, E54 ...

End-User

System Expert

Telnet, terminal or LabView session

TestDSR fe project Hardware tests of VXI-

DSR board Five testing modes LabView Control Interface

ECBPM Software Metrics• Language C/C++ • Operating System VxWorks 5.4• Development Effort 3-4 “man-months”• Lines of Code 10,000 (50 % COM)• Functions

– Manage DSR resources in VXI mainframe– Provide Acnet/MOOC interface for reading/setting and

basic control of BPM system.– Provide high-level functionality to user to configure

system for different operational modes

DSR Shared Library Metrics• Language C • Operating System VxWorks 5.4• Development Effort 2-3 “man-months”• Lines of Code 6700 (60 % COM)• Functions

– “Glue layer” to support communication between application software and DSR hardware.

– Encapsulate DSR hardware using “object-based” methodology.• Data: DSP hardware addresses• Methods

– Creation/initialization– Informational - DsrDump, DsrParamInfo– Client Vector Interrupts – requests for DSP services

DSP Software Metrics• Language C and Assembly• Operating System N/A• Development Effort 3-4 “man-months”• Lines of Code 4700 (50 % COM)• Functions

– Configure hardware in a default initial state– Communication with DSR hardware external to DSP, DDC

(AD6620) chip, VXI reset line, and hardware test points.– Low-level data processing and analysis including

acquisition, filtering and engineering calculations.

TESTDSR Software Metrics• Language C/C++ (LabView)• Operating System VxWorks 5.4• Development Effort 2 “man-months”• Lines of Code 3000 (60 % COM)• Functions

– Test low-level hardware functionality of DSR board– Five test modes

• Memory test, ADC test, Frequency sweep, Trim Potentiometers, Power Sweep

– Labview interface to control testing procedure

DSR, Tev Module Comparison

• Tev Module:

– 5 MHz BW

– Analog position processing

– Intensity triggered position sample once per turn.

– No turn marker used.

• DSR:– <<1 MHz BW

– Digital position processing

– Intensity triggered once per turn or pure narrow band

– Turn marker is optional

Process Bandwidth Considerations

• Wideband > 2 MHz– Good SNR– Systematic errors are hard to manage.

• Signal looks good but may have average error

• Narrow Band– Good SNR with large fill factor– Even with poor SNR, average is correct.

Trigger Options with DSR

AD662014

DSPAltera 7128

16

161616

32

53.1 MHz BPF .5 MHz BW

FP Trigger

VXI backplane 8 Channel Trigger Bus

IRQs

Analog Daughter Card

Q

I

TBT Circular Buffer

BPM Plate Signal +

-

Threshold Set DAC

Gain Set DAC

(Revolution Marker, TCLK Events)

Da

ta V

alid

Filte

r Re

se

ts

Reset 6620 filters on marker plus delay Generate IRQ after “n” Data Valids after marker

Com Bus

AD6644DDC & Baseband Filter

65MSPS ADC