Power Planning DMOHANTY

2
POWER PLANNING ASSIGNMENT How power values are defined in .lib files internal_powe r() { related_pin : "B"; rise_power(en ergy_templ ate_7x7) { index_1 ("0.008, 0.04, 0.08, 0.12, 0.16, 0.224, 0.28"); index_2 ("0.01, 0.06, 0.1, 0.15, 0.2, 0.25, 0.3"); values ( \ "0.002557, 0.002618, 0.002627, 0.002631, 0.002634, 0.002636, 0.002636", \ "0.00255, 0.002611, 0.00262, 0.002625, 0.002627, 0.002629, 0.002629", \ "0.00254, 0.002602, 0.002611, 0.002615, 0.002618, 0.00262, 0.00262", \ "0.002531, 0.002594, 0.002602, 0.002607, 0.002609, 0.002611, 0.002612", \ "0.002524, 0.002586, 0.002595, 0.0026, 0.002603, 0.002604, 0.002605", \ "0.002514, 0.002576, 0.002586, 0.002591, 0.002594, 0.002596, 0.002596", \ "0.002507, 0.00257, 0.002581, 0.002586, 0.002588, 0.00259, 0.002591"); } What are ccs models. Accurate delay calculation is critical for timing closure of complex digital designs. At 90nm and below, physical effects present new challenges for delay calculation. T op-level interconnect is becoming more resistive with narrower metal widths, resulting in cases where the interconnect impedance is much greater than the drive resistance of the driving cell. In addition, second order physical effects such as the Miller effect are now  becoming first o rder and must be a ccounted for in the timing analysis. The concern over power in today’s smaller technologies is also presenting new requirements for operation of all or part of the design at lower voltages, increasing the need for analysis over a range of voltages without a unique characterization for each operating point. At 90nm, max allowed slot width = 12un , process requirements is 36un to address EM/IR. What would be the right approach to address this? You need 3 straps of 12 un width to approach the process requirements of 36un DMOHANTY

Transcript of Power Planning DMOHANTY

Page 1: Power Planning DMOHANTY

 

POWER PLANNING ASSIGNMENT

• How power values are defined in .lib files

internal_power() {related_pin : "B";rise_power(energy_template_7x7) {index_1 ("0.008, 0.04, 0.08, 0.12, 0.16, 0.224, 0.28");index_2 ("0.01, 0.06, 0.1, 0.15, 0.2, 0.25, 0.3");values ( \"0.002557, 0.002618, 0.002627, 0.002631, 0.002634, 0.002636, 0.002636", \"0.00255, 0.002611, 0.00262, 0.002625, 0.002627, 0.002629, 0.002629", \"0.00254, 0.002602, 0.002611, 0.002615, 0.002618, 0.00262, 0.00262", \"0.002531, 0.002594, 0.002602, 0.002607, 0.002609, 0.002611, 0.002612", \"0.002524, 0.002586, 0.002595, 0.0026, 0.002603, 0.002604, 0.002605", \"0.002514, 0.002576, 0.002586, 0.002591, 0.002594, 0.002596, 0.002596", \"0.002507, 0.00257, 0.002581, 0.002586, 0.002588, 0.00259, 0.002591");}

◦ What are ccs models.

▪ Accurate delay calculation is critical for timing closure of complex digitaldesigns.

▪ At 90nm and below, physical effects present new challenges for delaycalculation.

▪ Top-level interconnect is becoming more resistive with narrower metalwidths, resulting in cases where the interconnect impedance is much greater than the drive resistance of the driving cell.

▪ In addition, second order physical effects such as the Miller effect are now becoming first order and must be accounted for in the timing analysis.

▪ The concern over power in today’s smaller technologies is also presentingnew requirements for operation of all or part of the design at lower voltages, increasing the need for analysis over a range of voltages without aunique characterization for each operating point.

• At 90nm, max allowed slot width = 12un , process requirements is 36un to

address EM/IR. What would be the right approach to address this?

◦ You need 3 straps of 12 un width to approach the process requirements of 36un

DMOHANTY

Page 2: Power Planning DMOHANTY

 

POWER PLANNING ASSIGNMENT

• For a 10K gate design with 500 MHz frequency and typical voltage of 1.2V,

die size of 5mmx5mm, tr of 0.3ns, R of 30Ω, having probability of transitions

as 50% and leakage power of 20mW. Calculate Avg. power & Total power.

◦ E(sw)=50% probability of transition in a given time period◦ therefore E(sw)=0.5◦ t=rc;◦ 3ns=30*c◦ therefore c=0.3ns/30◦ c=10pF◦ Total Power is given as:▪ cv2fE(sw) + v.imax(tr+tf/2)f+leakage power ▪ 10pf*(1.2)2*500MHz*0.5+1.2*40mA*0.3ns*500MHz+20mW▪ Total Power = 31mW

▪ Integrating the instantaneous power over the period of interest, the energyEVDD taken from the supply during the transition is given by

▪ EVDD= 0->∞∫I. VDD(t).VDD.dt▪ =VDD. 0->∞∫ CL.(dvout/dt).dt▪ = CL.VDD. 0->VDD∫.dvout▪ = CL.VDD2

◦ Average power = 10pf*(1.2)2=14.5pW

• What is IR Drop ?

IR Drop is the problem of voltage drop of the power and ground due to highcurrent flowing through the power-ground resistive network.

DMOHANTY