Porting NetBSD to the open source LatticeMico32 CPU
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Porting NetBSDon
the open source LatticeMico32 CPU
Yann SionneauM-Labs
@ EHSM 2014
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About me
• Yann Sionneau• Embedded software developer• Working at Sequans Communication• M-Labs contributor• @yannsionneau on twitter• Email: [email protected]
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I’m going to talk about…
How to run NetBSD and EdgeBSD on theMilkymist One
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Agenda
• I) The hardware part: the MMU–What is a MMU and how it works
• II) The software part–How to port NetBSD to a new CPU
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Milkymist One?!
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Milkymist One?!
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Milkymist One?!
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The Milkymist One uses an FPGA
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What’s an FPGA??
• A chip
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FPGA internals
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Milkymist System-on-Chip
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LatticeMico32 CPU
• 32 bits Harvard Architecture RISC• Big Endian• 6 stages• Fully bypassed• Optional configurable I/D caches– Direct mapped or– 2-way set associative
• Wishbone on-chip bus
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LatticeMico32 , Good points
• Small• Portable (works with several FPGA vendors)• Fast (~100 MHz on Slowtanpartan 6)• Actually works• GCC/Binutils/GDB/Qemu/uCLinux/OpenWRT
support• OPEN SOURCE
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LatticeMico32, Bad points
• No Memory Management Unit… yet!
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LatticeMico32, Bad points
• No Memory Management Unit… yet! Done
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Used in…
• Closed source commercial ASICs• Open source projects
• Can achieve 800 MHz in TSMC 90nm standard cell process
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LatticeMico32 pipeline
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What’s a pipeline?
• « In computing, a pipeline is a set of data processing elements connected in series, where the output of one element is the input of the next one. »
-- Pipeline (computing), Wikipedia
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What’s a pipeline?
Data processing element 1
Data processing element 2
Data processing element 3
ININ INOUTOUT
OUT
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What’s a pipeline?
$ cat .bash_history | grep 'cat' | wc -l 6
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What’s a CPU pipeline?
Address
instruction Fetch
instruction Decode
instruction eXecute
Memory load/store
register Write Back
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What’s a CPU pipeline?
A
F
D
X
M
W
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Pipelined instruction executionInstr.
numberPipeline Stage
1 A
2
3
4
Clock cycle 1 2 3 4 5 6 7
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Pipelined instruction executionInstr.
numberPipeline Stage
1 A F
2 A
3
4
Clock cycle 1 2 3 4 5 6 7
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Pipelined instruction executionInstr.
numberPipeline Stage
1 A F D
2 A F
3 A
4
Clock cycle 1 2 3 4 5 6 7
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Pipelined instruction executionInstr.
numberPipeline Stage
1 A F D X
2 A F D
3 A F
4 A
Clock cycle 1 2 3 4 5 6 7
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Pipelined instruction executionInstr.
numberPipeline Stage
1 A F D X M
2 A F D X
3 A F D
4 A F
Clock cycle 1 2 3 4 5 6 7
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Pipelined instruction executionInstr.
numberPipeline Stage
1 A F D X M W
2 A F D X M
3 A F D X
4 A F D
Clock cycle 1 2 3 4 5 6 7
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Pipelined instruction executionInstr.
numberPipeline Stage
1 A F D X M W
2 A F D X M W
3 A F D X M
4 A F D X
Clock cycle 1 2 3 4 5 6 7
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Address
instruction Fetch
instruction Decode
instruction eXecute
Memory load/store
register Write back
InstructionCache
DataCache
Main Memory
CPU Internal
Before
PHYSICAL
ADDRESS
PHYSICAL
ADDRESS
PA
PA
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Address
instruction Fetch
instruction Decode
instruction eXecute
Memory load/store
register Write back
InstructionCache
DataCache
Main Memory
CPU Internal
Memory Management Unit (MMU)
Raising exception
MM
U lo
okup
Cache lookup
After
VIRTUAL ADDRESSES PHYSICAL ADDRESSES
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What’s the MMU’s job?
• Translate « virtual addresses » into « physical addresses »
• Memory protection against unwanted execution of code or data write (e.g. software bug or security issue)– Memory right access management
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Main Memory
Memory Management Unit (MMU)
CPU pipelineVA PA
VA : Virtual AddressPA : Physical Address
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Main Memory
Memory Management Unit (MMU)
CPU pipelineVA PA
VA : Virtual AddressPA : Physical Address
How does the MMU know the VA->PA translation ?
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Main Memory
Memory Management Unit (MMU)
CPU pipelineVA PA
VA : Virtual AddressPA : Physical Address
Page Table
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Main Memory
Memory Management Unit (MMU)
CPU pipelineVA PA
VA : Virtual AddressPA : Physical Address
Page TableWhy « PAGE »?
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Why « Page »?
• 0x00000004 -> 0x10000000• 0x00000005 -> 0x10000001• 0x00000006 -> 0x10000002Etc…
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Why « Page »?
• 0x00000004 -> 0x10000000• 0x00000005 -> 0x10000001• 0x00000006 -> 0x10000002Etc…
This is WRONG!!!
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Why « Page »?
• 0x00000*** -> 0x10000***• 0x00001*** -> 0x10001***• 0x00002*** -> 0x10002***Etc…
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Main Memory
Memory Management Unit (MMU)
CPU pipelineVA PA
VA : Virtual AddressPA : Physical Address
Page Table
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Main Memory
Memory Management Unit (MMU)
CPU pipelineVA PA
VA : Virtual AddressPA : Physical Address
Page Table
TLBTLB : Translation Lookaside Buffer
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Main Memory
Memory Management Unit (MMU)
CPU pipelineVA PA
VA : Virtual AddressPA : Physical Address
Page Table
TLBOperating System
Updates the
Gets information from the
Updates the
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Features?
• Page size–Only 4 kB
32 bits physical address : xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
How many bits of an address indicate the offset within a given page?
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Features?
• Page size–Only 4 kB
32 bits physical address : xxxxxxxx xxxxxxxx xxxx xxxx xxxxxxxx
Page number [31:12]
20 bits
Offset [11:0]
12 bits
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Features?
• 2 TLB (Translation Lookaside Buffer)– ITLB–DTLB
• Each TLB contains 1024 entries–How many bits needed to index the TLB?
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Features?
• 2 TLB (Translation Lookaside Buffer)– ITLB–DTLB
• Each TLB contains 1024 entries–How many bits needed to index the TLB?
10 bits!
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Features?
• No hardware page-tree walker– i.e. TLB is software assisted
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Memory Management Unit
(MMU)
Virtual address
Load or store?
Instruction or Data?
Physical address
Accessgranted/denied
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Memory Management Unit
(MMU)
Virtual address
Load or store?
Instruction or Data?
Physical address
Accessgranted/denied
I don’t know!
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Let’s have a look inside
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Tag [10] Physical page number [20] Read-only [1] Valid [1]
0xABC 0xABC00 0 0
0x280 0xB0001 1 1
0x300 0x00001 0 1
The TLBVA = 0xA0001004
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Tag [10] Physical page number [20] Read-only [1] Valid [1]
0xABC 0xABC00 0 0
0x280 0xB0001 1 1
0x300 0x00001 0 1
The TLBVA = 0xA0001 004
Page number
Offset in the page
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Tag [10] Physical page number [20] Read-only [1] Valid [1]
0xABC 0xABC00 0 0
0x280 0xB0001 1 1
0x300 0x00001 0 1
The TLBVA = 0xA0001 004Page offset = 4
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Tag [10] Physical page number [20] Read-only [1] Valid [1]
0xABC 0xABC00 0 0
0x280 0xB0001 1 1
0x300 0x00001 0 1
The TLBVA = 0xA0001 004Page offset = 4Virtual Page number = 0xA0001
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Tag [10] Physical page number [20] Read-only [1] Valid [1]
0xABC 0xABC00 0 0
0x280 0xB0001 1 1
0x300 0x00001 0 1
The TLBVA = 0xA0001 004Page offset = 4Virtual Page number = 0xA0001
VPN = 0xA0001 1010 0000 0000 0000 0001
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Tag [10] Physical page number [20] Read-only [1] Valid [1]
0xABC 0xABC00 0 0
0x280 0xB0001 1 1
0x300 0x00001 0 1
The TLBVA = 0xA0001 004Page offset = 4Virtual Page number = 0xA0001 TLB index = 1
VPN = 0xA0001 1010 0000 00 00 0000 0001
TLB index, used to select a TLB line
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Tag [10] Physical page number [20] Read-only [1] Valid [1]
0xABC 0xABC00 0 0
0x280 0xB0001 1 1
0x300 0x00001 0 1
The TLBVA = 0xA0001 004Page offset = 4Virtual Page number = 0xA0001 TLB index = 1
VPN = 0xA0001 1010 0000 00 00 0000 0001
TLB index, used to select a TLB line
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Tag [10] Physical page number [20] Read-only [1] Valid [1]
0xABC 0xABC00 0 0
0x280 0xB0001 1 1
0x300 0x00001 0 1
The TLBVA = 0xA0001 004Page offset = 4Virtual Page number = 0xA0001 TLB index = 1
VPN = 0xA0001 1010 0000 00 00 0000 0001
Tag = 0x280 1010 0000 00=
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Tag [10] Physical page number [20] Read-only [1] Valid [1]
0xABC 0xABC00 0 0
0x280 0xB0001 1 1
0x300 0x00001 0 1
The TLBVA = 0xA0001 004Page offset = 4Virtual Page number = 0xA0001 TLB index = 1
VPN = 0xA0001 1010 0000 00 00 0000 0001
Tag = 0x280 1010 0000 00=
Physical page number = 0xB0001
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Tag [10] Physical page number [20] Read-only [1] Valid [1]
0xABC 0xABC00 0 0
0x280 0xB0001 1 1
0x300 0x00001 0 1
The TLBVA = 0xA0001 004Page offset = 4Virtual Page number = 0xA0001 TLB index = 1
VPN = 0xA0001 1010 0000 00 00 0000 0001
Tag = 0x280 1010 0000 00=
Physical page number = 0xB0001Physical Address = 0xB0001004
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Porting NetBSD
• 1°) NetBSD cross compilation toolchain– build.sh– Makefiles here and there– Arch-specific directories
Allows to do:$ ./build.sh -U -m lm32
tools
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Porting NetBSD
• 2°) Support for built-ins in libkern– NetBSD kernel is• Not linked against libgcc• Linked against libkern
– Need to implement basic arithmetic functions emitted by gcc in object code
– Implementation in sys/lib/libkern/arch/lm32
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Porting NetBSD
• 3°) Building my first kernel– Create sys/arch/lm32 and sys/arch/milkymist– Populate• sys/arch/<cpu|soc>/include• sys/arch/<cpu|soc>/conf
– Stub, stub, stub…
Allows to do:$ ./build.sh -m milkymist -U kernel=GENERIC
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Porting NetBSD
• 4°) Write basic console driver for early prints
struct consdev milkymist_com_cons = { […] milkymist_com_cngetc, /* cn_getc: kernel getchar interface */ milkymist_com_cnputc, /* cn_putc: kernel putchar interface */ […]};
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Porting NetBSD
• 5°) Implement exception handlers• 6°) Call milkymist_startup() C code– Initialize console driver • -> consinit() -> milkymist_uart_cnattach()• cn_tab = &milkymist_com_cons;
– Initialiaze virtual memory subsystem• Call MD pmap_bootstrap()
– Let the kernel boot• Call NetBSD MI main()
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Porting NetBSD
• 7°) Implement pmap.9pmap -- machine-dependent portion of the virtual memory system– pmap_bootstrap()– pmap_init, pmap_create, pmap_destroy …– SW managed TLB? -> sys/uvm/pmap/
– used in (PowerPC Booke and LM32)
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Porting NetBSD
• 8°) Implement copyin/copyout• 9°) Implement atomic operations– No atomic instruction RAS (Restartable Atomic
Sequence) CAS (Compare And Swap)– Other atomic ops built around this CAS
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RAS CASint _atomic_cas_32(volatile uint32_t *val, uint32_t old, uint32_t new);_atomic_cas_32:_atomic_cas_ras_start:
lw r4, (r1+0) /* load *val into r4 */bne r4, r2, 1f /* compare r4 (*val) and old (r2) */ sw (r1+0), r3
_atomic_cas_ras_end: 1:
mv r1, r4 /* return (*val) */ret
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Porting NetBSD
• 10°) Add support for interrupts– Write a function to register interrupt handlers
• 11°) Have a running system clock– Write cpu_initclocks()– Write clock irq handler• Call hardclock()
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Other functions to write
• Switch context from one thread to another– cpu_switchto(9)
• Copy data and abort on page fault– kcopy(9)
• Save current context– setfault()
• Low level code to finish up fork() operation– cpu_lwp_fork(9)
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Other functions to write
• Block interrupts to protect critical sections– spl(9)
• Init CPU and print copyright message– cpu_startup(9)
• Determine the root file system device– cpu_rootconf(9)
• Etc…
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Porting NetBSD
• To boot user space– Create dummy ramdisk with /sbin/init– Build kernel with MFS– Insert ramdisk with mdsetimage– Boot it!
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Porting NetBSD
DEMO
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Thank you!
Sébastien Bourdeauducq, Michael Walle, Robert Swindells, Stefan Kristiansson, Lars-Peter Clausen, Pierre Pronchery, Radoslaw Kujawa, Youri Mouton, Matt Thomas, tech-kern@, M-Labs mailing list, and many more
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Questions?
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NetBSD/milkymist Memory Layout
Kernel spaceUser space
0 0xffffffff
0xc0000000
0xc8000000Ram window
User stack
Kernelstack
DDR SDRAM : 128 MB