Pn Junctions Introduction

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    EEE 531: Semiconductor Device Theory I

    EEE 531: Semiconductor Device Theory I

    Instructor: Dragica Vasileska(Notes provided by: Prof. Dieter Schroder)

    Department of Electrical EngineeringArizona State University

    Topic covered: Introduction to some general concepts for PN-

    junctions

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    EEE 531: Semiconductor Device Theory I

    1. PN-junctions - General Consideration:

    PN-junction is a two terminal device. Based on the doping profile, PN-junctions can beseparated into two major categories:

    - step junctions

    - linearly-graded junctions

    p-side n-side

    AD NN

    p-side n-side

    AD NN ax

    Step junction Linearly-graded junction

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    EEE 531: Semiconductor Device Theory I

    (A) Equilibrium analysis of step junctions

    (a) Built-in voltage Vbi:

    (b) Majority- minority carrier

    relationship:

    CE

    VE

    iE

    FE

    biqV

    W)(

    x-qNA

    qND

    )(xV

    x

    biV

    )(E

    xmaxE

    px nx

    +-

    p-side n-side

    ( ) ( )

    ( )[ ]

    [ ]

    =

    ==

    +=

    2200

    0

    0

    lnln

    exp

    exp

    i

    DAT

    i

    npBbi

    BFiip

    BiFin

    niFpFibi

    nNNV

    nnp

    qTkV

    TkEEnp

    TkEEnn

    EEEEqV

    [ ]

    [ ]Tbinp

    Tbipn

    VVnn

    VVpp

    /exp

    /exp

    00

    00

    =

    =

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    EEE 531: Semiconductor Device Theory I

    (c) Depletion region width:

    Solve 1D Poisson equation using depletion charge

    approximation, subject to the following boundary condi-tions:

    p-side:

    n-side:

    Use the continuity of the two solutions at x=0, andcharge neutrality, to obtain the expression for the depletion

    region width W:

    0)()(,)(,0)( ==== pnbinp xExEVxVxV

    ( )202

    )( ps

    Ap xx

    k

    qNxV +

    =

    ( ) bins

    Dn Vxx

    k

    qNxV +

    = 202

    )(

    DA

    biDAs

    nDpA

    np

    pn

    NqN

    VNNkW

    xNxN

    VV

    Wxx)(2)0()0( 0 +=

    =

    ==+

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    EEE 531: Semiconductor Device Theory I

    (d) Maximum electric field:

    The maximum electric field, which occurs at the

    metallurgical junction, is given by:

    (e) Carrier concentration variation:

    )(00max

    DAs

    DA

    x NNk

    WNqN

    dx

    dVE

    +==

    =

    105

    107

    109

    1011

    1013

    1015

    0 0.5 1 1.5 2 2.5 3 3.5

    n [cm-3

    ]

    p [cm-3

    ]

    Concentration

    [cm

    -3]

    Distance [m]

    cmkVE

    cmkVE

    mW

    cmNN

    sim

    DC

    calc

    DA

    /93.8

    /36.9

    23.1

    10

    )max(

    )max(

    315

    =

    ==

    ==

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    EEE 531: Semiconductor Device Theory I

    cmkVEcmkVEmW

    cmNN

    simDCcalc

    DA

    /93.8,/36.9,23.1

    10

    )max()max(

    315

    ===

    ==

    -1015

    -5x1014

    0

    5x1014

    1015

    0 0.5 1 1.5 2 2.5 3 3.5

    (x)/q

    [cm

    -3]

    Distance [m]

    -10

    -8

    -6

    -4

    -2

    0

    0 0.5 1 1.5 2 2.5 3 3.5

    Electricfield[kV/cm]

    Distance [m]

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    EEE 531: Semiconductor Device Theory I

    cmkVEcmkVEmW

    cmNcmN

    simDCcalc

    DA

    /67,/53.49,328.0

    10,10

    )max()max(

    318316

    ===

    ==

    -10

    17

    -5x1016

    0

    5x1016

    1017

    0.6 0.8 1 1.2 1.4

    (x)/q

    [cm

    -

    3]

    Distance [m]

    -70

    -60

    -50

    -40

    -30

    -20

    -10

    0

    10

    0.6 0.8 1 1.2 1.4

    Electricfield[k

    V/cm]

    Distance [m]

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    EEE 531: Semiconductor Device Theory I

    (f) Depletion layer capacitance:

    Consider a p+n, or one-sided junction, for which:

    The depletion layer capacitance is calculated using:

    ( )

    D

    bis

    qN

    VVkW

    m02 =

    02

    0 )(21

    )(2 =

    === sDbi

    bi

    sDDc

    kqN

    VV

    CVV

    kqN

    dV

    dWqN

    dV

    dQ

    C

    m

    m

    VVbi V

    21 C

    DN

    slope1

    Forward biasReverse

    bias

    Measurement setup:

    W dW

    ~

    V

    vac

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    EEE 531: Semiconductor Device Theory I

    (B) Equilibrium analysis of linearly-graded junction:

    (a) Depletion layer width:

    (c) Maximum electric field:

    (d) Depletion layer capacitance:

    Based on accurate numerical simulations, the depletion

    layer capacitance can be more accurately calculated ifVbiis replaced by the gradient voltage Vg:

    ( )3/1

    012

    =qa

    VVkW bis

    m

    ( )

    3/120

    2

    12

    =

    VVqakC

    bi

    s

    m

    0

    2

    max8

    =sk

    qaWE

    =

    30

    2

    8ln

    3

    2

    i

    TsTg

    qn

    VkaVV