PG2 ADRV9009+ULTRASCALE SOM CONNECTOR1 PG3 … · 2019. 5. 3. · 1 19 : pitch-pitch ... phy...
Transcript of PG2 ADRV9009+ULTRASCALE SOM CONNECTOR1 PG3 … · 2019. 5. 3. · 1 19 : pitch-pitch ... phy...
PG10 JTAG,PUSHBUTTONS, SLIDE SWITCHES, LEDS
PG11 UART, FAN, SD CARD, PMOD
PG6 AUDIO CODEC
PG8 10/100/1000 SGMII ETHERNET
PG7 SFP+, QSFP+
PG9 HMC7044
PG11 POWER
PG12 POWER
PG5 DISPLAY PORT, USB3
PG4 FMC HPC
PG3 ADRV9009+ULTRASCALE SOM CONNECTOR2
PG2 ADRV9009+ULTRASCALE SOM CONNECTOR1
1 19
<User Define><User Define><User Define>
: Pitch-pitch StyleVendor StylePACKAGE : N/A-lead N/A N/A-family
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
no_template
ACodeID1:1
02_048950TBD
-
-
-
-
-
<PTD_ENGINEER>
-
-
-
-
REV
2REVISIONS
1
OWNED OR CONTROLLED BY ANALOG DEVICES.THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTSPURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. JP#USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER
8
CONNECTORFUNCTIONCODE DEVICE
2
2
6JUMPER TABLE
4
7
5
A
3
DATE APPROVED
D
B
DESCRIPTION
34
OFFON
5
57
OEM PART# HANDLER
6
C
B
8
SOCKET OEMBK/BD SPEC.P.O SPEC.
A
1
RELAY CONTROL CHART
3 14
C
NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, ORTHIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS
CHECKER
DESIGNER
PTD ENGINEER
TEST ENGINEER
DECIMALS
X.XXX +-0.005X.XX +-0.010
MASTER PROJECT TEMPLATE
TOLERANCES
+-1/32FRACTIONS
+-2SIZE
DDDD
SCHEMATIC
DRAWING NO.
SCALE CODE ID NO.SHEET OF
REV.
DA A
ENV C
L GSE
ODATE
ANGLES
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES
TESTER TEMPLATE
TEMPLATE ENGINEER
HARDWARE SERVICES
HARDWARE SYSTEMS
COMPONENT ENGINEER
TEST PROCESS
HARDWARE RELEASE
* SEE ASSEMBLY INSTRUCTIONS
CONTROL
D
VIN12V0 PG_ALLPG_SOM
JUMPER TO OVERWRITE PG_SOM JUMPER TO OVERWRITE PG_ALL
PHY BACKPLANE
PS
SE ONLY
PHY BACKPLANE
DP RX N/A
REFERENCE RESISTOR FOR DCI
ACTIVE HIGH
3V3 FROM SOM
PLBANK 67, 68 - FMC
SE ONLY
SE ONLY
SE ONLY
SE ONLY
SE ONLY SE ONLY
I2C PROGRAMMING INTERFACE
FMC MALE CONNECTOR
REFERENCE RESISTOR FOR DCI
???
VCCO68
VCCO67
PROVIDED BY CARRIER
BANK 65 - OTHER PERIPHERALS: SFP, QSFP, PCIE
REFERENCE RESISTOR FOR DCIINTERNAL TERMINATION CALIB
SOM CONNECTOR 1
PROVIDED BY SOM
CARRIER -----> SOM -----> CARRIER -----> SOMPOWER_GOOD NEGOTIATION
VCCO_65 - 1V8_SOM IS LOOPED BACK FROM TEH SOM BANK 65
PROVIDED BY SOM
I2C0
I2C1
CROSSOVER
2 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
ASP-134488-01
100100
ASP-134488-01
240
ASP-134488-01
1MEG
DNI
1MEG
10K
ASP-134488-01
240ASP-134488-01 ASP-134488-01ASP-134488-01
10K
ASP-134488-01
240
ASP-134488-01 ASP-134488-01
499
R293R292
P12P12P12P12P12P12
P12 P12 P12 P12
R278R277
R241
P20
R224
R223
R225
P18
R240
P19
R239
USB_UART_RXD
USB3_CH1_SET1USB3_CH1_SET2USB3_CH2_SET1
SDA_ADM1166_3V3
I2C1_SCLI2C1_SDA
USB_UART_TXD
ETH_MD1_N
PS_DONE
ETH0_MDC
DPAUX_DATA_OUT
I2C_EXP_RESETB
JTAG_TMSJTAG_FPGA_TDO
JTAG_FPGA_TDI
SDIO_SEL
VADJ_SNS_PVADJ_SNS_N
FMC_HPC_LA24_P
PB_GPIO_2
FMC_VADJ
DIP_GPIO_1
PCIE_PERST
FMC_HPC_LA02_N
SDIO_CARRIER_DAT1SDIO_CARRIER_DAT0
USB3_GTR_RX_NUSB3_GTR_TX_P
PS_MODE3_503PS_MODE2_503PS_MODE1_503PS_MODE0_503USB_OTG_CPENUSB_VBUS_OTGUSB_ID
USB_OTG_NUSB_OTG_P
DP0_GTR_TX_NDP0_GTR_TX_P
DP1_GTR_TX_NDP1_GTR_TX_P
USB3_GTR_TX_N
SGMII0_GTR_TX_NSGMII0_GTR_TX_P
SGMII0_GTR_RX_P
FMC_HPC_LA31_P
VDDA3P8_SNS_PVDDA3P8_SNS_N3V3_SNS_P3V3_SNS_N
5V0_SNS_P5V0_SNS_N
1V8_SOM
1V8_SOM
SGMII0_GTR_RX_N
PG_CARRIER
VREG_ADP5054
PG_ALL
1V8_SOM
EN_PWR_CAR
FMC_VREFA_M2C
USB3_CH2_SET2
VIN_12V0
QSFP_INTL
ETH_PHY_LED0
FMC_HPC_LA15_P
FMC_HPC_LA25_N
FMC_HPC_LA21_N
FMC_HPC_LA11_P
FMC_HPC_LA15_N
FMC_HPC_LA19_PFMC_HPC_LA19_N
FMC_HPC_LA21_P
FMC_HPC_LA32_NFMC_HPC_LA11_N
FMC_HPC_CLK0_M2C_PFMC_HPC_CLK0_M2C_N
FMC_HPC_LA30_P
FMC_HPC_LA32_P
PMOD0_D0
PMOD0_D3
FMC_HPC_LA13_NFMC_HPC_LA13_P
DIP_GPIO_0
DIP_GPIO_2
FMC_HPC_LA26_NFMC_HPC_LA26_P
FMC_HPC_LA01_N_CCFMC_HPC_LA01_P_CC
PB_GPIO_3
PB_GPIO_1PB_GPIO_0
FMC_HPC_LA06_PFMC_HPC_LA06_N
FMC_HPC_LA10_PFMC_HPC_LA10_N
PMOD0_D1
PMOD0_D2
DIP_GPIO_3
FMC_HPC_LA14_NFMC_HPC_LA14_P
FMC_HPC_LA23_PFMC_HPC_LA23_N
FMC_HPC_LA22_N
PMOD0_D5PMOD0_D4
FMC_HPC_LA30_N
PMOD0_D7PMOD0_D6
FMC_VREFA_M2C
FMC_HPC_LA22_P
FMC_HPC_LA09_NFMC_HPC_LA09_P
FMC_HPC_LA05_PFMC_HPC_LA05_N
FMC_HPC_LA27_NFMC_HPC_LA27_P
FMC_HPC_LA17_P_CCFMC_HPC_LA17_N_CC
FMC_HPC_LA18_N_CCFMC_HPC_LA18_P_CC
FMC_HPC_LA28_PFMC_HPC_LA28_N
FMC_HPC_CLK1_M2C_N
ETH0_MDIO
DPAUX_HPD
1V8_SOM
SCL_ADM1166_3V3SDA_ADM1166_3V3
PG_SOM
PG_ALLPG_SOM
FMC_HPC_LA16_NFMC_HPC_LA16_P
PS_SRST_BPS_PROG_B
VCC_PSBATT
ETH_MD2_N
ETH_MD3_PETH_MD3_N
ETH_MD4_PETH_MD4_N
PS_ERROR_OUTETH_PHY_LED1
PS_INIT_B
PS_ERROR_STATUS
FMC_HPC_LA33_NFMC_HPC_LA33_P
FMC_HPC_LA25_P
PCIE_WAKE_B
I2S_LRCLK
FMC_HPC_LA29_N
FMC_HPC_LA31_N
FAN_TACHFAN_PWM
QSFP_MODPRSL
FMC_HPC_LA29_P
DPAUX_DATA_OEDPAUX_DATA_INETH0_RESET_B
QSFP_LPMODE
FMC_HPC_LA07_NFMC_HPC_LA07_P
FMC_HPC_LA00_P_CC
QSFP_RESETL
FMC_HPC_LA08_P
FMC_HPC_LA00_N_CC
FMC_HPC_LA08_N
LED_GPIO_3LED_GPIO_2
LED_GPIO_1LED_GPIO_0
ETH_MD1_P
USB3_GTR_RX_P
FMC_HPC_LA12_P
FMC_HPC_LA04_P
FMC_HPC_LA20_NFMC_HPC_LA20_P
FMC_HPC_LA03_PFMC_HPC_LA03_N
FMC_HPC_LA24_N
FMC_HPC_LA04_N
I2S_SDATA_OUTSFP/QSFP_REC_CLK_NSFP/QSFP_REC_CLK_P
FMC_HPC_CLK1_M2C_P
I2S_BCLKI2S_MCLK
REFCLK_AD9545_NREFCLK_AD9545_P
FMC_VADJ
FMC_HPC_LA12_N
SFP+_TX_DISABLE
I2S_SDATA_IN
1V8_SOM
FMC_HPC_LA02_P
ETH_MD2_P
SCL_ADM1166_3V3
JTAG_TCK
SDIO_CARRIER_CMDSDIO_CARRIER_CLKSDIO_CARRIER_CD
SDIO_CARRIER_DAT2SDIO_CARRIER_DAT3
K28
D13
D10
D19
D35D34
D16D17
D26
D38
D32
D30
B39C39
D22
J13
E6
G11F12F11F10
G9J9G10H10
H17H16
H20
J15
K17
K22K23
K25
K31
K33
D14
C11
D2
B6
A4A5
A10
A34
A32
A25
A33
A31
A37A36
A24
A35
A23
A1
A8
A30
A40A39A38
A29A28A27A26
A18A17A16
A13A12
A9
A7
A2
A14A15
A22A21A20
A11
A19
A3
A6C7
C15
C9
C18C19
C21C22C23
B40
B28B27
B25 23
B13
3
D9
B34
C31C30
D39D40
B38
B14
J40
K30
K36
B18
B20
C4B5
B19
B7
G40
K35
C33
D1
K4
D28
D31
B4
J28
B3
2
32
B32
C40
1
B33
D29
C38
B2
B35
K32
K34
K37
K11
K29
K26K27
K21K20K19
J14
J21
J35J36
J39
J34
H5
H21
H28
H30H31H32
J37J38
H22
G1
G4G3
H6
G8
H18
H13
J4J3
G18G19G20G21G22G23G24
G28
G31G30
G32G33
G36G37
G39G38 F38
F39
F35
F26F27F28F29F30F31
F37F36
E1E2
E5
E3E4
E7E8E9E10E11E12E13
E29
E33E34E35E36
E40E39E38E37
E21
E15E14
E32
E16E17E18
E20E19
E26
E31E30
F32
G34
B1
H1H2
H9
J20
J27
H36H37
H33H34
H39H38
F6F7F8F9
F13F14F15F16F17F18F19F20F21F22F23F24F25
E22E23E24E25
G35
J26
J22J23J24J25
H3
H12H11
H7
H24H25H26
G17
G14G13G12
G7G6G5
G2
G15G16
G25G26G27
G29
F1F2F3F4F5
F33F34
F40
E27E28
B23
H40
J30J29
K2
K12K13
D4
K38K39K40
D3
D6
D18
D20
D23
D37D36
D21
D33
1
C37
1
C28C29
C27C26C25
C16
C12
C10
C8
C34
C24
C20
C35C36
C32
B16B17
B8B9B10B11B12
B37B36
B31B30B29
H35
B26
B22B21
B24
B15
H27
K3
K18
K16
J5J6
H15
H4
H14
J33
D27
D24D25
K8
J16
D7
C5
C3C2C1
J2
H8
H23
H19
D11
C17
C6
C14D15
K15
K10
H29
K14
K9J10
J8
J1
K24
J11
J7
J17
J19J18
K7K6
J12
K5
K1
C13
J31J32
D12
D8
D5
GNDGND
GND
GND
GND
GND
GND
GND
GNDGNDGNDGND
GND
GND
GNDGND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
SOM CONNECTOR 2 FMC MALE CONNECTOR
3 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
ASP-134488-01
ASP-134488-01 ASP-134488-01ASP-134488-01ASP-134488-01
ASP-134488-01 ASP-134488-01
ASP-134488-01 ASP-134488-01
ASP-134488-01
P14P14
P14 P14 P14 P14 P14P14
P14P14
FMC_HPC_GBTCLK1_M2C_P
AUX_SYNTH_OUT_B
GPIO_5_A
AUX_SYNTH_VTUNE_A
FMC_HPC_DP6_M2C_N
QSFP_TX1_P
TX1_ENABLE_A
1V8_SOMSPI_CLKSPI_MISOSPI_MOSISPI_CSN_HMC7044_CAR
GPIO_3_HMC7044_CARGPIO_2_HMC7044_CARGPIO_1_HMC7044_CARRESET_HMC7044_CARRESETB_AD9545
I2C1_SDAI2C1_SCL
TX2_ENABLE_A
TX1_ENABLE_B
RX1_ENABLE_BGPIO_17_BGPIO_16_BGPIO_15_BGPIO_14_BGPIO_13_BGPIO_12_BGPIO_11_BGPIO_10_BGPIO_9_BGPIO_8_B
GPIO_6_BGPIO_5_BGPIO_4_BGPIO_3_BGPIO_2_BGPIO_1_BPWR_FAULT2
RF_SYNTH_VTUNE_B
REFCLK_OUT1_N
TCXO_CLK_SOM_PTCXO_CLK_SOM_N
GPIO_3P3_1_B
GPIO_3P3_2_A
FMC_HPC_DP6_C2M_PFMC_HPC_DP6_C2M_N
FMC_HPC_DP2_M2C_PFMC_HPC_DP2_M2C_N
SFP_REFCLK_PSFP_REFCLK_N
FMC_HPC_DP3_M2C_N
QSFP_REFCLK_NFMC_HPC_DP1_M2C_P
FMC_HPC_DP3_M2C_P
ETH_REFCLK2_N
FMC_HPC_DP7_C2M_P
ETH_REFCLK1_P
FMC_HPC_DP0_C2M_P
FMC_HPC_DP7_C2M_N
FMC_HPC_DP8_C2M_NFMC_HPC_DP8_C2M_P
REFCLK_OUT1_P
FMC_HPC_DP5_C2M_NFMC_HPC_DP5_C2M_P
QSFP_TX3_N
FMC_HPC_DP9_C2M_PFMC_HPC_DP9_C2M_N
AUXADC_3_B
AUX_SYNTH_VTUNE_B
FMC_HPC_DP5_M2C_N
GPIO_7_A
GPIO_3P3_3_A
GPIO_3P3_0_A
SYNC_OUT1
GPIO_16_A
GPIO_14_A
GPIO_9_A
GPIO_3P3_1_A
AUXADC_2_B
AUXADC_1_BAUXADC_0_B
GPIO_3P3_0_B
GPIO_1_AGPIO_2_AGPIO_3_A
GPIO_6_A
GPIO_8_A
GPIO_10_A
GPIO_3P3_5_BGPIO_3P3_4_B
GPIO_11_A
GPIO_0_A
GPIO_3P3_11_B
GPIO_3P3_8_AGPIO_3P3_9_A
GPIO_3P3_11_AGPIO_3P3_10_A
AUXADC_2_AAUXADC_1_A
AUXADC_3_A
AUXADC_0_ARF_SYNTH_VTUNE_A
GPIO_3P3_2_B
SFP+_RX_PFMC_HPC_GBTCLK0_M2C_N
1V8_SOM
SFP+_TX_PSFP+_RX_N
FMC_HPC_DP8_M2C_PFMC_HPC_DP8_M2C_N
FMC_HPC_DP0_C2M_N
QSFP_RX2_NQSFP_RX2_P
FMC_HPC_DP0_M2C_NFMC_HPC_DP0_M2C_P
FMC_HPC_DP1_M2C_N
FMC_HPC_DP4_M2C_NFMC_HPC_DP4_M2C_P
FMC_HPC_DP4_C2M_NFMC_HPC_DP3_C2M_P
FMC_HPC_DP7_M2C_P
FMC_HPC_DP2_C2M_P
FMC_HPC_GBTCLK1_M2C_N
QSFP_RX1_P
QSFP_TX4_N
QSFP_RX4_N QSFP_RX3_N
QSFP_REFCLK_P
GPIO_7_B
GPIO_3P3_6_A
GPIO_4_HMC7044_CAR
GPIO_3P3_7_BGPIO_3P3_8_B
REFCLK_OUT2_P
PWR_FAULT1
FMC_HPC_DP2_C2M_N
QSFP_RX4_P
SFP+_TX_NFMC_HPC_DP9_M2C_PFMC_HPC_DP9_M2C_N
GPIO_3P3_3_B
FMC_HPC_DP3_C2M_N
FMC_HPC_DP5_M2C_P FMC_HPC_DP6_M2C_P
REFCLK_OUT2_N
GPIO_4_ARX2_ENABLE_A
GPIO_13_A
GPIO_15_A
RX1_ENABLE_AGPIO_17_A
AUX_SYNTH_OUT_A
GPIO_12_A
TX2_ENABLE_B
RX2_ENABLE_B
GPIO_3P3_4_AGPIO_3P3_5_A
GPIO_0_B
GPIO_3P3_6_B
GPIO_3P3_9_BGPIO_3P3_10_B
GPIO_3P3_7_A
GPIO_18_A
GPIO_18_B
PCIE_CLK_QO_NPCIE_CLK_QO_P
PCIE_TX6_NPCIE_TX6_P
PCIE_TX3_NPCIE_TX3_P
QSFP_TX3_P
PCIE_TX0_NPCIE_TX0_P
PCIE_TX7_NPCIE_TX7_P
PCIE_TX4_NPCIE_TX4_P
QSFP_TX2_PQSFP_TX2_N
PCIE_TX1_N
ETH_REFCLK1_N
PCIE_TX1_P
PCIE_RX5_NPCIE_RX5_P
QSFP_RX1_N
PCIE_RX2_NPCIE_RX2_P
PCIE_RX7_NPCIE_RX7_P
PCIE_TX5_N
FMC_HPC_DP4_C2M_P
FMC_HPC_DP7_M2C_N
PCIE_TX5_P
PCIE_TX2_N
QSFP_TX4_P
ETH_REFCLK2_P
PCIE_TX2_P
PCIE_RX6_NPCIE_RX6_P
PCIE_RX3_NPCIE_RX3_P
QSFP_RX3_P
PCIE_RX0_P
PCIE_RX4_NPCIE_RX4_P
PCIE_RX1_NPCIE_RX1_P
QSFP_TX1_N
PCIE_RX0_N
FMC_HPC_GBTCLK0_M2C_P
FMC_HPC_DP1_C2M_PFMC_HPC_DP1_C2M_N
C32
D26
D23
D27
D24
C18C19
D29
H1
G10
F32
F21F20
F17
A28
A16A15A14A13
A27
A21
A6
A32A33A34A35A36A37A38
A23
A29
A1
A7
A12
A17
A20
A2
A4A3
A22
A24
A26A25
A30A31
A40A39
D4
D13C12
D31
D6
D1D2
D8D7
K15
K26
K30
G33
G29
G27
G25
G37
H27
G36
H19H20
H26
J19
J36J35
J40
G35
C17
D15D16
K17
K22
J31J32
K34
D3
C21C22
H36
C20
C30C29C28C27C26C25C24C23
C16C15C14C13
C11C10
B27B26
D22D21
D18
D11
D19D20
D14B15B16
B35
B28
D17
K40
B17
B29
C8
B2
C6
B25
B36
B21
B3
B7
B11
C37
C39
E26
H24
J20
G26
G28
B23
B18
E20
B14
C31 B31B32
C5
C2
B30
B13
C1
D9
D12
K14
K35
G32G31
G20G21G22G23G24
F38E37E38
F28
H32
H39 F39
H21
H23
K36
J23J24J25
J34
J37J38J39
F36F37
K10
H38
D34D35
B19
D33
D36
K27
J33 H33
G38
F33
E31
E36E35E34F34G34
H40
D30
D28
J26
F35
F29
H34
H30H29
H25
H22
J27
J18
J16J17
J28
K25
K38K37
K33
F11
F8F9
F4F5
F14
F19H18H17
H14J15
H10H11
J7
K16
K7H8
G30
B38
K24
F27F26
E40
E33E32
E28E27
E24E23E22
E19E18
E14
E7E6E5
E3E2E1
D40D39D38D37
D32
D25
C38
C36C35C34C33
C7
B39
B37
B33
B24
B22
B20
B12
C3
C40
K2J1
E30
F25
G40
F24
G39
K1
K5K6
G12
G17
J30
F1
F23
K13
K23
E15
G18
H37
K11
F40
E25
E21
E39
J6
J12J13
K9K8
K12
H2H3
H6
H4K3
J2
J5
J3J4
G3
G19
E4F3
G2 F2G1
F6
F12
F16 E16E17
E10E11
J8
H5
H12
G16G15
G11
G8G7
G5G4
F7
F10
F18
E8E9
E12E13
F15
G9
H7
H9
H13
J11J10J9
A5
B8
C4
D10
K32K31
J22J21
H16
J14H15
F13
B10
B6B5B4
C9
A11A10A9A8
D5
K29K28
J29
H31
H35
F31F30
B40
B34
A19A18
B1
B9
K39
K4
K19K20K21
K18
H28
G6
G14
E29
G13
F22
GNDGNDGNDGNDGNDGND
GND GND GND GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
FMC HA/HB CONNECTIONS
4 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
00
0
00
000
00
000
00
0
00
00000
00
00000
0
0000
000
00
0000000
0
00
00000000000000000000
000
000
0
0
00
000
0
JP29JP28
JP90
JP26JP27
JP23JP24JP25
JP21JP22
JP18JP19JP20
JP16JP17
JP15
JP13JP14
JP12JP11JP10JP9JP8
JP40JP41
JP35JP36JP37JP38JP39
JP34
JP30JP31JP32JP33
JP53JP52JP51
JP49JP50
JP48JP47JP46JP45JP44JP43JP42
JP91
JP74JP75
JP73JP72JP71JP70JP69JP68JP67JP66JP65JP64JP63JP62JP61JP60JP59JP58JP57JP56JP55JP54
JP89JP88JP87
JP84JP85JP86
JP83
JP82
JP80JP81
JP77JP78JP79
JP76
RF_SYNTH_VTUNE_A_FMC
TX2_ENABLE_A TX2_ENABLE_A_FMCTX1_ENABLE_A TX1_ENABLE_A_FMC
GPIO_18_A GPIO_18_A_FMC
RX1_ENABLE_A RX1_ENABLE_A_FMCRX2_ENABLE_A RX2_ENABLE_A_FMC
GPIO_15_A GPIO_15_A_FMCGPIO_16_A GPIO_16_A_FMCGPIO_17_A GPIO_17_A_FMC
GPIO_13_A GPIO_13_A_FMCGPIO_14_A GPIO_14_A_FMC
GPIO_10_A GPIO_10_A_FMCGPIO_11_A GPIO_11_A_FMCGPIO_12_A GPIO_12_A_FMC
GPIO_8_A GPIO_8_A_FMCGPIO_9_A GPIO_9_A_FMC
GPIO_7_A GPIO_7_A_FMC
GPIO_5_A GPIO_5_A_FMCGPIO_6_A GPIO_6_A_FMC
GPIO_4_A GPIO_4_A_FMCGPIO_3_A GPIO_3_A_FMCGPIO_2_A GPIO_2_A_FMCGPIO_1_A GPIO_1_A_FMCGPIO_0_A GPIO_0_A_FMC
GPIO_3P3_10_B GPIO_3P3_10_B_FMCGPIO_3P3_11_B GPIO_3P3_11_B_FMC
GPIO_3P3_5_B GPIO_3P3_5_B_FMCGPIO_3P3_6_B GPIO_3P3_6_B_FMCGPIO_3P3_7_B GPIO_3P3_7_B_FMCGPIO_3P3_8_B GPIO_3P3_8_B_FMCGPIO_3P3_9_B GPIO_3P3_9_B_FMC
GPIO_3P3_4_B GPIO_3P3_4_B_FMC
GPIO_3P3_0_B GPIO_3P3_0_B_FMCGPIO_3P3_1_B GPIO_3P3_1_B_FMCGPIO_3P3_2_B GPIO_3P3_2_B_FMCGPIO_3P3_3_B GPIO_3P3_3_B_FMC
GPIO_3P3_11_A GPIO_3P3_11_A_FMCGPIO_3P3_10_A GPIO_3P3_10_A_FMCGPIO_3P3_9_A GPIO_3P3_9_A_FMC
GPIO_3P3_7_A GPIO_3P3_7_A_FMCGPIO_3P3_8_A GPIO_3P3_8_A_FMC
GPIO_3P3_6_A GPIO_3P3_6_A_FMCGPIO_3P3_5_A GPIO_3P3_5_A_FMCGPIO_3P3_4_A GPIO_3P3_4_A_FMCGPIO_3P3_3_A GPIO_3P3_3_A_FMCGPIO_3P3_2_A GPIO_3P3_2_A_FMCGPIO_3P3_1_A GPIO_3P3_1_A_FMCGPIO_3P3_0_A GPIO_3P3_0_A_FMC
GPIO_18_B GPIO_18_B_FMC
TX1_ENABLE_B TX1_ENABLE_B_FMCTX2_ENABLE_B TX2_ENABLE_B_FMC
RX2_ENABLE_B RX2_ENABLE_B_FMCRX1_ENABLE_B RX1_ENABLE_B_FMCGPIO_17_B GPIO_17_B_FMCGPIO_16_B GPIO_16_B_FMCGPIO_15_B GPIO_15_B_FMCGPIO_14_B GPIO_14_B_FMCGPIO_13_B GPIO_13_B_FMCGPIO_12_B GPIO_12_B_FMCGPIO_11_B GPIO_11_B_FMCGPIO_10_B GPIO_10_B_FMCGPIO_9_B GPIO_9_B_FMCGPIO_8_B GPIO_8_B_FMCGPIO_7_B GPIO_7_B_FMCGPIO_6_B GPIO_6_B_FMCGPIO_5_B GPIO_5_B_FMCGPIO_4_B GPIO_4_B_FMCGPIO_3_B GPIO_3_B_FMCGPIO_2_B GPIO_2_B_FMCGPIO_1_B GPIO_1_B_FMCGPIO_0_B GPIO_0_B_FMC
RF_SYNTH_VTUNE_B RF_SYNTH_VTUNE_B_FMCAUX_SYNTH_VTUNE_B AUX_SYNTH_VTUNE_B_FMCAUX_SYNTH_OUT_B AUX_SYNTH_OUT_B_FMC
AUXADC_1_B AUXADC_1_B_FMCAUXADC_2_B AUXADC_2_B_FMCAUXADC_3_B AUXADC_3_B_FMC
AUXADC_0_B AUXADC_0_B_FMC
RF_SYNTH_VTUNE_A
AUX_SYNTH_OUT_A AUX_SYNTH_OUT_A_FMCAUX_SYNTH_VTUNE_A AUX_SYNTH_VTUNE_A_FMC
AUXADC_1_A AUXADC_1_A_FMCAUXADC_2_A AUXADC_2_A_FMCAUXADC_3_A AUXADC_3_A_FMC
AUXADC_0_A AUXADC_0_A_FMC
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
FMC HPC
LPC
- REMOVE THE SOLDER JUMPERS (PAG 5) IF ATTACHING A MEZZANINE CARD
UG571 PG22
JTAG
TBD
NC
LPC
NC
LPC
GA0=0
TBD
ARE OK
ENABLE JTAG MUX
LPC
FMC_VADJ, FMC_12V0, FMC_3V3HIGH WHEN:
FEMALE CONNECTOR
NCGA1=0
NOT USED ON ZCU102
THAT'S USING THESE SIGNALS FOR OTHER PURPOSES
- GA0 AND GA1 ARE HARDCODED 0
- TALISE GPIOS CONNECTED TO FMC HA/HB
- FOR SYNC_OUT2 REMOVE R14 (PAG 12) - FOR SYNC_OUT2 REMOVE AC COUPLING CAPS (PAG 12)
- PG_M2C IS NOT USED ON XILINX BOARDS (ONLY PULL-UP TO 3V3)
5 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
ASP-134486-01ASP-134486-01ASP-134486-01 ASP-134486-01
ASP-134486-01ASP-134486-01
ASP-134486-01
ASP-134486-01
ASP-134486-01
ASP-134486-01
0
4.7K
10K
P1 P1P1
P1
P1
P1P1 P1
P1P1
R21
R20
R22FMC_PG_C2M
GPIO_8_B_FMCGPIO_9_B_FMC
GPIO_10_B_FMC
RF_SYNTH_VTUNE_A_FMC
AUX_SYNTH_VTUNE_A_FMCAUX_SYNTH_OUT_A_FMC
AUXADC_3_A_FMCAUXADC_2_A_FMC
AUXADC_1_A_FMCAUXADC_0_A_FMC
GPIO_11_A_FMCGPIO_10_A_FMC
GPIO_3P3_6_A_FMC
GPIO_3P3_10_B_FMCGPIO_3P3_11_B_FMC
TX2_ENABLE_B_FMC
FMC_HPC_LA17_P_CC
SYNC_OUT2
FMC_HPC_LA23_NFMC_HPC_LA23_P
GPIO_3P3_8_B_FMC
FMC_TDOFMC_TDI
FMC_HPC_LA26_NFMC_HPC_LA26_P
FMC_TCK
FMC_TMS
FMC_HPC_DP0_C2M_N
3V3
FMC_HPC_LA13_N
FMC_HPC_LA05_PFMC_HPC_LA05_N
FMC_HPC_LA18_P_CC
FMC_HPC_LA09_P
FMC_12V0
FMC_HPC_DP9_C2M_N
FMC_HPC_CLK0_M2C_P
FMC_HPC_PRSNT_M2C_L
FMC_HPC_DP1_C2M_P
FMC_HPC_DP2_M2C_P
FMC_HPC_DP8_M2C_NFMC_HPC_DP8_M2C_P
FMC_HPC_DP9_M2C_NFMC_HPC_DP9_M2C_P
FMC_HPC_DP7_M2C_P
FMC_HPC_DP8_C2M_P
FMC_HPC_DP7_C2M_P
FMC_HPC_DP9_C2M_P
FMC_HPC_GBTCLK1_M2C_NFMC_HPC_GBTCLK1_M2C_P
FMC_HPC_DP7_M2C_NFMC_HPC_LA10_P
FMC_HPC_DP6_M2C_PFMC_HPC_DP6_M2C_N
FMC_HPC_SCLFMC_HPC_SDA
FMC_3V3
FMC_12V0
FMC_HPC_CLK0_M2C_N
FMC_HPC_LA02_N
FMC_HPC_LA04_PFMC_HPC_LA04_N
FMC_HPC_GBTCLK0_M2C_NFMC_HPC_GBTCLK0_M2C_P
FMC_HPC_DP0_C2M_P
FMC_HPC_LA18_N_CC
3V3
FMC_HPC_LA32_PFMC_HPC_LA32_N
FMC_HPC_DP5_C2M_PFMC_HPC_DP5_C2M_N
FMC_HPC_DP6_C2M_N
FMC_HPC_LA11_N
FMC_HPC_LA13_P
FMC_HPC_LA28_NFMC_HPC_LA28_P
FMC_HPC_LA25_P
FMC_HPC_LA22_P
FMC_HPC_LA20_P
FMC_HPC_LA00_N_CCFMC_HPC_LA00_P_CC
FMC_HPC_CLK1_M2C_N
FMC_HPC_LA21_N
FMC_VADJ
FMC_HPC_LA15_P
FMC_HPC_LA07_NFMC_HPC_LA07_P
FMC_HPC_LA15_N
FMC_HPC_LA19_N
FMC_HPC_LA30_NFMC_HPC_LA30_P
FMC_HPC_LA24_N
FMC_HPC_LA21_P
FMC_HPC_LA03_PFMC_HPC_LA03_N
FMC_HPC_LA33_P
FMC_HPC_LA25_N
FMC_HPC_LA16_PFMC_HPC_LA16_N
FMC_HPC_LA12_P
FMC_HPC_LA08_N
FMC_HPC_LA22_N
FMC_HPC_CLK1_M2C_P
FMC_HPC_LA33_N
FMC_HPC_LA31_NFMC_HPC_LA31_P
FMC_HPC_LA29_NFMC_HPC_LA29_P
FMC_HPC_LA20_N
FMC_HPC_LA12_N
FMC_HPC_LA08_P
FMC_HPC_LA09_N
FMC_HPC_LA14_N
FMC_HPC_LA06_P
FMC_HPC_DP0_M2C_N
FMC_HPC_DP6_C2M_P
FMC_HPC_DP3_M2C_P
FMC_HPC_DP4_M2C_P
FMC_HPC_DP1_M2C_NFMC_HPC_DP1_M2C_P
FMC_HPC_DP5_M2C_PFMC_HPC_DP5_M2C_N
FMC_HPC_DP3_C2M_PFMC_HPC_DP3_C2M_N
FMC_HPC_DP2_M2C_N
FMC_HPC_DP4_M2C_N
FMC_HPC_DP4_C2M_N
FMC_HPC_DP2_C2M_NFMC_HPC_DP2_C2M_P
FMC_HPC_DP3_M2C_N
FMC_3V3
FMC_VADJ
GPIO_13_B_FMC
GPIO_16_B_FMCGPIO_17_B_FMC
GPIO_15_B_FMC
GPIO_12_B_FMC
RX2_ENABLE_B_FMC
FMC_3V3
FMC_HPC_LA10_N
FMC_HPC_LA11_P
FMC_HPC_LA24_P
GPIO_3P3_11_A_FMCGPIO_3P3_10_A_FMC
FMC_HPC_LA02_P
FMC_HPC_DP4_C2M_P
FMC_HPC_DP8_C2M_N
FMC_VADJ
RX1_ENABLE_B_FMC
GPIO_14_B_FMC
GPIO_3P3_5_B_FMC
GPIO_3P3_7_B_FMCGPIO_3P3_6_B_FMC
FMC_VADJ
FMC_3V3
FMC_HPC_DP7_C2M_N
FMC_HPC_LA17_N_CC
FMC_HPC_LA14_P
FMC_HPC_DP1_C2M_N
FMC_HPC_LA27_PFMC_HPC_LA27_N
FMC_VREFA_M2C
REFCLK_OUT3_P
FMC_HPC_LA06_N
REFCLK_OUT4_PREFCLK_OUT4_N
REFCLK_OUT3_N
GPIO_8_A_FMCGPIO_9_A_FMC
GPIO_6_A_FMC
GPIO_5_A_FMCGPIO_4_A_FMC
GPIO_3_A_FMC
GPIO_7_A_FMC
GPIO_1_A_FMCGPIO_0_A_FMC
GPIO_3P3_9_A_FMCGPIO_3P3_8_A_FMC
GPIO_3P3_7_A_FMC
GPIO_3P3_1_A_FMC
GPIO_3P3_3_A_FMC
GPIO_3P3_5_A_FMCGPIO_3P3_4_A_FMC
GPIO_3P3_0_A_FMC
GPIO_3P3_2_A_FMC
GPIO_12_A_FMCGPIO_13_A_FMC
GPIO_17_A_FMC
RX1_ENABLE_A_FMC
GPIO_14_A_FMCGPIO_15_A_FMC
GPIO_16_A_FMC
TX1_ENABLE_A_FMC
RX2_ENABLE_A_FMC
TX2_ENABLE_A_FMC
FMC_HPC_LA19_P
TX1_ENABLE_B_FMC
GPIO_3P3_0_B_FMCGPIO_3P3_1_B_FMC
GPIO_3P3_2_B_FMCGPIO_3P3_3_B_FMC
GPIO_3P3_4_B_FMC
GPIO_3P3_9_B_FMC
VIN_12V0
GPIO_18_B_FMCGPIO_11_B_FMC
GPIO_18_A_FMC
GPIO_2_A_FMC
FMC_HPC_DP0_M2C_P
FMC_HPC_LA01_P_CCFMC_HPC_LA01_N_CC
GPIO_7_B_FMC
GPIO_0_B_FMCGPIO_1_B_FMC
GPIO_2_B_FMCGPIO_3_B_FMC
GPIO_4_B_FMCGPIO_5_B_FMC
GPIO_6_B_FMC
AUXADC_0_B_FMCAUXADC_1_B_FMC
AUXADC_2_B_FMCAUXADC_3_B_FMC
AUX_SYNTH_OUT_B_FMCAUX_SYNTH_VTUNE_B_FMC
RF_SYNTH_VTUNE_B_FMC
J31
J29
J22
J32
K34
J4
E33E34E35
E31
K3
D34D35
D31
F6
E25
F18
F12
F5
F11
F14
E17
E2
E6
G2
D11
E9
J10K11K12
K17
K24
J20
J8
J3J2
K16
F23
F28F29F30F31
F27
D24
E32
J33
J38
K31
K40
E39
K38
K30
J24J25J26
J39
J23
K29
J17
H11
K33
K28K27
J15
H28
K36
J40
J28
K25
J27
B21
K13
K39
K37
K32
K15
K9
K7K6
K8
K4
H25
J1
J18
E10E11E12
E15
E13
E19
E22
E24E23
E27E28E29E30
E36
E40
E1
E8
J12
F20
E3
D37
F16
B19
B28B29B30B31B32
A12
B3
B10
C40
C33C32C31
C36
H15H16
D5
F8
F2
F24
D2D3
D28
C30
D32
D30
C26
D33
C38
C35
J6J5
H2H1
H4H5
D26
G3
G14
H3
H10
H22
C13
A31A30A29
G8
H36
D1
H39
J21
H23
H40
G15
H17
J7
D25
C27C28
C25
D39
D22C23C24
C22C21
C11C10
B38
B25
C4
A2
B27
B24
B12
A15
B20
A3
A36A37A38
A24
A19A20
A17A18
A21
A4
A6
A22A23
A11
D40
D36
F13
A40B39
G11
G18
G5G4
H6
G1
H7
D9
C20
C29
G6
B17
B15
D20
B14
B8B7A7
A9A10
C19B18
B16
B9
B6
C1C2
C5
C8
B5
B35B36
B23
B13
B4
A14
B1A1
D21
D19D18
E5
D10
D8
H12H13H14
H18
G27G28G29
D17
D12
C17
H27
H29
G36
A33A34A35
B34
G10
G7
D27
D23
D14D13
D15C14
C12
C18
C16C15
A26A27
H24
G35
G19
G13G12
G40
A5
A8
G32
H30
J19
F38
H31
G17
B22
A32
C39A39
H26
F3
F7
F1
J13
H8
K1
G22
H20
G25G24
B37
A13
B2
H9
J11
F26
J30
J14
H32
G38G37
G39
D38
H19
J35
K2
F17
E7
F36F37
F40
F35F34F33F32
F25
F22
H34
C37
B33
F10
D7
D16
C9
C6
C3
A25
B11
G16
H21
G9
G20G21
G23
G26
G30G31
G33G34
H38H37
H35
H33
J36
F9
F21
E4 F4
F19
K5
K18
J34
J16
J37
F39
A28
A16
D29
E37E38
B40
C34
B26
J9
K14
K10
K26
K35
K23
F15E14
E16
E18
D4
D6
E20
K19K20K21K22
C7
E21
E26
GNDVIO_B_M2CGNDHB18_NHB18_PGNDHB15_NHB15_PGNDHB11_NHB11_PGNDHB07_NHB07_PGNDHB01_NHB01_PGNDHA22_NHA22_PGNDHA18_NHA18_PGNDHA14_NHA14_PGNDHA11_NHA11_PGNDHA07_NHA07_PGNDHA03_NHA03_PGNDGNDCLK3_BIDIR_NCLK3_BIDIR_PGND
VADJGNDLA32_NLA32_PGNDLA30_NLA30_PGNDLA28_NLA28_PGNDLA24_NLA24_PGNDLA21_NLA21_PGNDLA19_NLA19_PGNDLA15_NLA15_PGNDLA11_NLA11_PGNDLA07_NLA07_PGNDLA04_NLA04_PGNDLA02_NLA02_PGNDCLK0_M2C_NCLK0_M2C_PGNDPRSNT_M2C_LVREF_A_M2C
GNDVADJGNDLA33_NLA33_PGNDLA31_NLA31_PGNDLA29_NLA29_PGNDLA25_NLA25_PGNDLA22_NLA22_PGNDLA20_NLA20_PGNDLA16_NLA16_PGNDLA12_NLA12_PGNDLA08_NLA08_PGNDLA03_NLA03_PGNDLA00_N_CCLA00_P_CCGNDGNDCLK1_M2C_NCLK1_M2C_PGND
VADJGNDHB20_NHB20_PGNDHB16_NHB16_PGNDHB12_NHB12_PGNDHB08_NHB08_PGNDHB04_NHB04_PGNDHB02_NHB02_PGNDHA19_NHA19_PGNDHA15_NHA15_PGNDHA12_NHA12_PGNDHA08_NHA08_PGNDHA04_NHA04_PGNDHA00_N_CCHA00_P_CCGNDGNDPG_M2C
GNDVADJGNDHB21_NHB21_PGNDHB19_NHB19_PGNDHB13_NHB13_PGNDHB09_NHB09_PGNDHB05_NHB05_PGNDHB03_NHB03_PGNDHA20_NHA20_PGNDHA16_NHA16_PGNDHA13_NHA13_PGNDHA09_NHA09_PGNDHA05_NHA05_PGNDGNDHA01_N_CCHA01_P_CCGND
3P3VGND3P3VGND3P3VGA1TRST_LTMS3P3VAUXTDOTDITCKGNDLA26_NLA26_PGNDLA23_NLA23_PGNDLA17_N_CCLA17_P_CCGNDLA13_NLA13_PGNDLA09_NLA09_PGNDLA05_NLA05_PGNDLA01_N_CCLA01_P_CCGNDGNDGBTCLK0_M2C_NGBTCLK0_M2C_PGNDGNDPG_C2M
GND3P3VGND12P0VGND12P0VGA0GNDGNDSDASCLGNDGNDLA27_NLA27_PGNDGNDLA18_N_CCLA18_P_CCGNDGNDLA14_NLA14_PGNDGNDLA10_NLA10_PGNDGNDLA06_NLA06_PGNDGNDDP0_M2C_NDP0_M2C_PGNDGNDDP0_C2M_NDP0_C2M_PGND
GNDGND
GND
RES0GNDGNDDP6_C2M_NDP6_C2M_PGNDGNDDP7_C2M_NDP7_C2M_PGNDGNDDP8_C2M_NDP8_C2M_PGNDGNDDP9_C2M_NDP9_C2M_PGNDGNDGBTCLK1_M2C_NGBTCLK1_M2C_PGNDGNDDP6_M2C_NDP6_M2C_PGNDGNDDP7_M2C_NDP7_M2C_PGNDGNDDP8_M2C_NDP8_M2C_PGNDGNDDP9_M2C_NDP9_M2C_PGNDGNDCLK_DIR
GND
GNDGNDGNDGNDGND
GND
VIO_B_M2CGNDHB17_N_CCHB17_P_CCGNDHB14_NHB14_PGNDHB10_NHB10_PGNDHB06_N_CCHB06_P_CCGNDHB00_N_CCHB00_P_CCGNDHA23_NHA23_PGNDHA21_NHA21_PGNDHA17_N_CCHA17_P_CCGNDHA10_NHA10_PGNDHA06_NHA06_PGNDHA02_NHA02_PGNDCLK2_BIDIR_NCLK2_BIDIR_PGNDGNDVREF_B_M2C
GNDDP5_C2M_NDP5_C2M_PGNDGNDDP4_C2M_NDP4_C2M_PGNDGNDDP3_C2M_NDP3_C2M_PGNDGNDDP2_C2M_NDP2_C2M_PGNDGNDDP1_C2M_NDP1_C2M_PGNDGNDDP5_M2C_NDP5_M2C_PGNDGNDDP4_M2C_NDP4_M2C_PGNDGNDDP3_M2C_NDP3_M2C_PGNDGNDDP2_M2C_NDP2_M2C_PGNDGNDDP1_M2C_NDP1_M2C_PGND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
CARRIER -> SOMSOM -> CARRIER
SDIO_SEL = OPEN FOR SOM SDSDIO_SEL = GND FOR CARRIER SD
DPAUX GENERATOR
SD CARD
100OHM DIFFERENTIAL LINES. SEE UG583 (ULTASCALE PCB GUIDELINES, PAGE 176
DISPLAYPORT
VOLTAGE TRANSLATORS
6 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
NLSV4T244MUTAG
4.7K 4.7K
SD-RSMT-2-MQ
49.9
49.9
10K
0
0.1UF
0.1UF0.1UF
0.1UF
0.1UF
0.1UF
0.1UF0.1UF
1.1A
47272-0001
0.1UF
1MEG
100K
10
0.1UF
1MEG
DNI
0
1.5K
ADN4691EBRZ
2.49K
0.001UF
100K
100K
RCLAMP7534P.TNT
0.1UF
4.7K
DNI
CL-SB-12B-02T
RCLAMP7534P.TNT
NLSV4T244MUTAG
0.1UF
P15
R31
R32R26
R25
C242 C243
C30
C33
C35
C36
C31
C32
F1R24
U22
R23
C29
C28
R28
C34 R33
P2
R30
R29
U9 R35
D1
R27
R34
R237R235
R236
S9
D2
U21
C114 C241
FMC_TDO_1V8DPAUX_DATA_INDPAUX_HPDPCIE_PERST
SDIO_CARRIER_CLK
3V3
SDIO_CARRIER_DAT1SDIO_CARRIER_DAT2
SDIO_CARRIER_DAT0
SDIO_CARRIER_DAT3
DP0_GTR_TX_P
DPAUX_HPD_3V3
3V3
DP1_GTR_TX_P
DPAUX_C_N
3V3
DP0_GTR_TX_N
1V8_SOM
DPAUX_C_P
DP1_GTR_TX_N
DPAUX_C_N
3V3
3V3
3V3
DPAUX_DATA_OUT_3V3
DPAUX_DATA_IN_3V3DPAUX_DATA_OE_3V3
1V8_SOM1V8_SOM
DPAUX_C_P
SDIO_SELSDIO_CARRIER_CMD
SDIO_CARRIER_CD
PCIE_WAKE_B_3V3
DPAUX_DATA_OE_3V3
PCIE_WAKE_BDPAUX_DATA_OUTDPAUX_DATA_OE
FMC_TDO
3V3
DPAUX_DATA_OUT_3V3
1V8_SOM
PCIE_PERST_3V3DPAUX_HPD_3V3DPAUX_DATA_IN_3V3
11
3
7
1
4
6
PAD2PAD1
1098
5
2
1615
SH3
6
2
20
12
18
14
1
87
4
19
13
SH4
17
3
5
SH1
9
SH2
1011
GND
GND
GND
SHLD
OE_N
B1B2B3B4
A4A3A2A1
VCCBVCCA
GND
GND
GND
GND
GND
GNDGND
GND
OE_N
B1B2B3B4
A4A3A2A1
VCCBVCCA
GND
GND
GND
GND
GND
GND
VCC
BA
GNDDIDE
RE_NRO
GNDGND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
DLW21HN900SQ2LUSB 3.0 AC COUPLING FOR TX
0 0 HIGH CURRENT MODE 1 0 MEDIUM CURRENT MODE
OUT2 OUT1
1 1 DEFAULT CURRENT MODE
I2C MODE ADR 0X3A
USB 2.0 - 90 OHMS DIFFERENTIAL IMPEDANCEUSB 3.0 - 100 OHMS DIFFERENTIAL IMPEDANCE
POWER + DATA USB
MAX STUB LENGHT ON D+/D_ 2.5MM
USB 3.1USB3.1 MUX
DEFAULT MODE DRP
7 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
4.7UFADP198ACBZ-11 DNI2.2UF
4.7K
10K
10K
10K10K
10K
10K
DNI
DNI
0.1UF
0.1UF
0.1UF
0DNI
4.7K
4.7K
4.7K
PTN5150AHXMP
0.01UF
12401598E4#2A
1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
4.7K
4.7K4.7K
TCA9548ARGER
4.7K
4.7K
4.7K
4.7KDNI
4.7K
DNI4.7K
4.7K
0
DNI4.7K
0
RCLAMP7534P.TNT
90OHMS AT 100MEGHZ
RCLAMP7534P.TNT
0.001UF
DNI
0
PTN36043BXY
0
DNI
4.7K 4.7K
4.7K4.7KC205
R212
R197
R192 R193
R191
R195
C203
C199
C202
R194
R196
C281
U20
R189R188
R181
C204
R186
C201
C208
C207
C206
C211
C210
C209
R176
R177
R180
R187R184R178
R172
C200
R169
R170
TP27 TP28
U8
D8
L6
D9
M3
TP26TP25TP22
TP24
TP23
U7
U19
R190
R182R179
R185R183
R175
R173
R174
R171FMC_3V3
FMC_3V3
SFP+_I2C_SCL_3V3
USB_OTG_CPEN
QSFP_I2C_SCL_3V3I2C1_SCL_PTN5150
USB_C_TX1_P
I2C1_SCL_AUDIO
USB_C_CC1
1V8_SOM
VBUS
USB_C_SEL_MUX
USB3_GTR_TX_N
3V3
FMC_HPC_SDA
5V0
I2C1_SCL_AD9545
USB_ID
3V3
USB3_CH2_SET2USB3_CH2_SET1USB3_CH1_SET2
USB3_GTR_TX_PUSB_C_CC1
VBUS
3V3
USB_C_TX1_N
USB_SHIELD
USB3_GTR_RX_P
USB_C_TX2_N
USB_C_TX1_N
USB3_GTR_RX_N
USB_C_TX2_P
USB_C_TX1_P
VBUS
3V3
USB_C_CC2
I2C1_SDA_PTN5150
I2C_EXP_RESETB
I2C1_SCL
I2C1_SDA_AUDIOI2C1_SDA_AD9545
1V8_SOM
I2C1_SCL_PTN5150
USB3_CH1_SET1USB_C_SEL_MUX
USB_C_RX2_N
QSFP_I2C_SDA_3V3SFP+_I2C_SDA_3V3
USB_C_TX2_P
I2C1_SDA
3V3
FMC_HPC_SCL
1V8_SOM
1V8_SOM
1V8_SOM
USB_C_RX2_PUSB_C_RX2_N
USB_C_TX2_N
USB_OTG_P
USB_OTG_N
1V8_SOM
USB_C_RX2_PUSB_C_RX1_NUSB_C_RX1_P
USB_VBUS_OTG
1V8_SOM
I2C1_SDA_PTN5150
USB_C_CC2
USB_C_RX1_NUSB_C_RX1_P
A2
B2
A11
B1
817
14
B12
A1
12
9
2
SH1
16
11
13
18
12
5
11
4
3
PAD
10
1
67
58
4 1
10
3
2
6
A1
79
A5
B10
B5B6B7
B11
B4
B9
A7A6
A4
A9A8
A12
SH2
A3A2
B1
A10
B2
SH4SH3
B3
B8
15
GND
GND GND
GND
GND
TX_CON_2-TX_CON_2+TX_AP_-
TX_AP_+
SEL
RX_AP_-RX_AP_+
GND
CH2_SET1CH2_SET2
RX_CON_2-RX_CON_2+
TX_CON_1-TX_CON_1+
VDD1V8
CH1_SET2
RX_CON_1-RX_CON_1+
CH1_SET1
GND
GND
GND
GND
SH4SH3SH2SH1
GNDTX2+TX2-
VBUSCC2D+D-
SBU2VBUSRX1-RX1+GND
GNDRX2+RX2-VBUSSBU1
D-D+
CC1VBUSTX1-TX1+GND
ENGND
VOUTVIN
GND
VDD
EXT_SEL
CC1VBUS_DET
SDA/OUT1
GND
SCL/OUT2
ID
INTB/OUT3
ADR/CON_DET
PORT
CC2
GND
GND
GND
GNDGNDGND
GND
PAD
RESET_N
A1A0
VCC
SDASCL
A2SC7
SD7
SC6
SD6
SC5
SD5
SC4
SD4
GND
SC3
SD3
SC2
SD2
SC1
SD1
SC0
SD0
GNDD
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
STEREO SINGLE-ENDED INPUT
I2C MODE ADR 0X70
AUDIO CODEC
HEADPHONE OUTPUT
DIFFERENTIAL INPUT
STEREO SINGLE-ENDED OUTPUT
8 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
ADAU1761BCPZ
1K49.9
0.1UF
25K
10UF
0
0
0
0
0
0
DNI
DNI
DNI
1K
1K
1K
10K 10K
10UF
()
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
1UF
0.1UF
0.1UFDNI
0.1UFDNI
0.1UFDNI
0.1UFDNI
0.1UF
0.1UF0.1UF
0.1UF
2K
120OHM
220UF
220UFSTX-4235-3/3-N
20K
49.9K
20K
49.9K
2K 69157-102
100
100
STX-4235-3/3-N
STX-4235-3/3-N
STX-4235-3/3-N
R40
R39
R37
C45
C48
C49
C47
C46
R50
R51
R58
R57
R56
R46
R52
R53
R38
R47R43
C43
C38
C53
C50
C54
C39C37
C55
C52 C58
C51 C57
C44
C42C41
C40
U2
E3
C59
C56
R54
R55
R48
R49
R44
R45
R41
R42
P5
P5
JP1
P6
P6
I2S_SDATA_INI2S_MCLK
RAUXRINN
LINN
LAUX
LHP1V8_SOM
ROUTPRHPMONOOUT
LOUTP
1V8_SOM
I2S_LRCLKI2S_SDATA_OUT
I2C1_SDA_AUDIO
RINN
I2S_BCLK
I2C1_SCL_AUDIO
ROUTP
LINN
LAUX
RAUX
LOUTP
MICBIAS
AUD_1V8
VDDA1P8
AUD_1V8
1V8_SOM
MONOOUT
RHP
LHP
MICBIAS
1314
32
283
11
1912
15
1810
7
31
29
17
4
2021
8 23
16
30
24 1
27
25
26
6
9
5
PAD22
2
NP
NP
5A
2A
1A
1 2
1B
2B
5B
1A
2A
5A
1B
2B
5B
GNDGND
GNDGND
PAD
SCL/CCLK
SDA/COUT
ADDR1/CDATALRCLK/GPIO3
BCLK/GPIO2
DAC_SDATA/GPIO0
ADC_SDATA/GPIO1
DGND
DVDD
OUT
MONOOUTLHP
RHP
LOUTPLOUTN
ROUTNROUTPRAUX
RINNRINPLINNLINP
AGND
AVDD
CM
LAUX
MICBIAS
JACKDET/MICIN
ADDR0/CLATCH_N
MCLK
IOVD
D
GND
GND
GND
GNDGND
GND
GND
GND
GNDGNDGND
GNDGNDGND
GND
GND
GNDGND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
SFP+, QSFP+
LOAD JUMPER TO ENABLE SFP+
SFP+ CAGE
DEFAULT HIGH-POWER MODE
PULL-UP IN MODULE
MODSELL = '0' I2C ALWAYS ENABLED
PULL-UP IN MODULE
9 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
4.7K
BSS138TA
4.7UH
0.1UF
1UH
0.1UF
22UF 0.1UF
4.7K4.7K
DNI
DNI
4.7K4.7K
4.7K4.7K
10K
74LVC2G07GV,125
10K
DNI0.1UF
0.1UFDNI
4.7K
4.7K
0.1UF22UF 22UF22UF
DNI
74LVC2G07GV,125
4.7K
4.7K
4.7K
DNI
0.1UF
0.1UF
22UF
22UF
4.7UH
1888247-1
1UH
1UH
FS1-R38-20A2-10
2007194-1
R203 R205 R207
Q3
C249
C245
C254 R206C255
L11
R204
C253
R201
R202
R199
R198
R113
C252
U23
C246 C247 C248
R200
TP38
C250 C251
R110
R111 R112
C256 C257
C244
M4
U24
L9
L8
L7
L10 P13
TP40
TP39
P4
P3
QSFP_MODPRSLSFP+_TX_FAULT_3V3
SFP+_LOS_3V3
SFP+_MOD_DETECT_3V3SFP+_I2C_SCL_3V3
SFP+_LOS_3V3
SFP+_TX_DISABLE
3V3_SFP_RX
SFP+_TX_DISABLE_3V3
3V3_SFP_RX
SFP+_TX_DISABLE_3V3SFP+_I2C_SDA_3V3
SFP+_RS0_3V3
SFP+_RS1_3V3
SFP+_RX_NSFP+_RX_P
3V3_SFP_TX
SFP+_TX_N
SFP+_RS1_3V3
SFP+_MOD_DETECT_3V3
SFP+_RS0_3V3
SFP+_TX_FAULT_3V3
QSFP_INTL
QSFP_RESETL
QSFP_RESETL_3V3
QSFP_LPMODE_3V3
1V8_SOM
QSFP_TX4_PQSFP_TX4_N
PG_ALL
QSFP_I2C_SDA_3V3QSFP_I2C_SCL_3V3
3V3_QSFP_RX
3V3_QSFP
1V8_SOM
QSFP_RESETL_3V3
3V3_QSFP_RX
3V3_QSFPQSFP_LPMODE_3V3
QSFP_RX4_NQSFP_RX4_P
QSFP_RX2_NQSFP_RX2_P
QSFP_RX1_PQSFP_RX1_N
QSFP_TX2_NQSFP_TX2_P
3V3
3V3
QSFP_TX3_P
QSFP_TX1_N
3V3
3V3_SFP_TX
SFP+_TX_P
3V3
3V3_QSFP_TX3V3
3V3
QSFP_LPMODE
1V8_SOM
QSFP_RX3_N
QSFP_INTLQSFP_MODPRSL
QSFP_RX3_P
3V3_QSFP_TX
QSFP_TX3_N
QSFP_TX1_P
10
1
21
19
16
7
18
14
11
5
12
10
24
26
32
23
11
9
15
33
22
73
17
9
6
4
2
20
15
8
13
16
38
27
29
8
5
1
32
4
1718
31
343536
GND
6
121314
21
30
20
37
25
28
19
GND1GND2GND3GND4GND5
GND
6G
ND7
GND
8G
ND9
GND
10
GND11GND12GND13GND14GND15
GND
16G
ND17
GND
18G
ND19
GND
20
GND
CGND
CGND
CGND
CGND
CGND
CGNDCGNDCGNDCGNDCGND
CGND
CGND
CGND
CGND
CGND
CGNDCGNDCGNDCGNDCGND
GND
1Y
VCC2Y
2AGND
1A
GND
GND
GND
1Y
VCC2Y
2AGND
1A
GND
GND
GND
GND
GND
GND
GND
GND
GND
G
S
D
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
CHECK UNUSED DATA LINES
PHY1
ETHERNET
PASSIVE CONN
10 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
BSS138LT1G
1K
220
1K
10K
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
BSS138LT1G
0.1UF
0.1UF
BSS138LT1G
BSS138LT1G
0.1UF 4.7UF
25MEGHZ
88E1512-56QFN
DNI
0.1UF
0.1UF
L0805
51L0805
0.1UF4.7UF 0.1UF 1UF10UF0.1UF
4.99K
0
0.1UF
100OHM220
10K
4.7K
DNI
27PF
0.1UF
0.1UF
51
4.7UF
4.7UF
0.1UF
0.1UF
0
0.1UF
L829-1J1T-43
0.1UF46
0.1UF
27PF
100OHM
0.1UF 1UF
1UF
NC7SZ08FHX
0.1UF
46
1K
46
46
1K
L829-1J1T-43
0.1UFL0805
100OHM
41
0.1UF 0.1UF 0.1UF4.7UF
C93 C95R82
R80
C107
C106
R81
Q8
C94
C87
Y1
R78
U10
R76
C99
C97
U11
R77
C96 C83 C86 C89
C92C84
Q7
Q9
Q10
R79
R75
R85
C72
C81
C74
C78
C77
C75
C76
E5
C98
C70
C73 C79 C82
C80
C85 C91
C90
R84C103
C102
C101
C100
C105
C104
M1
M2
R83
C71
E6
E4
R86
C88
PHY1_VDD_3V3
PHY1_VDD_3V3
PHY1_LED_0
ETH_PHY_LED1
ETH_MD4_N
3V3
ETH_MD3_PETH_MD2_N
ETH_MD1_P
3V3
ETH_PHY_LED0
PHY1_VDD_3V3
ETH0_PHY_LED1
3V3
ETH0_MD4_N
ETH0_MD2_N
ETH0_MD2_P
ETH0_PHY_LED0
ETH0_PHY_LED1
PHY1_VDD_3V3
PHY1_LED_1
PHY1_AVDD_1V8
PHY1_DVDD_1V0
PHY1_AVDD_3V3
PHY1_1V81V8_SOM
ETH0_MD1_P
PHY1_AVDD_1V8_OUT
ETH0_MD1_NETH0_MD4_N
PHY1_LED_1
PHY1_AVDD_1V8
PHY1_DVDD_1V0
SGMII0_GTR_RX_N
1V8_SOM
PHY1_AVDD_1V8PHY1_AVDD_1V8_OUT
PHY1_AVDD_3V3
PHY1_1V8
PHY1_AVDD_1V8
PHY1_AVDD_3V3PHY1_DVDD_1V0
PHY1_VDD_3V3
PHY1_1V8
ETH0_MD2_PETH0_MD2_N
SGMII0_GTR_RX_P
SGMII0_GTR_TX_P
SGMII0_GTR_TX_N
PG_ALL
ETH0_PHY_LED0
ETH0_RESET_B
1V8_SOM
ETH0_MD3_NETH0_MD4_P
ETH0_MD3_P
ETH0_MD1_N
ETH0_MD1_P
ETH_MD4_PETH_MD3_N
PHY1_1V8
ETH_MD1_NETH_MD2_P
ETH0_MD3_N
ETH0_MD3_P
3V3
PHY1_LED_0
ETH0_MDCETH0_MDIO
ETH0_MD4_P
3V3
17
1
14
13
13
SH2
15
9
35
6
130
35
375
34
31
15 16
36
4856 53 51 50 49 47
1 2
42
2
39
32
PAD
22
14
2
46 45
14
26
43
34
2721
7
16
15
10
12
33
40
1
1 2
12
SH2SH1
7
16
25
44
4
3
2
1
1112
10
17 24 2823
29
41
9
52
678
19 20
17
SH1
1
11
4
28
13
6
11
104
53
28
9
38
55 5418
PINSPARE
PINSPARE
PINSPARE
GND
GND
VCC
NC
Y
GNDBA
GND
RJ45
1000pF 2kV
4 X 75OHMS
1CT:1CT
1CT:1CT
1CT:1CT
1CT:1CT
TRP4-(8)
TRP4+(7)
TRP3-(5)
TRP3+(4)
TRP2-(6)
TRP2+(3)
TRP1-(2)
TRP1+(1)
LED2
SHIELDSHIELD
LED1
TRCT1
TRD4-
TRD+
TRD2+TRD1-
TRD2-TRD3+
TRD4+TRD3-
TRCT4
TRCT2
TRCT3
RJ45
1000pF 2kV
4 X 75OHMS
1CT:1CT
1CT:1CT
1CT:1CT
1CT:1CT
TRP4-(8)
TRP4+(7)
TRP3-(5)
TRP3+(4)
TRP2-(6)
TRP2+(3)
TRP1-(2)
TRP1+(1)
LED2
SHIELDSHIELD
LED1
TRCT1
TRD4-
TRD+
TRD2+TRD1-
TRD2-TRD3+
TRD4+TRD3-
TRCT4
TRCT2
TRCT3
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GND
PAD
TX_C
TRL
TXD(
3)TX
D(2)
TX_C
LKVD
DOTX
D(1)
TXD(
0)VD
DORX
D(3)
RXD(
2)RX
_CLK
RXD(
1)RX
D(0)
RX_C
TRL
DVDDREGCAP2
DVDD_OUTAVDD18_OUT
AVDD18REGCAP1
REG_INAVDDC18XTAL_IN
XTAL_OUTHSDACPHSDACN
RSETTSTPT
MDI
P(0)
MDI
N(0)
AVDD
18AV
DD33
MDI
P(1)
MDI
N(1)
MDI
P(2)
MDI
N(2)
AVDD
33AV
DD18
MDI
P(3)
MDI
N(3)
RESE
TNCO
NFIG
LED(0)LED(1)LED(2)/INTNVDDOVDDO_SELCLK125MDIOMDCDVDDS_OUTNS_OUTPAVDD18S_INNS_INP
PINSPARE
GND
GND
GNDGND
GND
PINSPARE
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
PCIE
11 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
0.1UF0.1UF
0.1UF0.1UF
0.1UF0.1UF
0.1UF
0.1UF0.1UF
0.1UF0.1UF
0.1UF0.1UF
0.1UF0.1UF
0.1UF
DNI
DNI
15
DNI
SPC20500
NCFINGER_2X49_PCIE
0.01UF0.01UF
NCFINGER_2X49_PCIE
C275C266
C274C265
C273C264
C269
C268C259
C272C263
C271C262
C270C261
C260
R229
R228
R227
R226
P16
C267C258
P17 P17
PCIE_PRSNT_B
PCIE_TX7_NPCIE_TX7_P
PCIE_TX6_NPCIE_TX6_P
PCIE_TX5_NPCIE_TX5_P
PCIE_TX1_N
PCIE_TX0_NPCIE_TX0_P
PCIE_TX4_NPCIE_TX4_P
PCIE_TX3_NPCIE_TX3_P
PCIE_TX2_NPCIE_TX2_P
PCIE_TX1_P
PCIE_RX1_P
PCIE_RX0_PPCIE_CLK_QO_NPCIE_CLK_QO_P
PCIE_PERST_3V3
PCIE_RX2_N
PCIE_RX0_N
PCIE_RX1_N
PCIE_RX2_P
PCIE_RX3_N
PCIE_RX4_P
PCIE_RX5_N
PCIE_RX6_P
PCIE_RX7_PPCIE_RX7_N
PCIE_RX6_N
PCIE_RX5_P
PCIE_RX4_N
PCIE_RX3_P
PCIE_PRSNT_X1
PCIE_PRSNT_X8
PCIE_PRSNT_X4
PCIE_WAKE_B_3V3
3V3
PCIE_PRSNT_B
PCIE_PRSNT_X1
PCIE_PRSNT_X8
PCIE_PRSNT_X42
6
3
A29
A40
B18
B8
B2
B47
B1
B3
B12B11
B19B20B21
1
A8
A13
A17A18A19
A6
A9
A1A2
4
A47
5
B29B28
B26
B22
B16B15
B13
B10
B17
B4B5B6B7
B9
B14
B23B24B25
B27
B30B31B32B33B34B35B36B37B38B39B40B41B42B43B44B45B46
B48B49
A14
A26
A24
A28
A11A10
A23
A3A4A5
A7
A12
A15A16
A20A21A22
A25
A27
A30A31A32A33A34A35A36A37A38A39
A41A42A43A44A45A46
A48A49
GNDGND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
TALISE FMC CARD
PLACE DECOUPLING CPAS CLOSE TO HMC7044LENGTH MATCH REFCLK_OUT1_P/N, REFCLK_OUT2_P/N, REFCLK_OUT3_P/N, REFCLK_OUT4_P/N
PLACE SERIES RESISTORS NEAR HMC7044LENGTH MAYCH SYNC_OUT1 AND SYNC_OUT2
PLACE DECOUPLING CPAS CLOSE TO HMC7044
HMC7044
TALISE FMC CARD
SOM
SOM
LAYOUT NOTES:
PLACE NEAR OSCILLATOR
LAYOUT NOTES:
LAYOUT NOTES:
PLACE NEAR CONNECTOR
12 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
4.7K4.7K
4.7UF
100
100
49.9
49.9
0.1UF
142-0701-2010
100PF
0.1UFDNI
49.9
49.9
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
1UF
10K
0.1UF
4.7UF
49.9
49.9DNI
0.1UF
0.1UF1UF120OHM
1UF
10K
142-0701-201
4.7UF
0
100
100100
100
100
4.7UF 4.7UF
0.1UF
19.2MEGHZ
DNI
49.9
49.9
0.1UF
0.1UF
DNI0
DNI
11K
0.1UF
DNI0
DNI
430
DNI
4700PF
4700PF 1UF 2.2UF
DNI
142-0701-201
DNI
0
0
0.1UF
DNI
49.9
DNI
DNI
49.9
DNI
49.9
DNI
49.9
0
0
0
DNI0 DNI
0.1UF
DNI
0 DNI
DNI
DNI
49.9
DNI0
DNI
142-0701-201
0.1UF
0
0.1UF
0.1UF
HMC7044LP10BE
49.9
0.1UF
0.1UF
0.1UF
0
0
120OHM
49.9
82PF
CVHD-950X-122.880122.88MEGHZ
100PF2200PF
24
0.1UF10UF
120OHM
0.1UF
0.01UF
0.01UF
0.01UF
0.01UF
0.1UF
0.1UF
DNI
160PF
142-0701-2010.1UF
19.2MEGHZ
R10R9
C2 C6
R5
R11
R14
R13
C240
J6
C308
C307
C236
C291
C279
R253
R250
C10
C7
R6
C4
C5
R8
C3
C9
C282
R231
E18
C278C277C276
R12
J3
C1
R3
R2R7
C8
U1
R234
C283
R233
Y5
C284
R232
C11 C21
R15
C22
R17
R18
TP2
C15C13
C12
R16
TP3
J1
C280
R36
R230J2
J5
C16
R251
R252
R248
C292
R255
R256
R261
R262
R258
C293
C294
R259
C289
R254
R249
C290
R242
R247
R243
R257
C17
C19
R19
TP4
C27
Y2
C26C25C24C23
E2
E1
C286
C287
R260
C18
C14 C20
C285
R1C288
Y4
R4
SYNC_OUT1
REFCLK_OUT4_P
REFCLK_IN_P
VCC5_PLL1
1PPS_SYNC_CK_N
REFCLK_OUT1_N
VCC5_PLL1
REFCLK_IN_N
SFP/QSFP_REC_CLK_P
SPI_CSN_HMC7044_CAR
1PPS_SYNC_CK/RFSYNC_N1PPS_SYNC_CK/RFSYNC_P
OSCIN_EXT
SFP/QSFP_REC_CLK_N
TCXO_CLK_SOM_P
TCXO_VDD
TCXO_CLK_SOM_N
1V8_SOM
RESET_HMC7044_CAR
TCXO_CLK_N
VCCXO_GND
VDDA3P3_VCXO
VCCXO_GND
GPIO_3_HMC7044_CARGPIO_2_HMC7044_CARGPIO_1_HMC7044_CAR
VCCXO_GND
VCCXO_GND
GPIO_4_HMC7044_CAR
SPI_CLKSPI_MOSI
TCXO_CLK_NTCXO_CLK_P
VCC1_VCO
VCC2_OUT
VCC3_SYSREF
VCC4_OUT
VCC9_OUT
TCXO_CLK_P
TCXO_VDD
VCC8_OUT
VCC7_PLL2
VCC6_OSCOUT
CPOUT1
VCC5_PLL1
REFCLK_IN_N
1PPS_SYNC_CK/RFSYNC_P
REFCLK_IN_P
1PPS_SYNC_CK/RFSYNC_N
1PPS_SYNC_CK_P
REFCLK_OUT1_P
VCCXO_GND
VCCXO_GND
OSCIN_EXTCPOUT1
SYNC_OUT2
VDDA3P3_VCXO
SFP_REFCLK_P
SFP_REFCLK_N
QSFP_REFCLK_P
REFCLK_OUT2_P
REFCLK_OUT2_N
REFCLK_OUT3_P
QSFP_REFCLK_N
REFCLK_OUT3_N
REFCLK_OUT4_N
13
22
21
33
56
18
20
1642
38 57 68
34
43
41
1
25
23
14
39
15
4
48
32
49
PAD
5
31
19
63
6
35
17 5110
7
67
46
1112
9 27
6252
26
65
24
45
50
64
44
8
40
3637
47
66
58
61
5960
3
30
55
2829
5354
2
SUP_VOLT
GND GNDOUTPUT
GND SUP_VOLT
GND GNDOUTPUT
GND
GND
GND
GND
GND
GNDGND
GND
PADVC
C9_O
UT
CLKOUT12_NCLKOUT12
SCLKOUT13_NSCLKOUT13
GPIO4GPIO3 SCLKOUT11_N
SCLKOUT11CLKOUT10_N
CLKOUT10
VCC8
_OUT
CLKOUT8_NCLKOUT8
SCLKOUT9_NSCLKOUT9
GPIO2
VCC7
_PLL
2
CPOUT2
LDOBYP7
OSCIN_NOSCIN
LDOBYP6
OSCOUT1_N
OSCOUT1
CLKIN2_N/OSCOUT0_NCLKIN2/OSCOUT0
VCC6
_OSC
OUT
CLKIN0_N/RFSYNCIN_NCLKIN0/RFSYNCIN
VCC5
_PLL
1
CLKIN1_N/FIN_NCLKIN1/FIN
RSV
CLKIN3_NCLKIN3
CPOUT1
GPIO1
SCLKOUT7_NSCLKOUT7
CLKOUT6_NCLKOUT6
VCC4
_OUT
CLKOUT4_NCLKOUT4
SCLKOUT5_NSCLKOUT5
VCC3
_SYS
REF
SDATASCLKSLEN
VCC2
_OUT
CLKOUT2_NCLKOUT2
SCLKOUT3_NSCLKOUT3
LDOBYP5LDOBYP4
VCC1
_VCO
LDOBYP3LDOBYP2
BGABYP1
SYNCRESET
SCLKOUT1_NSCLKOUT1
CLKOUT0_NCLKOUT0
GNDGND
GND
GND
GND
VDDOUTCONTROL
GND
GNDGND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
DECOUPLING HMC7044
13 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
1UF
0.1UF1000PF120OHM
120OHM1000PF 0.1UF
1000PF 0.1UF120OHM
120OHM
120OHM
120OHM
1000PF 0.1UF
1000PF 0.1UF
1000PF 0.1UF
0.01UF 0.1UF
1UF
1000PF 0.1UF120OHM
120OHM1000PF 0.1UF
C226
C227
C228
C237
C238
C239
C225
E10
E11
E12
C222C216
C233
TP34
C230
TP35
E14
E15
C234C231
TP36
C235
C223
C232
E16
C224
C217 C229
C218C212
C219
TP33
C213
C220C214
TP29
TP30
C221C215
TP31
TP32
E9
E13
VDDA3P3_VCO
VCC6_OSCOUT
VDDA3P3_CLKVDDA3P3_CLK
VCC8_OUT
VCC4_OUT
VCC3_SYSREF
VCC9_OUT
VCC2_OUT
VCC7_PLL2
VCC5_PLL1
VCC1_VCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
1PPS SYNCHRONIZATION
ADDRESS 0X4A
CML OUTPUT MODE
CML OUTPUT MODE
I2C
CML OUTPUT MODE
14 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
100K
6.8PF
49.9
0.1UF
NC7SZ126M5X
0.1UF0.1UF 0.1UF 1UF120OHM
10UF
0.1UF
49.9
0.1UF
3900PF
0.1UF1UF1UF0.1UF0.1UF 0.1UF
100K
142-0701-201
100K
0.1UF
100K
0.1UF
6.8PF
100
4.7K
0.1UF
49.152MEGHZ
0.1UF
49.9
49.9
49.9
49.9
0.1UF
49.9
0.1UF
100K
49.9
0.1UF
0.1UF
0.1UF
49.90.1UF
3900PF
AD9545BCPZ
0.22UF
49.910K0.1UF
49.9
R246
C302
R283
R282
R285
C306
C305
R281
C304
C301
R280
R284
C303
R279
C300
C299
C185
R160 R164
E8
C196C195C187 C188 C189 C190 C191 C192
R165
C194 C197
C198
C193
C183
U18R159
U6
R167
C178
J4
Y3
R168
C181
R161
C180
C182
R163
C184
R244
C177 C179
R166
C186
R245
OUT1_B_N
OUT1_B_P
1V8_VDDIOB
1V8_AD9545
1V8_VDDIOB
REFCLK_AD9545_P
VDDA1P81V8_SOM
1V8_AD9545
1V8_AD95451V8_AD9545
1V8_AD9545
1V8_VDDIOB
1V8_AD9545
I2C1_SCL_AD9545I2C1_SDA_AD9545
1V8_AD9545
1V8_VDDIOB
RESETB_AD9545
1V8_VDDIOA
3V31V8_AD9545
OUT1_B_N
1V8_AD9545
REFCLK_AD9545_N
OUT0_A_P
OUT0_A_N
OUT1_A_POUT1_A_N
1PPS_SYNC_CK_P
1PPS_SYNC_CK_N
1V8_SOM
OUT1_A_P
1V8_VDDIOA
OUT1_B_P
1V8_AD9545
OUT0_A_POUT0_A_N
OUT1_A_N
ETH_REFCLK1_P
ETH_REFCLK2_P
ETH_REFCLK2_N
1V8_AD95451V8_AD9545
ETH_REFCLK1_N
1V8_SOM
1V8_SOM
1V8_AD9545
1V8_VDDIOB
241525
2019
6
1413
46PAD
38 373940
8
27
41
36
3231
2 3534
30
1112
444710
45 43 42
28
1
34
7
948
29
26
16 17 18 232221
335
GND GND
GND
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GNDGND
GNDGND
YA
OEVCC
GND
PAD
RESE
TBRE
F_A
REF_
AAVD
D_RE
F_AB NC
VDD_
SYSP
LL
XOB
XOA
VDD_
REF_
CDRE
F_BB
REF_
B M4
M3M2
VDD_IO_BM1M0
VDD_APLL1ALDO_1
LF_1VDD_APLL1BVDD_OUT1_A
OUT1_ANOUT1_AP
VDD_
OUT
1_B
OUT
1_BN
OUT
1_BP
NCVDD_
DIG
NC VDD_
OUT
0_C
OUT
0_CN
OUT
0_CP
OUT
0_BN
OUT
0_BP
VDD_
OUT
0_B
OUT0_ANOUT0_APVDD_OUT0_AVDD_APLL0BLF_0LDO_0VDD_APLL0ACSB/M6SDIO/SDAVDD_IO_ASCLK/SCLSDO/M5
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
TDI
TDO
TDI
TDO
ULTRASCALE CONFIGURATION LEDS
JTAG,ULTRASCALE CONFIGURATION LEDS,PUSH BUTTONS
OPEN-DRAIN, ACTIVE "0"OPEN-DRAIN, ACTIVE "0"
TDOTDI
FMC LPC
TDO
FPGA
TDI
JTAG HDR2 X 10
TDO
TDI
ULTRASCALE MODE SWITCHES
RED_SWITCH
ULTRASCALE RESET BUTTONS
RED_SWITCH
15 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
BSS138LT1G
BSS138LT1GBSS138LT1G
BSS138LT1G
1MEG1MEG1MEG
PTS645SK43SMTR92LFS
330
33010K
330
APT1608SURCK
BSS138LT1G
BSS138LT1G
BSS138LT1GBSS138LT1G
330
BSS138LT1G BSS138LT1G
0.1UF
330
BAT54JFILM
APT1608SURCKAPT1608SURCKAPT1608SURCK
330
499499
499
CL-SB-12B-02T
CL-SB-12B-02T
CL-SB-12B-02T
CL-SB-12B-02T
APT1608SURCK
APT1608SURCK
499
1MEG
499
499
PTS645SK43SMTR92LFS
10K10K
10K
0.1UF0.1UF
330
NLSV4T244MUTAG
330
APT1608SURCK
ADG719BRTZ
APT1608SURCK
87832-1420
C309
U3
Q6
DS7
R288
R289
R217R287
Q5
R222
Q14Q13Q12
R213
Q20Q19 R290
R291
R286 R219
Q4
R221
C69
R220
D3
DS9DS8
P7
S11
R216
R215R211R210
DS6
R208
S10
S13
S14
S15
S16
DS13
DS10 DS11
R209
R214
R264
DS12
Q25
R263
Q26
C68
A1
R218
JTAG_TDOJTAG_TDO
3V3
PWR_FAULT2
PS_DONE
PS_SRST_B
3V3
PG_ALL EN_PWR_CARPS_ERROR_STATUS
1V8_SOM
3V3
PS_PROG_B
3V33V33V3
PS_MODE0_503
PS_MODE1_503
PS_MODE2_503
PS_MODE3_503
3V3
3V33V3
3V3 3V3
PS_INIT_B
PWR_FAULT1
JTAG_TMS
FMC_3V3
FMC_TMSFMC_TCK
1V8_SOM
FMC_TDIFMC_PG_C2M
JTAG_TCKJTAG_FPGA_TDOPG_ALL
PS_ERROR_OUT
JTAG_TCK
JTAG_FPGA_TDO
FMC_TDO_1V8
FMC_HPC_PRSNT_M2C_L
JTAG_TMS
JTAG_FPGA_TDI
1
3
1
22
3
1
2
3
C
A
21
3
13
54
6
14
78
101112
9
GND GND GND GND
GND
S2D
VDD
GND
S1
IN
GND
GND
SPAREPIN
SPAREPIN
GND
OE_N
B1B2B3B4
A4A3A2A1
VCCBVCCA
GND
GNDGND GNDGND
GND
GND
GND
GND
GNDGNDGNDGND
GND
N4N3N1
N2N4N3N1
N2
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
PMOD 1 TRANSLATOR
USER SLIDE SWITCHES
USER PUSH BUTTONS
BLACK_SWITCHBLACK_SWITCH
PMOD 1
BLACK_SWITCHBLACK_SWITCH
USER LEDS
MISCELLANEOUSUART, PMOD, USER LEDS, PUSH BUTTONS, SLIDE SWITCHES
16 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
10K
BSS138LT1G
PPPC062LJBN-RC
33
33
33
33
33
33
33
3333
33
33
33
33
33
0.1UF 0.1UF
3333
FXLA108BQXAPT1608SURCK
4994.7K
CP2103-GM
0.1UF
BSS138LT1G
APT1608LZGCK
EG1218
BSS138LT1G
0.1UF 0.1UF 0.1UF
0.1UF
EG1218
APT1608LZGCK
330
1K
SESD
0201
X1UN
-002
0-09
SESD
0201
X1UN
-002
0-09
47590-0001
1K
PTS645SH50SMTR92LFS
1K 1K1K
330330
0.1UF
0.1UF0.1UF
2.2UF
APT1608LZGCK
10K 10K 10K
10K 10K
10K
0.1UF
10K 10K
10K0.1UF
EG1218
10K
EG1218
SESD
0201
X1UN
-002
0-090.1UF
PTS645SH50SMTR92LFSPTS645SH50SMTR92LFS
PTS645SH50SMTR92LFS
10K
330
BSS138LT1G
APT1608LZGCK
C113
U12
R102R106
R97
R96
R95
R101
R100
R99
R109R105
R104
R103
R108
R107
R98
C112
R94
DS5
S4R74
S3S1
R64 R68
Q18
R62
C61
S2
R67
R60
P10
U4
R88
D4 D5 D6
P8
S5 S6
R66
S7
R69
S8
R73
R162
R90
C65
C110C109
C108
C66C62
C111
DS2
R70R61
R71R63R59
R87
C63 C67
R65
DS4
C60
DS3
C64
R157
R72
R145
DS1
Q17Q16Q15
R151
1V8_SOM
PMOD0_D7_3V3
PMOD0_D4_3V3
PMOD0_D5_3V3
PMOD0_D3_3V3
3V31V8_SOM
PMOD0_D1_3V3PMOD0_D0_3V3
PMOD0_D6
PMOD0_D4
PMOD0_D2
PMOD0_D7
PMOD0_D5
PMOD0_D3
PMOD0_D7_3V3PMOD0_D6_3V3
PMOD0_D4_3V3
PMOD0_D2_3V3PMOD0_D1PMOD0_D0
PMOD0_D6_3V3
3V3
1V8_SOM
USB_UART_RXD
1V8_SOM
DIP_GPIO_3
1V8_SOM1V8_SOM1V8_SOM
1V8_SOM
PMOD0_D2_3V3
1V8_SOM
DIP_GPIO_1
3V3
3V3
PMOD0_D1_3V3PMOD0_D0_3V3
PMOD0_D5_3V3
1V8_SOM
PB_GPIO_1PB_GPIO_3
1V8_SOM
PMOD0_D3_3V3
DIP_GPIO_2
1V8_SOM
USB_UART_TXD
3V3
PB_GPIO_2
DIP_GPIO_0
3V33V3
LED_GPIO_1LED_GPIO_0 LED_GPIO_2 LED_GPIO_3
PB_GPIO_0
1923456789
15141312
1 20
10 PAD
161718
11
4
2422
27
2325
9A
121
1
126
10987
432
115
5 6
8
1112
1
7
16
181928
3
PAD141310 2212015
C
A A
C
A
C
21
SH3SH2SH1
543
431 2
3 314 31
2 1 12 3
17
C
26
32 33
2 4 22 4
1
GND
GND
GNDGND
GND GND GND GND
GNDGND
GND GND
GND
N4N3N1
N2
GND
N4N3N1
N2
GND
N4N3N1
N2
GND
N4N3N1
N2
SGND
DCD
DTR
DSR
TXD
RXD
RTS
CTS
NCNC
GPIO.0GPIO.1GPIO.2GPIO.3
NCNCNC
SUSPENDSUSPEND_N
NC
RST_N
VBUS
REGINVDDVIO D-D+
GND
RI
GND
GND GND
GNDGNDGNDGND
GND
GND GND
GND GND
VCCGNDP10
P9P8P7
VCCGNDP4P3P2P1
GND
PAD
VCCB
OE_NB0B1B2B3B4B5B6B7
GND
A7A6A5A4A3A2A1A0
VCCA
GND
GND GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
POWER ENTRY
POWER INPUT, FAN12V 10A
RESISTIVE DIVIDER TO TRANSLATE TO 1.8V LOGIC INPUT
FAN CONNECTOR
17 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
TS621E-FL11E
47053-1000
MMSD4148T1G
10K
10K
ZXMS6004DGTA
1101M2S3CQE2
39-30-1060
2.7K
BNX016-01
1K
4.7K
BAT54JFILM
10UF
DMP3007SFG-7
1UF
0.1UF
10K
1K
Q1
D7
R91P9
R89
R93
S12
R92
D10
BT1
R238
C116C115
Q11FL1P11
C117
R114
TP5
R115
VIN_12V0
FAN_PWM
FAN_TACH
VIN_12V0
VCC_PSBATT
1V8_SOM
C
A
2
1
4
21
3
4
3
213
6
3
54
12
GND
GND
GND
D DIN
S
GND
GND
GND
GND
D
G
S
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
PARALLEL OPERATION
WITHOUT LDOS
R13838.3K 31.6K
WITH LDOS
3.8V, 2.5A
SAME SCHEMATIC AS SOM
3.3V, 12A
5V, 1.5A
18 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
499
750
R0402L0.001UF
750
R0402L
1K
0.001UF
R0402L
1KR0402L
R0402L
0.001UF
0.001UF
R0402L
R0402L
47UF
1.2UH
47UF
DMG6898LSD-13
0.1
1.2UH
470OHM AT 100MEGHZ
47UF
47UF
L0603L
DNI
100UF 100UF
100UF
41.2K
10UF
10UF
22UF
22UF
63.4K 20K
0DNI
680PF
0.0033UF
93.1K
499K
20K
200K
820PF
1UF
16.2K
20K
20K
100K
13.3K 022PF
69.8K
0.1UF
0.1UF
10K
0.1UF
31.6K
22K
22K
13.3K
0 0.01UF
38.3K
DNI37.4K
DMG6898LSD-13
039PF
47UF
22UH
47UF
100UF
0.1UF
ADP5054ACPZ
6.8UH
1K
1UF
1K
R0402L
3K
R0402L
3K
R0402L
R0402L
R0402L
5.1K
1K
825
R272
R276
C298R274
R265
R269
R270
R266
C297
R275
R273
R271
C295R267
C296R268
P21
TP8
TP11
C143
L4
R135
C140 C141
Q2
C139
R141
C142
E7
R130
C137
C135
R139
TP9
R137
C121
C120
C119
C118
R116
TP6
R120
R118 R122
C125
C124
R117
R119
R121
TP7
R123
C123
C122
R126
R125
R124
C126
R133 R136 C133
C128
C127
R132
C130
R128
R131
R129
C132
R138
R140
Q2
L2
R134 C131
L1
L3
C136
C138
C129
U13
TP10
TP12
R127
C134
5V0_SNS_N
5V0_SNS_P
VADJ_SNS_P
VADJ_SNS_NVDDA3P8_SNS_N
VDDA3P8_SNS_P
3V3_SNS_N
3V3_SNS_P
VADJ_P
3V3_N
VADJ_N
5V0_P
VDDA3P8_N
VDDA3P8_P
3V3_N
5V0
3V3
EN_PWR_CAR
VDDA3P8
VREG_ADP5054
VIN_12V0
5V0
VREG_ADP5054
VDDA3P8
5V0_N
3V3_P
VREG_ADP5054
VDDA3P8_N
3V3_P
VDDA3P8_P
5V0_N
PG_CARRIER
5V0_P
321
7
1
8
2
6
3
4
5
GND
GNDGNDGND
GND
GND
GND
GND
GND
GND
GND
GNDGND
GND
GND
GD
S
GD
S
EPAD
EN3
COMP3
FB3
VREG SYNC/MODE
VDD RT
FB1
COMP1
EN1
PVIN1PVIN1PVIN1
SW1SW1SW1
BST1
DL1
PGND
DL2
BST2
SW2SW2SW2
PVIN2PVIN2PVIN2
EN2
COMP2
FB2
CFG12
PWRGD
FB4COMP4
EN4
CFG34
BST4
PGND4PGND4
SW4SW4
PVIN4
PVIN3
SW3SW3
PGND3PGND3
BST3
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
1V2
1V8
1V5
500KHZ
3.3V, 0.4A
3.3V, 2A
3.3V, 0.4A
ANALOG SUPPLIES
1.8V, 0.4A
FMC VADJ
1.8V DEFAULT, 3A
19 19
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048950
<PTD_ENGINEER>
7.68K
0.1UF
ADP2386ACPZN
ADM7154ACPZ-3.3
100UF
DNI
1200PF
10PF
TBD0402
0
10UF
10UF
100UF
1UF
TBD0402
124K
23.2K
34.8K
23.2K 46.4K
ADP7158ACPZ-3.3-R701UF
0
1UF
ADM7154ACPZ-3.3
1UF
1UF1UF
0
1UF
1UF
1UF
1UF
3.3UH
10UF
()
10UF
()
()
10UF
()
10UF
10UF
()
10UF
()
10UF
10UF
()
22UF
()
22UF
0.1UF
0.1UF0.1UF
0.1UF
TBD0402
TBD0402
ADM7154ACPZ-1.8
10UF
R146
R144
C153
C152
TP15
C163
C162R153
C155
C164
U15
C170
R155
R158
L5
JP7
JP6
JP5
TP17
JP3
JP4
U5
R147
C160
C161
R148 R152JP2
TP18 TP20
TP21
R143C147
C159
U14
C148
C146C144
R154
C175
U17
TP16
C176
C168
R149
TP13
TP14
TP19
U16
C165C145
C169C151
C172
C166
C171
C156
C150
C154 C158
C174
C173C157
C149
R156
R142
R150 C167
VIN_12V0
EN_PWR_CAR
VADJ_P
FMC_VADJ
PG_CARRIER
VDDA1P8
VADJ_N
SW_ADP2386
SW_ADP2386
VDDA3P3_CLK
VDDA3P3_VCXO
VDDA3P8
VDDA3P8
VDDA3P8
VDDA3P3_VCO
VDDA3P8
VDDA3P3_VCXO
VDDA3P8
VDDA3P8
VDDA3P8
VDDA3P3_CLK
VDDA3P3_VCO
15
PAD1
14PAD2
18
23
12
21
2019
8
765
4
3
2
1
22
17
9 10 11 13
16
24
EP
VINVIN
VREG
REFREF_SENSE
EN
BYP
VOUT_SENSE
VOUTVOUT
GNDGND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GNDGND
EP
VINEN
REFREF_SENSE
GND
BYP VOUTVREG
GND
GND
GND
GND
GND
EP
VINEN
REFREF_SENSE
GND
BYP VOUTVREG
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
GND
EP
VINEN
REFREF_SENSE
GND
BYP VOUTVREG
SW
GND
SSSYNCRT
PGOOD
ENPVINPVINPVINPVINBST
SW
PGND
PGND
PGND
PGND
PGND
PGND
SWSWSW
GND
VREG
FB
COMP
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE