Peripheral Simulation Keilc for Lpc 2148

Peripheral Simulation For NXP (founded by Philips) LPC2148 — A/D Converter (6 Channels)

Simulation support for this peripheral or feature is comprised of:

Dialog boxes which display and allow you to change peripheral configuration.

VTREGs (Virtual Target Registers) which support I/O with the peripheral.

These simulation capabilities are described below.

A/D Converter 0 Dialog

The A/D Converter dialog displays the status registers for all of the A/D converters

supported by this device. The Analog Input Channels, listed at the bottom of the dialog,

allow you to specify the voltage for each analog input.

A/D Control

ADnCR (A/D n Control Register) contains the following control bits for the A/D

controller:

CLKS (Conversion Clocks)selects the number of clocks used for each conversion in

Burst mode and the bit accuracy.

START controls when and if the an A/D conversion is started.

SEL selects which pins of the analog input (AINn) are to be sampled and converted.

CLKDIV (Clock Divisor) is the value (minus 1) d ivided into the VPB clock to produce the

A/D Rate.

A/D Clock displays the A/D clock rate.

PDN (Power Down) is set if the A/D is operational. When reset, the A/D is in power

down mode.

BURST is set to use the number of clocks specified in BURST. If reset , conversions are

software controlled and requires 11 clocks.

EDGE is set to start the conversion on a rising edge. If reset, conversion starts on a

falling edge.

A/D Global Data & Status

ADnGDR (A/D n Global Data Register) contains the following bits for controlling A/D

data conversion:

RESULT (Result Value) when DONE is set, contains the voltage input divided by the

voltage reference.

CHN (Channel) is the channel containing the converted bits.

DONE is set when the A/D conversion completes.

ADINT is set when an A/D interrupt occurs.

OVERRUN is set if one or more conversions were overwritten before the current

conversion completed.

A/D Channel Data

ADnDR 0-7 (A/D n Channel Data Registers 0-7) contain the RESULT, DONE and

OVERRUN status for each of the eight channels.

A/D Interrupt Enable

ADnINTEN 0-7 (A/D n Channel Interrupt Enable 0-7) contains the interrupt enable bit

for each of the eight channels(ADINTEN0 - ADINTEN7).

ADGINTEN (A/D Global Interrupt Enable) is set to allow only the DONE flag to trigger

and ADC complete interrupt. When reset, each channel enabled in ADnINTEN can

trigger and ADC complete interrupt.

Analog Inputs

ADn (Analog Data Input Channels n) are used for setting voltage input to the ADC.

These inputs are alternate functions for Port pins. The text box displays the analog

voltage value for each input channel.

ADx VTREG Data Type: float

The ADx VTREGs set the analog input voltages for simulated A/D converters. The ADx

VTREGs represent the inputs to the analog input pins of the MCU for analog input 0, 1, 2,

and so on. AIN0 sets the input voltage for analog input #0, ADC1 sets the input voltage for

analog input #1, etc. If you have properly configured the analog inputs, the following

commands (typed in the debugger's Command Window) input the voltages specified.

AD0 = 0.000 /* Analog Input 0 = 0.000 volts */



You may create a debugger signal function to periodically change the value of the A/D input.

The following signal function increases the A/D Channel 1 input voltage by 0.1 volts each

second.

signal void AD1_sig (void) {

float f;

for (f = 0.0; f < 5.0; f += 0.1)

{

swatch (1.0); // Delay 1 second

AD1 = f; // Set AD1 Voltage

}

}

Get more information about the

Peripheral Simulation Capabilities

of the µVision Debugger.

Peripheral Simulation For NXP (founded by Philips) LPC2148 — D/A Converter




D/A Converter Dialog

The DAC Converter dialog displays and configures the

Digital/Analog converter. The controls in this dialog are separated

into several logical groups.

D/A Control

DACR (D/A Control Register) contains the following settings:

VALUE (Digital Data Velue) contains the value to be

converted to analog voltage on the AOUT pin.

BIAS (BIAS Option) changes the maximum current and

settling time for the analog voltage produced.

http://www.keil.com/uvision/db_sim_prf_peripherals.asp

Voltage Reference

VREF (VREF Value) contains the voltage refernece value.

Analog Output

AOUT (Analog Output) contains the D/A converted analog voltage.

Peripheral Simulation For NXP (founded by Philips) LPC2148 — External Interrupts




External Interrupts Dialog

The External Interrupts Dialog controls the interrupt support for triggering interrupts from

an external source. You may use the following controls to select and configure the external

interrupt settings.

Selected External Interrupt Group

EINTx (External Interrupt Flag 0-3) is set when an external interrupt (0-3) occurs.

EXTWAKEx (External Interrupt 0-3 Wake-Up Enable) when set allows an external

interrupt to wake up the processor from Power Down mode.

EXTMODEx (External Interrupt Mode 0-3) is set to configure the EINTx pin to be edge-

sensitive. If reset, the EINTx pin is level-sensitive.

EXTPOLARx (External Interrupt Polarity 0-3) in level-sensitive mode, is set to indicate

the corresponding pin is high-active. In edge-sensitive mode, this bit is set to indicate

rising-edge sensitivity.

EXTINT (External Interrupt Flag Register) contains the EINTx interrupt flags that set

when an external interrupt occurs.

INTWAKE (Interrupt Wake-Up Register) contains the EXTWAKEx bits that allow

external interrupts to wake up the MCU from Power Down mode.

EXTMODE (External Interrupt Mode Register) contains the external interrupt mode bit

settings for all EINT pins.

EXTPOLAR (External Interrupt Polarity Register) contains the polarity settings for all

EINT pins.




Peripheral Simulation For NXP (founded by Philips) LPC2148 — General Purpose Input/Output (GPIO0-1)





General Purpose Input/Output 0 (GPIO0) Dialog

The General Purpose Input/Output 0 (GPIO 0) Dialog controls the direction of the general

purpose port 0 pins. You may use the following controls to select and configure the external

interrupt settings.

GPIO0 Group

IO0DIR (Input Output Direction Register) contains the direction assignments for each

I/O port bit. The checkboxes are checked for output and unchecked for input.

IO0SET (Input Output Set Register) bits are checked to force a high level for a that

port bit during output.

IO0CLR (Input Output Clear Register) bits are checked to force a low level for a that


IO0PIN (Input Output Pin Value Register) contains the current condition of the GPIO 0

pins.

Pins is used to manually control a pin value.

General Purpose Input/Output 1 (GPIO1) Dialog


The General Purpose Input/Output 1 (GPIO 1) Dialog controls the direction of the general

purpose port 1 pins. You may use the following controls to select and configure the external

interrupt settings.

GPIO1 Group

IO1DIR (Input Output Direction Register) contains the direction assignments for each

I/O port bit. The checkboxes are checked for output and unchecked for input.

IO1SET (Input Output Set Register) bits are checked to force a high level for a that


IO1CLR (Input Output Clear Register) bits are checked to force a low level for a that


IO1PIN (Input Output Pin Value Register) contains the current condition of the GPIO 1

pins.

Pins is used to manually control a pin value.

PORTx VTREG Data Type: unsigned long

The PORTx VTREGs represent the I/O pins of the simulated MCU for Port A, Port B, and so

on. PORTA represents Port A, PORTB represents Port B, etc. You may read PORTx to

determine the state of the output pins of that port. For example, in the command window

you may type,

PORTA

to obtain value corresponding to the set pins of Port A. You may a lso change the input

values of port pins by changing the value of the VTREG. For example,

PORTA=0x000000F0

sets the upper four port pins of Port A to a value of 1 and all other port pins to a value of 0.

You may use the bitwise operators AND(&), OR(|) and XOR(^) to change individual bits of

the PORTx VTREGs. For example:

PORTA |= 0x00000001; /* Set PA0 Pin */

PORTB &= ~0x00000200; /* Clr PB9 Pin */

PORTA ^= 0x00800000; /* Toggle PA23 Pin */




Peripheral Simulation For NXP (founded by Philips) LPC2148 — I2C Interfaces: (I2C0-1)





I2C Communication Dialog

The I2C Communication dialog displays the I2C communication activity on the I2C bus. The

message Mode, Address, Direction and data message content are displayed for each

message. To clear the message display, double-click anywhere in the message display area.

I2C Hardware Dialog


The I2C Hardware dialog configures one of the on-chip I2C controllers. Each I2C controller

fully supports master or slave operations. The following groups control the simulation of the

I2C Interfaces:

I2C Control Group

I2CnCONSET (I2C Control Set Register) is used to set bits in the I2C control register.

A bit value of zero in this register has no effect on the I2C control register. It contains

the following control bits:

I2EN (Enable) is set to enable this I2C interface.

STA (Start) is set to enter master mode and send a START condition.

STO (Stop) is set to send a STOP condition in master mode, and recover from an error

in slave mode.

AA (Assert ACK) is set to request an acknowledge be returned from the slave device.

SI (Interrupt) is set to indicate a state change in the I2C controller.

I2CnCONCLR (I2C Control Clear Register) is used to clear bits in the I2C control

register. A bit value of zero in this register has no effect on the I2C control register. It

contains the following control bits:

I2ENC disables the I2C controller.

STAC clears the START flag.

AAC clears the Assert ACK flag.

SIC clears the I2C interrupt flag.

Clock Rate Group

I2CnSCLL (I2C SCL Low Duty Cycle Register) contains the SCL Low Duty Cycle count.

I2CnSCLH (I2C SCL High Duty Cycle Register) contains the SCL High Duty Cycle count.

Master Clock displays the serial clock.

Status Group

I2CnSTAT (Slave Status Register) contains I2C interface status code. The Device Mode

and Status display a decoded description of the interface status register value.

Address Group

I2CnADR (I2C Slave Address Register) contains the value of the I2C slave address

register. This register is only valid in Slave mode.

Device Address contains the slave device address.

GC is set to respond to a General Call address(0x00).

Data Group

I2CnDAT contains the data byte to be sent or the last data byte received.

I2C0_IN VTREG Data Type: unsigned short

I2C0_OUT VTREG Data Type: unsigned short

I2C1_IN VTREG Data Type: unsigned short

I2C1_OUT VTREG Data Type: unsigned short




Peripheral Simulation For NXP (founded by Philips) LPC2148 — Memory Accelerator Module (MAM)




Memory Accelerator Module Dialog

The Memory Accelerator Module (MAM) dialog configures the

on-chip Memory Accelerator Module. The MAM is useful in

improving ARM processor performance when running program

from Flash memory. The following groups control the

simulation of the MAM:

MAM Control Group

MAMCR (MAM Control Register) controls the operating

mode of the MAM.


Mode displays the current MAM mode.

MAM Timing Group

MAMTIM (MAM Timing Register) sets the number of processor clocks(CCLK) for each

MAM fetch cycle.

Fetch displays the current MAM timing setting.




Peripheral Simulation For NXP (founded by Philips) LPC2148 — Memory Mapping Control




Memory Mapping Control Dialog

The Memory Mapping Control (MAM) dialog configures the

on-chip Memory Mapping Control logic. Memory Mapping

Control remaps the interrupt vectors to different memory

locations. The Memory Mapping Control settings are:

Memory Mapping Control Group

MEMMAP (Memory Mapping Control Register) contains the Memory Mapping Control

register value.

MAP determines the area of memory the processor should use for interrupt vectors.




Peripheral Simulation For NXP (founded by Philips) LPC2148 — Phase Locked Loops (PLL0-1)


Dialog boxes which display and allow you to change peripheral configurat ion.


Phase Locked Loop 0 Dialog



The Phase Locked Loop 0 Dialog controls

Phase Locked Loop (PLL) function of the

ARM controller. Using this dialog, you can

configure the MCU clock frequency by

changing the multiplier and divider values

that control the MCU clock.

Control Register

PLL0CON (PLL Control Register)

contains the PLL Enable bit (bit 0), and

the PLL Connect bit (bit 1).

PLLE (PLL Enable) is set to activate the

PLL and allow it to lock to the requested

frequency.

PLLC (PLL Connect) is set to connect

the PLL as the clock source. A

successful connect requires the PLLE bit

set.

Configuration Register

PLL0CFG (PLL Configuration Register) contains the PLL Multiplier (MSEL) and PLL

Divider (PSEL) values.

MSEL (PLL Multiplier Value) is the multiplier value used in calculating the PLL clock

frequency.

PSEL (PLL Divider Value) is the divider value used in calculating the PLL clock

frequency.

Status Register

PLL0STAT (PLL Status Register) contains the following PLL status bits:

MSEL (PLL Multiplier Read-Back Value) is the multiplier value currently used by the PLL.

PSEL (PLL Divider Read-Back Value) is the divider value currently used by the PLL.

PLLE (PLL Enable Read-Back Value) is set when the PLL is active. If reset, the PLL is

turned off.

PLLC (PLL Connect Read-Back Value) is set when the MCU uses the PLL as the clock

source. If reset, the MCU uses the oscillator clock as the source.

PLOCK (PLL Lock Status) is set when the PLL is locked on the requested frequency.

Feed Register

PLL0FEED (PLL Feed Register) contains the 8-bit value last written to this register. To

set the clock configuration, this register must be stored with consecutive values of 0xAA

and 0x55, while the PLLE and PLLC bits are enabled.

Crystal Oscillator & Processor Clock

XTAL (Crystal Oscillator Frequency) the frequency (in MHz) of the crystal oscillator.

CLOCK (Processor Clock) is the computed processor clock frequency (CCLK) in MHz.

Phase Locked Loop 1 Dialog

The Phase Locked Loop 1 Dialog controls

Phase Locked Loop (PLL) function of the

ARM controller. Using this dialog, you can

configure the MCU clock frequency by

changing the multiplier and divider values

that control the MCU clock.

Control Register

PLL1CON (PLL Control Register)

contains the PLL Enable bit (bit 0), and

the PLL Connect bit (bit 1).

PLLE (PLL Enable) is set to activate the

PLL and allow it to lock to the requested

frequency.

PLLC (PLL Connect) is set to connect

the PLL as the clock source. A

successful connect requires the PLLE bit

set.

Configuration Register

PLL1CFG (PLL Configuration Register) contains the PLL Multiplier (MSEL) and PLL

Divider (PSEL) values.

MSEL (PLL Multiplier Value) is the multiplier value used in calculating the PLL clock

frequency.

PSEL (PLL Divider Value) is the divider value used in calculating the PLL clock

frequency.

Status Register

PLL1STAT (PLL Status Register) contains the following PLL status bits:

MSEL (PLL Multiplier Read-Back Value) is the multiplier value currently used by the PLL.

PSEL (PLL Divider Read-Back Value) is the divider value currently used by the PLL.

PLLE (PLL Enable Read-Back Value) is set when the PLL is active. If reset, the PLL is

turned off.

PLLC (PLL Connect Read-Back Value) is set when the MCU uses the PLL as the clock

source. If reset, the MCU uses the oscillator clock as the source.

PLOCK (PLL Lock Status) is set when the PLL is locked on the requested frequency.

Feed Register

PLL1FEED (PLL Feed Register) contains the 8-bit value last written to this register. To

set the clock configuration, this register must be stored with consecutive values of 0xAA

and 0x55, while the PLLE and PLLC bits are enabled.

Crystal Oscillator & Processor Clock

XTAL (Crystal Oscillator Frequency) the frequency (in MHz) of the crystal oscillator.

CLOCK (Processor Clock) is the computed processor clock frequency (CCLK) in MHz.





Peripheral Simulation For NXP (founded by Philips) LPC2148 — Pin Connect Block




Pin Connect Block Dialog

The Pin Connect Block Dialog allow the user to

configure pins P0.0 - P0.31 of the MCU based

on functions required. Selecting a pin allows

you to change the function for that pin.

Selected Pin

P0.x (Pin Name) lists the function choices

available for the selected pin.

Pin Select

PINSELx (Pin Selection Registers 0-1)

contain the composite bit settings for the

32 Port 0 bits.




Peripheral Simulation

For NXP (founded by Philips) LPC2148 — Power Control





Power Control Dialog

The Power Control Dialog controls the power saving mode

of the ARM controller. With this dialog, you can selectively

enable or disable unused peripherals to save power.

Selected Peripheral

When checked, this box indicates that the selected

peripheral is disabled. The checkbox name changes based

on the peripheral selected.

Power Control Group

PCON (Power Control Register) contains the Idle

Mode bit (bit 0), and the Power Down mode bit (bit

1).

PCONP (Power Control Peripheral Register) contains

the individual power control bits for all the peripherals

in the list.

IDL (Idle Mode) if set, stops the processor clock, but

leaves the other peripherals active. Any interrupt

starts the processor clock again.

PD (Power Down Mode) if set, stops the oscillator and

all on-chip clocks to stop. A wakeup condition starts

the oscillator and clocks again and resets this bit.

PDBOD (Power Down Brown-Out Detect Mode) if set, forces the processor into power-

down mode when a brown-out condition is detected.

BODPDM (Brown Out Detect Power Down Mode) if set, the BOD circuitry will go into

power down mode when chip power down is asserted.

BOGD (Brown Out Global Disable) if set, fully disables the BOD circuitry at all times.

BORD (Brown Out Reset Disable) if set, prevents the second stage of low voltage

detection (2.6 V) from causing a chip reset.

Interrupt Wakeup Group

INTWAKE (Interrupt Wakeup Register) contains following bit settings:

RTCWAKE (Real-Time Clock Wakeup Enable) if set, wakes up the processor from power

down mode.

BODWAKE (Brown-Out Detect Wakeup Enable) if set, wakes up the processor from

power down mode.

USBWAKE (USB Wakeup Enable) if set, USB activity wakes up the processor from

power down mode.




Peripheral Simulation For NXP (founded by Philips) LPC2148 — Pulse Width Modulator (PWM)





Pulse Width Modulator (PWM) Dialog

The Pulse Width Modulator dialog configures Pulse Width Modulator (PWM) simulation. When

configured for PWM mode, the Timers (0 or 1) provide a basis for PWM outputs. Pulse

period, pulse width, single and double edge controlle d outputs are supported.

Prescaler

PR (PWM Prescaler Register) contains the number of times (minus 1) PCLK must cycle

before incrementing the PWM Timer Counter (TC).

PC (PWM Prescaler Counter) contains the incrementing counter value. When this value

equals the PR value plus 1, the PWM Timer Counter (TC) is incremented.

Timer

TCR (PWM Timer Control Register) contains the Counter Enable, Counter Reset and the

PWM Enable control bits.

TC (PWM Timer Counter) contains the current value of the incrementing PWM Timer.

When the Prescaler Counter (PC) reaches the Prescaler Register (PR) value plus 1, this

counter is incremented.

Counter Enable is set to enable the PWM Timer Counter and PWM Prescale Counter.

Reset is set to reset the PWM Timer Counter and the PWM Prescale Counter to zero.

PWM Enable enables PWM mode. In this mode, writing to a Match Register does not

affect the the match result until a corresponding bit in Latch Enable Register (LER) is

set followed by a PWM Match event.

Interrupt Register

IR (Interrupt Register) contains the interrupt flags for PWM Match Channels 0-6. An

interrupt flag is set when an interrupt occurs for that channel (MRx Interrupt).

Match Channels The Match Channel group allows simulation of 6 single-edge controlled or

3 double-edge controlled PWM outputs. You may modify the seven Match Channels to

configure these PWM outputs to suit your requirements. Selected Channel

MRx (Match Register x) contains the value to be compared to the Timer Counter (TC)

value. When equal, a Match event occurs.

Match x Latch is set to allow the last value written to a Match Register x to become

active on the next timer reset.

MRx Interrupt (Match Register x Interrupt) is set when a interrupt occurs for Match

Channel 0-6

Interrupt on MRx is set to allow an interrupt to occur on Match Channel 0-6 when

Match Register x (MRx) equals the Timer Counter (TC) value.

Reset on MRx is set to reset the Timer Counter (TC) when the Match Register (MRx)

equals the Timer Counter (TC) value.

Stop on MRx is set to stop the Timer Counter (TC) and Prescaler Register (PC) when

the Match Register (MRx) equals the Timer Counter (TC) value. This condition also sets

the Timer Counter Register (TCR) to zero.

MCR (PWM Match Control Register) contains the Interrupt, Reset and Stop bits that

control the selected Match Channel.

LER (Latch Enable Register) contains the Match x Latch bits for each Match Channel.

PCR (PWM Control Register) contains the bits that enable PWM outputs 0-6 and select

single-edge or double-edge control for each output.




Peripheral Simulation For NXP (founded by Philips) LPC2148 — Real Time Clock




Real Time Clock Dialog


The Real Time Clock Dialog shows the current state of the on-chip real-time clock (RTC).

You can change the RTC settings using the controls in this dialog.

Clock Control

CCR (Clock Control Register) holds the following settings:

CLKEN (Clock Enable) is set to enable one of the time counters. This bit must be reset

to initialize a time counter.

CTCRST (Clock Tick Count Reset) is set to hold the Clock Tick Counter in a reset

condition.

Clock Tick Counter

CTC (Clock Tick Counter) contains the current value of the clock tick counter. 32,768

ticks of this clock equals 1 second.

Interrupt Location

ILR (Interrupt Location Register) holds the following settings:

RTCCIF ()

RTCALF ()

Counter Increment Interrupt

CIIR (Counter Increment Interrupt Register) holds the control bits for generating an

interrupt when a specific counter is incremented. The following control bits are

supported:

IMSEC is set to generate an interrupt when the Second value increments.

IMMIN is set to generate an interrupt when the Minute value increments.

IMHOUR is set to generate an interrupt when the Hour value increments.

IMDOM is set to generate an interrupt when the Day of Month value increments.

IMDOW is set to generate an interrupt when the Day of Week value increments.

IMDOY is set to generate an interrupt when the Day of Year value increments.

IMMON is set to generate an interrupt when the Month value increments.

IMYEAR is set to generate an interrupt when the Year value increments.

Alarm Mask

AMR (Alarm Mask Register) allows you to disable the alarms function for the following

time counters:

AMRSEC is set to disable the Second alarm (ALSEC).

AMRMIN is set to disable the Minute alarm (ALMIN).

AMRHOUR is set to disable the Hour alarm (ALHOUR).

AMRDOM is set to disable the Day of Month alarm (ALDOM).

AMRDOW is set to disable the Day of Week alarm (ALDOW).

AMRDOY is set to disable the Day of Year alarm (ALDOY).

AMRMON is set to disable the Month alarm (ALMON).

AMRYEAR is set to disable the Year alarm (ALYEAR).

Time Counter

SEC displays the current second (0-59).

MIN displays the current minute (0-59).

HOUR displays the current hour (0-23).

DOM displays the current day of the month. This value will be 1-28, 29, 30 or 31

depending on the month and leap year.

DOW displays the current day of the week (0-6).

DOY displays the current day of the year (1-365 or 1-366 for a leap year).

MONTH displays the current month (1-12).

YEAR displays the current year (0-4095).

Alarm This group contains the alarm values for triggering alarm interrupts. The alarm mask

bits (AMR) must be reset for an alarm interrupt to occur.

ALSEC is the Seconds alarm value.

ALMIN is the Minutes alarm value.

ALHOUR is the Hour alarm value.

ALDOM is the Day of Month alarm value.

ALDOW is the Day of Week alarm value.

ALDOY is the Day of Year alarm value.

ALMONTH is the Month alarm value.

ALYEAR is the Year alarm value.

Consolidated Time

CTIME0 (Consolidated Time Register 0) contains the current value of the Seconds

(SEC), Minutes (MIN), Hours (HOUR) and Day of Week (DOW) time counters.

CTIME1 (Consolidated Time Register 1) contains the current value of the Day of Month

(DOM), Month (MON) and Year (YEAR) time counters.

CTIME2 (Consolidated Time Register 2) contains the current value of the Day of Year

(DOY) time counter.

Prescaler

PREINT contains the integer portion of the Prescale Value. This value equals int(PCLK /

32768) - 1.

PREFRAC contains the fractional portion of the Prescale value. This value equals PCLK -

((PREINT+ 1) x 32768)

1s Tick (s) displays the resulting number of 1-second ticks for the Prescaler using the

PREINT and PREFRAC values.




Peripheral Simulation For NXP (founded by Philips) LPC2148 — SPI Interface: SPI0





Serial Peripheral Interface 0 Dialog

The Serial Peripheral Interface 0 Dialog allows you to

view and edit the Serial Peripheral Interface (SPI)

simulator configuration. Simulation of this interface is

controlled by the following groups:

Control Register Group

SPCR (Serial Peripheral Control Register)

contains the following bits that control the

functions of the SPI:

SPIE (SPI Interrupt Enable) is set to generate an

interrupt when either the SPI Transfer Complete

(SPIF) or Mode Fault (MODF) bits set.

LSBF (LSB First) is set to transfer SPI data

starting with bit 0. If reset, SPI starts data

transfers with bit 7.

MSTR (Master Mode) is set to configure the SPI

as a Master. If reset, the SPI operates in Slave

mode.

CPOL (Clock Polarity) is set when the serial clock

(SCK) is active low. If reset, SCK is active high.

CPHA (Clock Phase) is set to sample data on the

second clock edge. If CPHA is reset, data

sampling starts on the first clock edge, and Slave Select (SSEL) signal determines the

start and end of the data transfer cycle.

Status Register Group


SPSR (SPI Status Register) monitors the SPI status. It contains the following read-only

bits:

SPIF (Data Transfer Complete) is set when the SPI completes a data transfer

operation. This bit clears after this register and the data register (SPDR) are read.

WCOL (Write Collision) is set when data is written to the SPI data register while a SPI

data transfer is in progress.

ROVR (Read Overrun) is set when the SPI receives data before it's read buffer is

empty.

MODF (Mode Fault) is set when the Slave Select (SSEL) goes active and the SPI is

configured as a master.

ABRT (Slave Abort) is set when the Slave Select (SSEL) signal goes inactive before a

data transfer completes.

Clock Counter Group

SPCCR (SPI Clock Counter Register) controls the SPI clock rate when the SPI is

configured as a master. This value is the number of PCLK cycles that make up 1 SPI

clock.

Master Clock is the SPI clock value (SCK) based on the SPCCR setting.

Data Register Group

SPDR (SPI Data Register) contains the either the data to be transmitted or the data

received. In Master mode, writing to this register starts data transfer.

Slave Select Group

SSEL# Pin (Slave Select) is the signal level at the slave select pin.

Interrupt Register Group

SPINT (SPI Interrupt Register) contains the SPI interrupt flag setting.

SPI Interrupt (SPI Interrupt Flag) is set by the SPI interface to generate an SPI

interrupt.

SPIx_IN VTREG Data Type: unsigned char

The SPIx_IN VTREG (where x indicates the SPI port 0, 1, 2, and so on) contains a byte

which is received via the MCU SPI (Serial Peripheral Interface) port on the next SPI transfer.

You may use this VTREG in a simulation script. For example:

signal void spi_func (void) {

while (1) {

wwatch (SPI0_OUT);

printf ("SPI0_OUT: %2.2X\n", (unsigned) SPI0_OUT);

SPI0_IN = SPI0_OUT + 1;

}

}

This signal function returns the SPI byte send plus 1 on the next SPI transfer.

SPIx_OUT VTREG Data Type: unsigned char

The SPIx_OUT VTREG (where x indicates the SPI port 0, 1, 2, and so on) contains a byte

output via the MCU SPI (Serial Peripheral Interface) port. When your simulated program

sends a byte via SPI, the SPIx_OUT VTREG is set with the value output. You may monitor

this VTREG in a simulation script. For example:

signal void spi_watcher (void) {

while (1) {

wwatch (SPI1_OUT);

printf ("SPI1_OUT: %2.2X\n", (unsigned) SPI1_OUT);

}

}




Peripheral Simulation For NXP (founded by Philips) LPC2148 — SSP Interface





SSP (Synchronous Serial Port)

Dialog

The Synchronous Serial Port dialog displays

and allows you to edit the configuration of the

Synchronous Serial Port. The controls in this

dialog are separated into several logical

groups.

Control

SSPCR0 (SSP Control Register 0)

contains the SSP control register settings.

SSPCR1 (SSP Control Register 1)

contains the SSP control register 1

settings.

SSE (SSP Enable) is set to enable the

Synchronous Serial Port.

LBM (Loop Back Mode Control) is set to

connect received input to transmitted

output.

FRF (Frame Format) selects SPI, TI ot

Microwire frameing format.


DSS (Data Size Selection) selects the transfer data widths from 4-bits to 16-bits.

SCR (Serial Clock Rate) is the number of prescaler output clocks per bit, minus 1.

MS (Master/Slave Mode) is set to generate shift clocking from SCLK.

SOD (Slave Output Disable) is set to prevent the SP controller from transmitting data.

SPH (Clock Out Phase Control) is set to latch receive data on the leading clock edge

and shift on the trailing edge. If reset, Shift receive data on the leading clock edge and

latch on the trailing edge.

SPO (Clock Out Polarity Control) is set make the clock line low-active and the leading

clock edge is a high-to-low transition.

Status

BSY (Busy Flag) indicates data transfer is in progress.

RFF (Receive FIFO Full Flag) indicates the receive FIFO is full.

RNE (Receive FIFO Not Empty Flag) indicates the receive FIFO contains unread data.

TNF (Transmit FIFO Not Full Flag) indicates the transmit FIFO can accept data.

TFE (Transmit FIFO Empty Flag) indicates that all data previously sent has been

transmitted.

Data

SSPDR (SSP Data Register) contains data to be sent or received.

Clock Prescaler

SSPCPSR (SSP Clock Prescale Register) contains the PCLK divisor value (2-254) used

to generate the prescaler output clock.

Interrupts

SSPIMSC (SSP Interrupt Mask Set/Clear Register) contains the bits that enable the

following four interrupts in the SSP controller:

TXIM (Transmit Interrupt) is set to trigger an interrupt when the transmit FIFO is at

least half empty.

RXIM (Receive Interrupt) is set to trigger an interrupt when the receive FIFO is at least

half full.

RTIM (Receive Timeout Interrupt) is set to trigger an interrupt when the receive FIFO

is not empty and nothing has been read for a predetermined time.

RORIM (Receive Overrun Interrupt) is set to trigger an interrupt when the receive FIFO

is full and another frame is received.

SSPRIS (SSP Raw Interrupt Status Register) contains the SSP control register 0

settings.

TXRIS (Raw Transmit Interrupt) is set to trigger an interrupt when the transmit FIFO is

at least half empty.

RXRIS (Raw Receive Interrupt) is set to trigger an interrupt when the receive FIFO is

at least half full.

RTRIS (Raw Receive Timeout Interrupt) is set to trigger an interrupt when the receive

FIFO is not empty and nothing has been read for a predetermined time.

RORRIS (Raw Receive Overrun Interrupt) is set to trigger an interrupt when the

receive FIFO is full and another frame is received.

SSPMIS (SSP Masked Interrupt Status Register) contains the following SSP masked

interrupts:

TXMIS (Masked Transmit Interrupt) is set to trigger an interrupt when the transmit

FIFO is at least half empty.

RXMIS (Masked Receive Interrupt) is set to trigger an interrupt when the receive FIFO

is at least half full.

RTMIS (Masked Receive Timeout Interrupt) is set to trigger an interrupt when the

receive FIFO is not empty and nothing has been read for a predetermined time.

RORMIS (Masked Receive Overrun Interrupt) is set to trigger an interrupt when the

receive FIFO is full and another frame is received.

SSPICR (SSP Interrupt Clear Register) is used by software to clear SSP interrupt

conditions.

RORIC (Receive Overrun Interrupt Clear) clears a Receive Overrun interrupt.

RTIC (Receive Timeout Interrupt Clear) clears a Receive Timeout interrupt.

Master Clock

Clock The SSP clock rate.

Frame Sync/Slave Select

FS/SSEL1 pin Displays the status of the Frame Sync/Slave Select signal.

SSP Data Input VTREG Data Type: unsigned short

SSP Data Output VTREG Data Type: unsigned short




Peripheral Simulation For NXP (founded by Philips) LPC2148 — Timers: (Timer0-1)




Timer 0 Dialog


The Timer 0 Dialog displays and changes the settings associated with Timer 0. Timers

perform various event timing, capture and measurement tasks.

Prescaler Mode

PR (Prescale Register) contains the number of MCU clocks (PCLK) required to increment

the Timer Counter (TC) value.

PC (Prescale Counter) contains the current prescale counter value. When this value

equals the Prescale Register (PR), the Timer (TC) value is incremented.

Timer Control

TCR (Timer Control Register) contains Timer Enable and Reset control bits.

TC (Timer Counter) is the timer counter value. It is incremented when the Prescale

Counter (PC) equals the Prescale Register (PR).

Enable is set to enable the Timer.

Reset is set to reset the Timer.

Interrupt Register

IR (Interrupt Register) contains the interrupt flags for the seven match channels. When

a match channel interrupt is generated, the flag bit in the IR for that match channel is

set. Storing a 1 in any of the IR bits resets that match channel interrupt.

Match Channels

MCR (Match Control Register) controls the Timer reset and interrupt generat ion when a

Match Register (MRx) value equals the Timer Counter (TC) value.

EMR (External Match Register) enables and configures the behavior of the MAT0/1

output signal.

MRx (Match Register 0-3) contains a match value that is compared to the Timer

Capture value. When they are equal, depending on the Match Control Register (MCR),

the MCU may suspend the Timer or Prescaler counting, or generate an interrupt.

Interrupt on MRx is set to generate an interrupt when the value in MRx matches the

Timer Counter (TC) value.

Reset on MRx is set to reset the Timer Counter value (TC) when the value in MRx

matches the Timer Counter (TC) value.

Stop on MRx is set to stop the Timer Counter value (TC) and the Prescale Counter

(PC) when the value in MRx matches the Timer Counter (TC) value.

EMCx (External Match Control x) defines how the output level is set when an external

match occurs on MRx.

External Match x reflects the state of the output MAT0/1 when a match on MRx

occurs.

MRx Interrupt is set when an MRx matches the value in TC.

Capture Channels

CCR (Capture Control Register) controls which edge of the capture inputs trigger

loading the Capture Registers.

CRx (Capture Register x) contains the Timer Counter (TC) value when the last capture

event occurred for this register.

Rising Edge x is set to trigger a when a rising edge occurs on the capture event pin

(CAP0.x).

Falling Edge x is set to trigger a when a falling edge occurs on the capture event pin

(CAP0.x).

Interrupt on Event x is set to trigger an interrupt when the capture register (CRx) is

loaded.

CAP0.x (Capture Signals) are signal levels that can be configured to load a Capture

Register or generate an interrupt.

CRx Interrupt is set to trigger a Capture Register (CRx) interrupt.

Count Control

CTCR (Count Control Register.) enables either Timer and Counter mode.

Mode (Current Mode) display and selects either Timer and Counter mode.

Counter Input displays and selects the pin to use as input to the counter.

Timer 1 Dialog

The Timer 1 Dialog displays and changes the settings associated with Timer 1. Timers

perform various event timing, capture and measurement tasks.

Prescaler Mode

PR (Prescale Register) contains the number of MCU clocks (PCLK) required to increment

the Timer Counter (TC) value.

PC (Prescale Counter) contains the current prescale counter value. When this value

equals the Prescale Register (PR), the Timer (TC) value is incremented.

Timer Control

TCR (Timer Control Register) contains Timer Enable and Reset control bits.

TC (Timer Counter) is the timer counter value. It is incremented when the Prescale

Counter (PC) equals the Prescale Register (PR).

Enable is set to enable the Timer.

Reset is set to reset the Timer.

Interrupt Register

IR (Interrupt Register) contains the interrupt flags for the seven match channels. When

a match channel interrupt is generated, the flag bit in the IR for that match channel is

set. Storing a 1 in any of the IR bits resets that match channel interrupt.

Match Channels

MCR (Match Control Register) controls the Timer reset and interrupt generation when a

Match Register (MRx) value equals the Timer Counter (TC) value.

EMR (External Match Register) enables and configures the behavior of the MAT0/1

output signal.

MRx (Match Register 0-3) contains a match value that is compared to the Timer

Capture value. When they are equal, depending on the Match Control Register (MCR),

the MCU may suspend the Timer or Prescaler counting, or generate an interrupt.

Interrupt on MRx is set to generate an interrupt when the value in MRx matches the

Timer Counter (TC) value.

Reset on MRx is set to reset the Timer Counter value (TC) when the value in MRx

matches the Timer Counter (TC) value.

Stop on MRx is set to stop the Timer Counter value (TC) and the Prescale Counter

(PC) when the value in MRx matches the Timer Counter (TC) value.

EMCx (External Match Control x) defines how the output level is set when an external

match occurs on MRx.

External Match x reflects the state of the output MAT0/1 when a match on MRx

occurs.

MRx Interrupt is set when an MRx matches the value in TC.

Capture Channels

CCR (Capture Control Register) controls which edge of the capture inputs trigger

loading the Capture Registers.

CRx (Capture Register x) contains the Timer Counter (TC) value when the last capture

event occurred for this register.

Rising Edge x is set to trigger a when a rising edge occurs on the capture event pin

(CAP1.x).

Falling Edge x is set to trigger a when a falling edge occurs on the capture event pin

(CAP1.x).

Interrupt on Event x is set to trigger an interrupt when the capture register (CRx) is

loaded.

CAP1.x (Capture Signals) are signal levels that can be configured to load a Capture

Register or generate an interrupt.

CRx Interrupt is set to trigger a Capture Register (CRx) interrupt.

Count Control

CTCR (Count Control Register.) enables either Timer and Counter mode.

Mode (Current Mode) display and selects either Timer and Counter mode.

Counter Input displays and selects the pin to use as input to the counter.




Peripheral Simulation For NXP (founded by Philips) LPC2148 — UARTs: (UART0-1)






UART 0 Dialog

The Universal Asynchronous Receiver Transmitter (UART 0) Dialog configures UART 0. A

UART transfers serial data to and from external devices and the ARM controller. The UART

can be configured in a variety of ways to suit the external serial device.

Line Control Group

LCR (Line Control Register) displays the combined control information for the following:

Word Length selects the data character length of 5, 6, 7 or 8 bits per character.

Stop Bits (Number of Stop Bits) selects the number of stop bits to be sent with each

character.

Parity selects odd, even or no (forced "0" or "1") parity.

DLAB (Divisor Latch Access Bit) is set to calculate the baud rate based on the Divisor

Latch register (DLL and DLM) values.

Break Control is set to enable transmission of a Break.

Parity Enable is set to enable parity generation and checking.

Line Status Group

Receiver Data Ready (RDR) set when the UART 0 receives at least 1 character and

the receiver hold register is not empty.

Overrun Error (OE) set if the controller detects an overrun condition since the last

status reset command.

Parity Error (PE) set if the controller detects at least 1 false parity bit since the last


Framing Error (FE) set if the controller detects a framing error since the last status

reset command.

Break Interrupt (BI) is set when a Break condition occurs while receiving data.

Tx Holding Register Empty (THRE) is set when the transmission hold register is

empty.

Transmitter Empty (TEMT) set if there are no characters in the transmitter.

Error in Rx FIFO (RXFE) is set when the receiver detects any error (parity, framing,

overrun or break).

Interrupt Enable Group

IER (Interrupt Enable Register) contains the RBR, THRE and Line Status Enable bits.

RBR IE (Receive Buffer Register Interrupt Enable) is set to enable the Receive Data

Available interrupt.

THRE IE (Transmit Hold Register Empty Interrupt Enable) is set to enable the

Transmitter Empty (THRE) interrupt.

Rx Line Status EI (Line Status Interrrupt Enable) is set to enable Line Status

interrupts.

Interrupt ID & FIFO Control Group

IIR/FCR (Interrupt Identif ication/FIFO Control Register)

Interrupt displays the interrupt type(Line Status, THRE, RDA, Character Time-out).

FIFO Enable (FIFO Enable) is set to clear and enable the receive and transmit FIFOs.

Rx Trigger (Rx Trigger Level Select) sets the number of characters required to trigger

a receive interrupt.

Rx FIFO Reset clears the receive FIFO buffer.

Tx FIFO Reset clears the transmit FIFO buffer.

Divisor Latch Group

DLL (Divisor Latch LSB Register) contains the lower 8-bit value that the MCU divides

into the MCU clock (PCLK) to generate the UART baud rate.

DLM (Divisor Latch MSB Register) contains the upper 8-bit value that the MCU divides


Baudrate is the computed UART baud rate.

Receiver & Transmitter Registers Group

RBR/THR (Receiver Buffer Register/Transmitter Hold Register) when receiving, is the

oldest character received. When transmitting, it is the newest character to be

transmitted.

Scratch Pad Group

SCR (Scratch Pad Register) has no effect on the UART operation. It can be used for

general purpose storage.

UART 1 Dialog

The Universal Asynchronous Receiver Transmitter (UART 1) Dialog configures UART 1. A

UART transfers serial data to and from external devices and the ARM controller. The UART

can be configured in a variety of ways to suit the external serial device.

Line Control Group

LCR (Line Control Register) displays the combined control information for the following:

Word Length selects the data character length of 5, 6, 7 or 8 bits per character.

Stop Bits (Number of Stop Bits) selects the number of stop bits to be sent with each

character.

Parity selects odd, even or no (forced "0" or "1") parity.

DLAB (Divisor Latch Access Bit) is set to calculate the baud rate based on the Divisor

Latch register (DLL and DLM) values.

Break Control is set to enable transmission of a Break.

Parity Enable is set to enable parity generation and checking.

Line Status Group

Receiver Data Ready (RDR) set when the UART 1 receives at least 1 character and

the receiver hold register is not empty.

Overrun Error (OE) set if the controller detects an overrun condition since the last


Parity Error (PE) set if the controller detects at least 1 false parity bit since the last


Framing Error (FE) set if the controller detects a framing error since the last status

reset command.

Break Interrupt (BI) is set when a Break condition occurs while receiving data.

Tx Holding Register Empty (THRE) is set when the transmission hold register is

empty.

Transmitter Empty (TEMT) set if there are no characters in the transmitter.

Error in Rx FIFO (RXFE) is set when the receiver detects any error (parity, framing,

overrun or break).

Interrupt Enable Group

IER (Interrupt Enable Register) contains the RBR, THRE and Line Status Enable bits.

RBR IE (Receive Buffer Register Interrupt Enable) is set to enable the Receive Data

Available interrupt.

THRE IE (Transmit Hold Register Empty Interrupt Enable) is set to enable the

Transmitter Empty (THRE) interrupt.

Rx Line Status EI (Line Status Interrrupt Enable) is set to enable Line Status

interrupts.

Modem Status EI (Modem Status Interrrupt Enable) is set to enable modem

interrupts.

Interrupt ID & FIFO Control Group

IIR/FCR (Interrupt Identif ication/FIFO Control Register)

Interrupt displays the interrupt type(Line Status, THRE, RDA, Character Time-out).

FIFO Enable (FIFO Enable) is set to clear and enable the receive and transmit FIFOs.

Rx Trigger (Rx Trigger Level Select) sets the number of characters required to trigger

a receive interrupt.

Rx FIFO Reset clears the receive FIFO buffer.

Tx FIFO Reset clears the transmit FIFO buffer.

Divisor Latch Group

DLL (Divisor Latch LSB Register) contains the lower 8-bit value that the MCU divides


DLM (Divisor Latch MSB Register) contains the upper 8-bit value that the MCU divides


Baudrate is the computed UART baud rate.

Receiver & Transmitter Registers Group

RBR/THR (Receiver Buffer Register/Transmitter Hold Register) when receiving, is the

oldest character received. When transmitting, it is the newest character to be

transmitted.

Scratch Pad Group

SCR (Scratch Pad Register) has no effect on the UART operation. It can be used for

general purpose storage.

Modem Control Group

MCR (Modem Control Register) contains the DTR, RTS and Loobback modem controls.

DTR Control (Data Terminal Ready Control) is the DTR modem output level.

RTS Control (Request To Send Control) is the RTS modem output level.

Loopback Mode is set to perform diagnostic loopback testing.

Modem Status Group

MSR (Modem Status Register) contains the following status from the modem input

signals:

Delta CTS (Delta Clear to Send) is set when the state of modem input CTS changes.

Delta DSR (Delta Data Set Ready) is set when the state of modem input DSR changes.

Trailing Edge RI (Trailing Edge Ring Indicator) is set when a low-to-high transition

occurs on the RI input.

Delta DCD (Delta Data Carrier Detect) is set when the state of modem input DCD

changes.

CTS (Clear To Send) is the complement of the CTS input signal.

DSR (Data Set Ready) is the complement of the CTS input signal.

RI (Ring Indicator) is the complement of the CTS input signal.

DCD (Data Carrier Detect) is the complement of the CTS input signal.

Modem Lines Group This group displays the following modem signal levels.

RTS1 Request To Send

CTS1 Clear To Send

DTR1 Data Terminal Ready

DSR1 Data Set Ready

DCD1 Data Carrier Detect

RI1 Ring Indicator

SxIN VTREG Data Type: unsigned int

The SxIN VTREG represents the serial input of the simulated microcontroller. Values you

assign to SxIN are input to the serial channel 0, 1, 2, and so on. You may assign input using

the command window. For example,

S0IN='A'

causes the simulated microcontroller serial input 0 to receive the ASCII character A. If you

want to use the SxIN VRTEG to simulate reception of multiple characters, you must be sure

to delay for at least one character time between successive assignments to SxIN. This may

be done using a signal function. For example:

signal void send_cat (void) {

swatch(0.01); /* Wait 1/100 seconds */

S0IN='C'; /* Send a C */

swatch(0.01);

S0IN='A';

swatch(0.01);

S0IN='T';

}

You may use the SxIN VTREG to input data (5-8 bits), parity, frame error and break

condition. SxIN Format (16-bit Register)

Bits 0-7: Data (5, 6, 7, or 8 bit)

Bit 8: Parity bit Value

Bit 9: Parity bit Presence (0=Not present, 1=Present)

Bit 10: Invalid Stop bit (0=Normal, 1=Invalid)

For example:

S0IN=0x0074 // Data = 0x74, No Parity bit

S0IN=0x0274 // Data = 0x74, Parity bit = 0

S0IN=0x0374 // Data = 0x74, Parity bit = 1

S0IN=0x0474 // Data = 0x74, No Parity bit

// Invalid Stop bit - Frame Error

S0IN=0x0400 // Break Condintion

In addition to the SxIN VRTEG, the serial window allows you to input serial characters by

simply typing. Serial characters that are transmitted byt the simulated microcontroller

appear in the serial window.

SxOUT VTREG Data Type: unsigned int

The SxOUT VTREG represents the serial output from the simulated serial port 0, 1, and so

on. Whenever the simulated serial port transmits a character, the value transmitted is

automatically assigned to SxOUT (which is read-only). You may read the value of SxOUT to

determine the character transmitted by your simulated program. For example,

S0OUT

outputs the value of the last character transmitted by serial port 0.

SxOUT Format (16-bit Register)

Bits 0-7: Data (5, 6, 7, or 8 bits)

Bit 8: Parity bit Value

Bit 9: Parity bit Presence (0=Not present, 1=Present)

Bit 10: Invalid Stop bit (0=Normal, 1=Invalid)

For example:

S0OUT & 0x00FF // Data

S0OUT & 0x0200 // Parity bit is present

S0OUT & 0x0100 // Parity bit value (0=0, 0x0200=1)

Note that you cannot assign values to the SxOUT VTREGs. You may use the SxOUT VTREG

in a script to process transmitted data. For example,

signal void s0out_sig (void) {

while (1)

{

wwatch(S0OUT); /* wait for something in S0OUT */

printf ("Transmitted a %2.2X\n", (unsigned) S0OUT);

}

}

SxTIME VTREG Data Type: unsigned char

The SxTIME VTREG allows you to control the timing of the simulated serial port 0, 1, and so

on.

A value of 1 (which is the default) indicates that the serial port timing is identical to the

target hardware. Use this value when you want to see the effects of baud rate on the

serial port I/O.

A value of 0 indicates that all serial input and output occur instantaneously. Use this

value when you don't care about any baud rate effects or when you want serial output

to be fast.

For example:

S0TIME = 0 /* Set Serial Port 0 for FAST timing */

S0TIME = 1 /* Set Serial Port 0 for accurate timing */




Peripheral Simulation For NXP (founded by Philips) LPC2148 — Vectored Interrupt Controller (VIC)





Vectored Interrupt Controller Dialog

The Vectored Interrupt Controller Dialog displays the status of all simulated MCU interrupts.

The source, channel, type, vector and interrupt state for each interrupt is displayed. You

may select and configure each interrupt using the following control groups:

Selected Interrupt

The checkboxes in this group control or reflect the highlighted interrupt.

IntSelect is set if the highlighted interrupt is an FIQ interrupt. If reset, it is a vectored

IRQ interrupt.

SoftInt is set to trigger a software interrupt for the highlighted interrupt.

IntEnable Enables the highlighted interrupt.

RawInt is set if any interrupt request occurs for the highlighted interrupt, whther

enabled or not.

Vectored IRQ

Slot (Slot Number) selects a Slot Number to be assigned to a Channel when the Enable

box is checked.

Channel (Channel Number) selects the Channel number that receives the Slot Number

assignment.

Enable when set, assigns the current Slot Number to the selected Channel. Resetting

this checkbox unassigns a Slot.

VICVectCntlx (Vector 0-15 Control Register) contains the interrupt request slot

number assigned to vectored IRQ x and the the IRQ enable bit.

VICVectAddrx (Vector Address 0-15 Register) contains the address of the interrupt

service routine for the vectored interrupts 0-15.

VICVectAddr (Vector Address Register) contains the address of the interrupt service

routine for the highest priority vectored IRQ.

VICDefVectAddr (Default Vector Address Register) is the interrupt service routine for

non-vectored IRQ interrupts.

VICProtection (Protection Enable Register) if set, software must be in Privileged mode

to access the Vectored Interrupt Controller (VIC).

VICSoftInt (Software Interrupt Register) forces an interrupt if the corresponding bit is

set.

VICSoftIntClear (Interrupt Clear Register) releases the forced software interrupt if the

corresponding bit is set.

VICIntSelect (Interrupt Select Register) contains the type of interrupt. Bits that are

set represent non-vectored FIQ interrupts. Bits that are reset represent vectored IRQ

interrupts.

VICIntEnable (Interrupt Enable Register) enables IRQ or FIQ interrupts if the

corresponding bit is set.

VICIntEnClr (Interrupt Enable Clear Register.) resets an enabled IRQ or FIQ interrupts

if the corresponding bit is set

VICRawIntr (Raw Interrupt Status Register) displays the state of all interrupts,

enabled or not.

VICIRQStatus (IRQ Status Register) displays the state of enabled IRQ (vectored)

interrupts.

VICFIQStatus (FIQ Status Requests) displays the state of enabled FIQ (non-vectored)

interrupts.




Peripheral Simulation For NXP (founded by Philips) LPC2148 — VPB Divider




VPB Divider Dialog

The VPB Divider Dialog controls the VLSI Peripheral Bus Divider

control register. This register controls the VBP clock rate (PCLK)

based on the MPU clock rate (CCLK). You may display or change the

settings using this dialog.

VPB Divider

VPBDIV (VPB Divider Control Register) contains the bit settings

that determine the MPU clock (CCLK) divisor for calculating the peripheral clock (PCLK).

Use the list box to select the clock divider.





Peripheral Simulation For NXP (founded by Philips) LPC2148 — Watchdog




Watchdog Timer (WDT) Dialog

The Watchdog Timer Dialog shows the current state of the

on-chip Watchdog Timer. You can change the Watchdog

Timer settings using the controls in this dialog.

Mode Register

WDMOD (Watchdog Mode Register) contains the

Watchdog Timer mode (Debug or Operate) and status

bits of the Watchdog Timer.

WDEN (Watchdog Timer Enable)is set to enable the

Watchdog Timer interrupt.

WDRESET (Watchdog Timer Reset) is set to reset the

Watchdog Timer.

WDTOF (Watchdog Timer Time-Out Flag) is set when

the Watchdog Timer times out.

WDINT (Watchdog Timer Interrupt Flag) is set when a Watchdog Timer interrupt

occurs.

Time Constant and Value

WDTC (Watchdog Timer Constant Register) contains the time-out value used to reload

the Watchdog Timer.

WDTV (Watchdog Timer Value Register) contains the current value of the Watchdog

Timer.

Feed Register

WDFEED (Watchdog Timer Feed Sequence Register) is used to reload the Watchdog

Timer. Writing 0xAA followed by 0x55 to this register reloads the Watchdog Timer to its

preset value.






Peripheral Simulation Keilc for Lpc 2148

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