Performing Efficient Characterization and

Verification Test of LPDDR3Verification Test of LPDDR3

Chris Loberg Tektronix

LPDDR3 Summit Santa Clara 2012

AgendaAgenda

• Introduction

– LPDDR3 Verification Challenges

• Applying LPDDR3 Electrical Verification Techniques

– Signal Integrity steps for evaluation of data bursts

– Read & Write Burst Capture in a ranked PoP environment

• Performing JEDEC-Compliant Test Practices for LPDDR3

– How to consistently apply in a test environment

– Pass/Fail Analysis & Reporting – Pass/Fail Analysis & Reporting

• Accessing LPDDR3 Test Points with Good Signal Fidelity

– Evaluation of available test point access options

• Oscilloscope Interposers

• Solder-down Probing Systems

– Filter application

• Summary/Q&A

LPDDR3 Verification Challenges:LPDDR3 Verification Challenges:Faster, Smaller, More output, Less powerFaster, Smaller, More output, Less power

LPDDR3 Key Features

• Speed and Capacity

• Bandwidth of 6.4 – 8.5 Gbps per die

• x16, x32

• 4, 8, 16, 32Gb Package Options

• Multiple channels, ranks – up to 346 balls

• Battery Conservation

• Low Voltage (300mV – 1.2V MAX)

• Voltage Ramp and Device Initialization

• Temperature-compensated and partial array self refresh modes

• Deep power down mode which sacrifices all memory contents

• Compact Packaging

• PoP and Discrete Packages

LPDDR3 LPDDR3 Verification ChallengesVerification Challenges

Pushing the system power envelopePushing the system power envelope

LPDDR2:• 1.2 V• 533MHz

LPDDR3 LPDDR3 Verification ChallengesVerification Challenges

Pushing the system power envelopePushing the system power envelope

LPDDR3:• 1.2 V• 800MHz

LPDDR3 Verification ChallengesLPDDR3 Verification Challenges

Faster Clock FrequenciesFaster Clock Frequencies

LPDDR3 Verification ChallengesLPDDR3 Verification Challenges

PHY Test AccessPHY Test Access

Signal IntegritySignal Integrity

Bandwidth considerations for DDR VerificationBandwidth considerations for DDR Verification

• LPDDR2/3 Depending on Error Tolerance Levels

– 8GHz Debugging

– 12.5GHz for Chipset/Controller & System

Specification Reference

Generation DDR DDR2 DDR2 DDR3 DDR3 LPDDR3 DDR4

Speed all rates to 400MT/s to 800MT/s to 1600MT/s to 2400MT/sto

1600MT/s to 3200MT/s

Max slew rate per JEDEC 5 5 5 10 12 8 18

Typical V swing 1.8 1.25 1.25 1 1 0.6 0.8

20-80 risetime (ps) 216 150 150 60 50 45 27

Equivalent Edge BW 1.9 2.7 2.7 6.7 8.0 8.9 15.0

BW Recommendations (by end-user task, matched to scope BW availability)

Chipset Development/ S.I. 2.5 3.5 4.0 12.5 12.5 12.5 16

System Level Test 2.5 2.5 3.5 8 12.5 12.5 12.5

Debug ( low cost) 2.0 2.0 2.5 6 8 8 12.5

Signal Integrity ChallengeSignal Integrity Challenge

Verifying Slew RateVerifying Slew Rate

Signal IntegritySignal Integrity

Capturing LPDDR3 Reads/Writes for VerificationCapturing LPDDR3 Reads/Writes for Verification

Signal IntegritySignal Integrity

Read/Write Burst Timing EvaluationRead/Write Burst Timing Evaluation

• Eye Pattern Masks

Signal IntegritySignal Integrity

Verifying AC Over/UndershootVerifying AC Over/Undershoot

Signal IntegritySignal Integrity

DDR Eye DiagramsDDR Eye Diagrams

• Hexagon shaped area applied to DQ used as a keep-out zone to isolate only target rank of interest.

• Use additional areas to target specific DQ patterns.

Before After

Signal IntegritySignal Integrity

Characterizing LPDDR3 using Eye Diagrams Characterizing LPDDR3 using Eye Diagrams

• Tips for quick evaluation of DQ Signals

Signal IntegritySignal Integrity

Read/Write Burst IdentificationRead/Write Burst Identification

� On a Trigger

� Mark all Read/Write Events

� Post Acquisition

� Across entire recorded acquisition, apply a search algorithm to each acquired

waveform, and mark reads/writes with visual delimiters

LPDDR3 Command Bus Capture & DisplayLPDDR3 Command Bus Capture & Display

Verification of Setup & Hold on Command BusVerification of Setup & Hold on Command Bus

CS CA1 CA2 CAn

� 1-16 Digital Channels – CS, CA1…CAn

� Timing & Placement

� 1-4 Analog Channels – Clock, DQ, DS

� Slew rate

CKDQS0DQ0

LPDDR3 Address Bus Capture & DisplayLPDDR3 Address Bus Capture & Display

Burst Detect on Command BusBurst Detect on Command Bus

� Using command bus state, specific transactions can be isolated

– Analysis of analog signals is then used for fine burst positioning to gate

measurements

JEDEC Test JEDEC Test Verification of LPDDRVerification of LPDDR

JEDEC VerificationJEDEC Verification

• Identify, mark & measure LPDDR3 Read / Write bursts

– Search & Mark Capability for Cataloging Read/Write’s

– Suggest use of Digital Channels for Command/Address

– LPDDR JEDEC Measurements performed on ALL reads/writes

– JEDEC Tests + Debug Tools

JEDEC Test Verification of LPDDRJEDEC Test Verification of LPDDR

Verification ExampleVerification Example

• Verification in multi-channel, multi-rank environments

– Pinpoint source(s) of signal integrity concerns

– Validation without re-probing using mux

JEDEC Test Verification of LPDDR JEDEC Test Verification of LPDDR

System visibility in high ball count systemsSystem visibility in high ball count systems

TriggerState

MachineCH 1

CH 2

Analog In

CH 1

Analog Out

3 GHzAnalog

Mux

34 ch

34 ch

4 ch

CH 2

CH 3

CH 4

DSODSOLALA

CH 2

CH 3

CH 4

Mux34 ch

34 ch

34 ch

Package-on-Package tends

to have more clearance…

Signal Access & ProbingSignal Access & Probing

KeepKeep--out Comparison of out Comparison of PoPPoP & Embedded & Embedded

… compared to the

embedded areas of a target

Signal Access & ProbingSignal Access & Probing

BGA Access BGA Access UUsing Oscilloscope Interposerssing Oscilloscope Interposers

� Unique, re-usable socket design allows for multiple chip exchanges

� Signal paths and termination requirements are key and central to the designs

� Modeling to predict analog performance

� Oscilloscope filters to enable views with and without interposer circuit effects

• LPDDR2/3 increases the number of package types vs DDR2/3/4

Memory

TechnologyDIMM

Package-on-

PackageEmbedded

DDR378B X4/X896B X16

N/A As needed

DDR478B X4/X896B X16

N/A As needed

LPDDR2 TBD

136B X32168B X32216B Dual X32

79B x16112B X16128B X16/X32

Signal Access & ProbingSignal Access & Probing

LPDDR Interposer Support LPDDR Interposer Support

LPDDR2 TBD 216B Dual X32220B Dual X32240B Dual X32

128B X16/X32134B X16/X32176B X16/X32

LPDDR3 TBD216B Dual X32256B Dual X32

178B X32253B Dual X32346B Dual X32 MCP

Interposer

Style

• SLOT• Perimeter & Flex

Wing MCI• EdgeProbe MCI

• Perimeter MCI• Flex Wing MCI -

Multi-sided

• Perimeter MCI• Flex Wing MCI -

Single-sided

Increasing Customization

LPDDR Analog Verification & DebugLPDDR Analog Verification & Debug

• Verification & Analysis

– LPDDR standards support

– JEDEC conformance measurements

– Debugging approaches

• Signal Access & Probing

– BGA Interposers

– High BW Solder-in Probes

– Digital Probing– Digital Probing

• Signal Capture

– Analog & Digital

ResourcesResources

www.tek.com/technology/ddr