pd design 9

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RV-VLSI CONFIDENTIAL

Objective

●

Perform key design for manufacturing steps required after the signalrouting is complete:

* Antenna fixing

* Metal filling

* Metal slotting

* Adding redundant contacts

* Wire spreading




Design status at start of DFM phase

• Standard cells are placed

• Clock tree and HFN buffers are placed

• All clock, signal and P/G nets have been completely routed

• All route related optimizations are completed:

– Setup and Hold time: met

– Maximum capacitance limits - met

– Maximum signal transition times – met

– Design is DRC clean

Design for

manufacturability

Routing

CTS

Placement




Manufacturing issues

• Astro can address several issues to increase manufacturing yield:

– Gate Oxide integrity antenna fixing

– Via resistance and reliability extra contacts

– Random Particle defectWire spreading

– Metal erosion metal slotting

– Metal liftoff metal slotting

– Metal Over-Etching metal fill




Gate Oxide Integrity

• Metal wires (antennae) placed in an EM field generate voltage gradients.

• During the metal each stage, strong EM fields are used to stimulate the plasma etchant.

• Resultant voltage gradients at MOSFET gates can damage the thin oxide.




Antenna Rules

• As length of wire increases during processing , the voltage stressing the gate oxideincreases.

• Antenna rules define acceptable length of wires.

*Antenna Ratios:

Area of metal connected to Gate

Combined Area of Gate

poly

metal2

metal1




Metal Splitting Or layer Jumping

• Before Layer Jumping

metal3

M1blockage

M3 blockage

metal1

Unacceptable antenna area

Gate

poly

Driver

diffusion




Metal Splitting Or layer Jumping

• After Layer Jumping, to meet Antenna rules

metal3

M1blockage

M3 blockage

metal1

Acceptable antenna area

Gate

poly

Driver

diffusion

metal3




Inserting Diodes

• Before Inserting Diodesmetal3

metal1

Diode Inhibits large voltage swings

on metal tracks

metal3

metal1

During etch phase, the diode clamps

the voltage swings.




Antenna violations fixing flow

Insert Antenna Diodes

for all remaining

violations

Remaining Design for

Manufacturability

Search & Repair

Set antenna rules

Route DRC

violations?

No

Yes

Routing & related

optimizations

Routing & related

optimizations

Routing & related

optimizations

Routing & related

optimizations

Routing & related

optimizations

Search & Repair




Via resistance and reliability

• Replacing one via with multiple vias can improve yield & timing (series R reduction)

• Astro inserts multiple vias without rerouting

extra

vias

added




Random Particle Defects

• Random missing or extra material causes opens or shorts during the fabrication process.

* Wires at minimum spacing are most susceptible to shorts

* Minimum-width wires are most susceptible to opens

Conductive defects within critical

area-causing shorts

Conductive defects outside critical

area-causing no shorts

Non-conductive defects within

critical area-causing opens

Non-conductive defects outside

critical area-causing no opens

Critical

Areas

metal3




Wire Spreading + Widening

• Spread wires to reduce short critical area

- push routes off-track by half pitch

- will not push “frozen” nets

• Widens wires to reduce open critical area

Wire Tracks

Spreading off-Track

Widening




Metal Erosion

• The wafer is made flat (planarized) by a process called Chemical Mechanical Polishing(CMP)

• Metals are mechanically softer than dielectrics:

* CMP leaves metal tops with a concave shape -dishing

* the wider the metal the more pronounced the dishing

* Wide traces with little intervening dielectric and can become quite thin –

dishing

this severe is called erosion.

• Process rules specify maximum metal density per layer to minimize erosion.

Try to get pic for this




Metal Littoff

• Conductors and dielectrics have different coefficients of thermal expansion:

- Stress builts up with temperature cycling

- Metals can delaminate (litoff) with time

- Wide metal traces are more vulnerable than narrow ones

• Maximum metal density rules also address this issue.

Dielectric

Metal Thermal Expansion

Dielectric Thermal Expansion




Metal Slotting

• Slotting wide wires reduces the metal density

• Slots minimizes stresses buildup, reducing litoff tendency

• Primarily used on Power and Ground traces:

- Can apply to any other net if wide enough

• Slotting parameters can be set layer by layer

Slide clearance OpenSlot Slide Space

Width

EndSpace Lenght




Metal Over-Etching

• A narrow metal wire separated from other metal recieves a higher density of etchant thanclosely spaced wires

• The narrow metal can get over-etched

• Minimum metal density rules are used to control this.




Metal fill

• Fills empty tracks with metal shapes to meet the minimum metal density rules

• Uses up most of the remaining routing resource:

– No further routing or antenna fixes can be done

pd design 9

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