pd design 2

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05/29/09 1

Chip Design Flow

By Venkatesh Prasad


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Ph: 080-40-788574 www.rv-vlsi.comRV-VLSI Confidential

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LAYOUT

The transformation of circuit description into a geometric description

Layout is a process of specifying the physical placement of andinterconnections between all of the devices in a circuit

Layout is used to generate all of the mask layers used for chip fabrication

Layout for Analog circuits: Few transistors

Few transistors are minimum size

Transistors are sized to minimized offsets

Focusing to minimize individual effects

Layout for Digital circuits : Number of transistors are more

Transistors of minimum size

Transistors are sized for minimize delays

Interconnection focus between modules


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An IC consists of :

Digital Blocks

Like any Adder, Multiplier

Analog Blocks

Like PLL, Filters, ADC

Techniques to implement the flow

Full Custom

The designer creates layout masks by hand

Long design cycle

Fast & Power efficient design

Semi Custom

Short design cycle

Not so good power efficient design w.r.t. to Full-custom

IC Flow


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Full-Custom Flow


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Automated Analog Flow

Analog Flow


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Design Flow

System level design

create high level behavioural representation of design using VHDL, Verilog or System-C .

Logic design & verification

Translate system level description into transistors

schematic representation Circuit design

Transistor sizes

Performance evaluation with complex models (H-Spice)

Layout

Translate circuit into layout

DRC rules should be taken care

Need not be necessary that layout is too exact to schematic

Verification

Compare netlists

Full-Custom Flow


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Full Custom layout supports 3 different flavours for automation and

migration of technologies

Data-path layout

Analog

Cell

All three types are driven by a schematic based design style versus a

language based design style.

IC Flow


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Data-path full custom layout

Area limitation

Specific application

need repeated complex structures like adders, multipliers etc.

Example : Memory design

Memory layout design depends on the memory cell layout design

Cell efficiency

Need good layout designers to develop the smallest cell size

Interface blocks must match the pitch of memory cell and provide thefunctionality

Might be iterate so many times with circuit designer

IC Flow


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Analog full custom layout

It is the place where a designer should understand the complete phenomena that happenswithin the device, physical connections, implants and need to have a good knowledge ofsemiconductor physics

Margins of errors and tolerance is very less

Highly process dependent , so migration of technology is not possible

Device Matching

Inter-digitized

common centroid

Placement is tightly controlled (use schematic driven constraints placement)

Routing is crucial Connection Identifications

width of metals are specified by the schematic current, electro-migration, R, C requirements

Verification

Extraction and back annotation to the schematic

IC Flow


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Cell Layout

Cell full custom layout applies to the cells that are part of a family of buildingblocks, which have common abutment rules, performance characteristics,functionality

In general , use of Metal1 and Metal2 for cell layout

Compatibility to intended design flow : like all pins of standard cells on acommon pitch for easy and fast connection

Abutment includes consideration for power routing, substrate and cellconnections

Examples : Standard cell & Pad libraries

IC Flow


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Digital Circuit Implementation Flow

Custom Flow

Semi-custom Flow

Cell Based

Standard Cells Compiled Cells

Macro Cells

Array Based

Pre-diffused GATE Arrays

Pre-wired GATE Arrays

IC Flow


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Device Matching


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Two devices with the same physical layout never have quite the same

electrical properties.

Variations between devices are called mismatches.

Mismatches may have large impacts on certain circuit parameters, for

example common mode rejection ratio (CMRR).

By default, simulators such as SPICE do not model mismatches. The

designer must deliberately insert mismatches to see their effects.

Device Matching Overview


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Mismatches may be either random or systematic or combination of both.

Suppose two matched devices have parameters P1 and P2

Let the mismatch between the devices equal to = > P = P2 - P1

For a sample units, measure this : P

Compute sample mean m(P) and standard deviation s(P) and cell connections

m(P) is a measure of systematic mismatch

s(P) is measure of random mismatch

Types of Mismatches


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Random Mismatches are usually due to process variation

These process variations are usually manifestations of statistical variation, forex : scattering of dopant atoms

Random mismatches cannot be eliminated , but they can be reduced byincreasing device dimensions

In a rectangular device with active dimensions W by L , an areal mismatch canbe modelled as:

Precision matching requires large devices

Random Mismatches

P=kP

WL


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Systematic Mismatches may arise from imperfect balancing in a circuit

Ex: Differential pair mismatch generates an offset voltage

Usually, the circuit can be redesigned to minimize or even to completelyeliminate systematic offset

Systematic Mismatches also arises from gradients

Certain physical parameters may vary gradually across an IC.

Temperature

Pressure

Oxide thickness

Gradients can produce large effects

A 1 degree C change in temperature produces a -2mV in VBE which eqautes to 8%

variation in IC

Systematic Mismatches


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Devices on the same die match well (precision)

$(R) / R =~ 0.1%, $(C) / C =~ 0.1% For circuit characteristics , that depends on ratio of component values,

precise matching = accurate characteristics

To improve device matching , use devices with

Unit Elements

Large active area

Same orientation

Compact Layout

Minimum spacing

Dummy Segments

Common Centroid geometries

Layout Rules of Device Matching


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It cancel linear gradients

Require for moderate matching

Analyzing Gradients :

Assuming Linearity : The gradient is constant over the area

Electrical parameters depends linearly upon physical parameters

The magnitude of the mismatch equals the product of distance between thecentroids and the magnitude of the gradient along the axis of separation

Therefore , we can reduce the impact of the mismatch by reducing theseparation of the centroids

Centroid Matching Technique


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Rules for common centroids technique :

Coincidence

Symmetry

Dispersion

Compactness

How to find a Centroid ( assuming linearity)

If a geometric figure has an axis of symmetry, then the centroid lies on it

If a geometric figure has two or more axis of symmetry , then the centroid must lie at theirintersection

Centroid Matching Technique

Centroid Centroid


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The centroid of an array can be computed from the centroids of its segments

If all of the segments of the array are of equal size, then the location of centroidof the array is the average of the centroids of the segments

The centroid of an array does not have to fall within the active area of any of itssegments

Theoretically, A common centroid array should entirely cancel systematicmismatches due to gradients . Practically, it does not happen because ofassumptions

Two properly constructed array could have same centroid

Virtually, all precisely matched components in integrated circuits use common

centroids

The Centroid of an Array


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Inter-digitation Matching Technique

The simplest sort of common centroid array consists of a series of devices

arrayed in one dimension

One dimensional common-centroid arrays are ideal for long, thin devices, suchas resistors

Since the segments of the matched devices are slipped between one another toform the array, the process is often called inter-digitation

A

B

B

A


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Inter digitation Matching Technique

Certain arrays precisely align the centroids of the matched devices ( A, C).

These provide superior matching

Other arrays only approximately align the centroids. These provide inferior

matching. (B)

o n a x i sm e t r y o f d e v i c e A

A x i s o f s y m m e t r y

A B B A A B A B

( A ) ( B ) ( C )

A AB

C o m m o n a x i s o fs y m m e t r y

A x i s o f s y m m eo f d e v i c e B


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Some Other Techniques

Identical shape & size (Unit Elements)

Resistor Transistor Capacitor

Reference

Good

Bad


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Minimum Distance

Place devices as close as possible


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Cross Coupled common-centroid



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Same Orientation

Eliminatesmismatches arisingfrom anisotropicsubstrate, anisotropicprocess steps, packageinduced stress



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Dummy Devices

Place dummy devices at theend of array devices

Protects from processingnon-uniformity (etch-rate)



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PDK


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PDK : Process Design Kit

A Process design kit (PDK) is a collection of verified process models and process

data in the appropriate technology file formats (analog/mixed signal library), which

are designed to work with EDA IC tools and can be used to generate analog/mixed

signal IC.

It supports for fast and accurate silicon IC design.

The volume of information in a PDK can be huge and the presentation inconsistent

from foundry to foundry.

A PDK has data files which includes schematic symbols, SPICE models, Layout

Technology File, PCELLS, DRC rule-file, LVS rule-file, Extract rule-file and

scripts that run EDA tools to automate the generation and verification of design

data.

What is PDK


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Foundry document section describe the PDK documents, revision and dates while

the EDA section covers the tools, vendors and release dates supported. The device

section summarize the symbols, spice models, attributes, parametrized cells and

reports the verification of each device.

PDK changes for each technology : 180nm, 130nm, 90nm, 65nm etc. PDK primarily is used to focus on analog/mixed signal market.

Advantage of PDK

Design Productivity : IC designers can start design immediately and use entiredesign flow by using verified data sets.

Design Quality : Use of foundry guaranteed data ensures manufacturingsuccess.

Profitability : Reduces design cycle and a number of costly reworks.

Customer can focus on tape-outs instead of supporting design kits.

What is PDK


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It contains information specific to each design task and to specific design tools.

Example : Chartered PDK data maps to the Cadence Virtuoso Platform

What is PDK


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Process design kits that support a full custom design flow from schematic

entry to final layout verification.

PDK support Custom Flow


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Schematic symbols define available devices and their properties (device type , pins,

sizes etc.)

SPICE models are used for SPICE simulation

Layout Technology File defines layout environments, layers to be used with

attributes of layers and devices to be extracted.

PCELLS are cell layouts, generated automatically, or interactively based on

parameter input. PCELLS are written in scripting language e.g. LISA.

DRC rule-file is used for design rule check interactively at layout or in batch mode

for tape-out

LVS rule-file is used for interactive LVS check at cell layout or in batch mode for

tape-out

PDK Support Custom Flow

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