pd design 7

8/3/2019 pd design 7

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Ph: 080-40-788574 www.rv-vlsi.comRV-VLSI Confidential

1

Objective

Need for CTS

Revisit timing concepts and definitions

Introduction to the various steps involved in clock tree synthesis

After completion of this program students will be familiar with the CTS

flow,challenges in CTS, interdependencies and will be ready tosynthesize a clock tree for any project.


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2

Design Status before CTS

Placement completed

Power and ground nets- prerouted

Estimated congestion acceptable

Estimated timing acceptable (~ 0 ns slack)

Estimated max cap/ transition no violations

High fanout nets:

Reset, Scan Enable synthesized with buffers

Clocks are still not buffered.


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3

Clock Tree Synthesis

CTS: Clock Tree Synthesis

It's a kind of a tree to provide theclock to all of it's sinks (Binarytree, H-Tree etc.)

The basic of CTS is to develop

the interconnect that connect thesystem clocks to all the cells inthe chip that uses the clock

The primary task of CTS is varythe routing paths, placement ofclocked cells and clock buffers

to meet clock tree targets

Basics

Clock net are treated as idealduring synthesis

Logical proximity does notmean physical proximity of

related flops Clock net has a high fan out and

needs to be dealt withappropriately

Interconnect delays will degradethe quality of the clock signal


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4

Review Of Basic Terminology

PLL

Clock Period

Clock Latency

Source Latency

Network Latency

Clock Uncertainty

Setup & Hold

Constraints

Max Capacitance

Max Fanout

Max TransitionSkew

Global skew

Local skew

Useful skew


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5

PLL : Phase Locked Loop

Designers use low frequency crystalas on off-chip clock source

Reference Clock enters in the chip anddrives the PLL

It generates the desired stablefrequency on the chip

The PLL drives the clock distributionnetwork & one of it outputs used as afeedback in PLL

The main function of PLL is tocompare the reference clock anddistribution clock and match them withthe help of VCO, LF and PC.

PLL is very much sensitive to noise, soplacing the PLL in digital chip iscritical

Need to provide the power and groundlines around the PLL


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6

Clock Latency

INV

Rise=7Rise=7

Fall=4Fall=4

Rise=7Rise=7

Fall=4Fall=4

Rise=7Rise=7

Fall=4Fall=4

Rise=7Rise=7

Fall=4Fall=4

Rise=7Rise=7Fall=4Fall=4

CLK_aCLK_a

CLK_bCLK_b

INVINV INVINVINVINVINVINV

BUFBUF

Clock Latency = Tclk Tclk_a

Clock source latency is defined as the delay from Clock source to clock

definition port in your design

Clock network latency is defined as the delay from the Clock definition port to

clock sink of your design

It is also known as insertion delay (standard term)

Clock Latency = Tclk Tclk_b

Clock Definition Port

CLK


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7

Clock Uncertainty

The clock network delay uncertainty : Jitter

It is defined as the maximum difference of phase for a clock in oneclock cycle to other

The jitter can move launch edge of clock and capture edge of clock by

the jitter amountSources:

PLL oscillation frequency

Various noise sources like power supply noise

Two cases

Setup : Delayed the launch edge and early the capture edge Hold : Early the launch edge and delayed the capture edge


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8

Clock Skew

Flop 1ComboDelay

DQ

CK

Data

CLK

z

Buffer & Wire Delay

Flop 2CK CK

D

Clock skew for a particular clock is defined as difference in between insertion delays

Source of skews

Designed Variations : mismatch in buffer , load sizes, interconnect lengths

Process variations, Temperature variations

IR-DROP

Types : positive skew & negative skew

Skew range : 5-10% of clock period for your design


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9

Local Skew

D Q

FF1

D Q

FF3

D Q

FF4

A C

B

Din

CLK

B_out

0.38 ns

0.37ns

0.30ns

0.32 ns

D Q

FF2

C_out

Local Skew : Considered inbetween two flops which areinteracting logically with eachother in same clock domain

Here FF1 and FF2 areinteracting with each other solocal skew = 0.38 0.37 =0.01ns & FF3 and FF4 arealso interacting with eachother so local skew = 0.32 0.30 = 0.02ns

Local skew takes more runtimes and less buffers in yourdesign.

Must meet local skew


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10

Global Skew

Global Skew:It is consideredas the difference in the longestdelay path and shortest delaypath from clock definitionpoint to clock sink withing thesame domain

Here the global skew : 0.38 0.30 = 0.08ns

Global skews has faster runtime

Global skew add more buffers

in your design , so be cautiousabout it.

It impacts area constraints ofyour design and increasescongestion.

D Q

FF1

D Q

FF3

D Q

FF4

A C

B

Din

CLK

0.38 ns

0.37ns

0.30ns

0.32 ns

D Q

FF2


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11

Useful Skew

Flop 2CK

D

Flop 3

CK

D

Flop 1CK

D

CLOCK

Q

Q

Data input

Q

The useful skew concept is used tofix the setup violation

The same path should not violate thehold

This is a push/pull technique of

clock.Example: Let assume your path fromflop1 to flop2 is failing setup by -1ns& path from flop2 to flop3 is passingsetup by +1ns . Think ?

We use it very less these days in the

industry, because it again impactsyour skew in the design


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12

Setup & Hold

Setup time

For an edge triggered sequential element, the setup time is the time

interval before the active clock edge during which the data should

remain unchanged

Hold timeTime interval after the active clock edge during which the data should

remain unchanged


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13

CTS Specifications

Meet the buffering constraints

Maximum transition delay

Maximum load capacitance

Maximum fan out

Meet the clock tree targets Maximumskew

Min/Max insertion delay


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14

CTS Specifications

Typical specs which are used to design the clock tree are:

Clock skew

Clock Fanout

Clock Latency

Buffer levels


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15

CTS Flow

From Placement

Set Clock Common

Options

Synthesize the Clock

Tree (CTS)

Re-connect Scan

Chains

Enable propagated

Clocks

Post-CTS Placement

Optimization

Optimize Timing

Skew

Optimize Timing(Useful Skew CTO)

To Routing


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16

Clock Trees

Clock Tree : When you drive the all the sink pins of a particular clock from theclock port, it is known as the clock tree for that particular clock

Types :

H-Tree

Balanced Fanout Clock Tree

Binary Clock TreeWhen you synthesize your clock network with respect to particular clock knownclock tree synthesis

it consists of varying the routing paths

placement of clock buffers/cells

consideration of specification

After CTS your optimize your clock tree network to meet specific targets

skew


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17

Clock Tree

A path from the clock source to flops

Clock Source

FF FF FF FF FFFF FF FFFF FF


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18

Balanced Fanout Clock Tree

A path from the clock source to clock sinks

Clock Source

FF FF FF FF FFFF FF FFFF FF


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19

Binary Clock Tree

A path from the clock source to clock sinks

Clock Source

FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF


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20

H-Tree

4 Points4 Points 16 Points16 Points

H-Tree


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21

Clock Common Options

Clock Common Tree optionsused to set the different-2 optionsas shown in figure.


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22

Clock Common Options Constraints

Max Trans/Cap/Fanout

If specified at multiple places (Library,SDC, Default), it consider the smallestvalues.

if (Astro default values < SDC or Library),Verify with vendor and then proceed.

Max Buffer Level

By default it is defined 20. First let it be bydefault.

Want to change this number analyze thethings properly.

Max & Min Insertion Delay

Use this to control the min and maxinsertion delay.

By default , insertion delay in SDC have aPriority

We can choose to ignore SDC and Libraryconstraints.

If settings are too tight , violations may becreated


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23

Invoking Clock Tree Synthesis

Invoking of clock tree synthesishave the options as shown infigure on the right hand side.


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24

Clock Tree Begin and End

Clock tree begins at SDC-definedclock source.

Type of Astro-defined pins

Implicit pins: which tool definesby itself

Explicit pins: which user defines

Each pin comes into one of thecategory mentioned above.

Clock tree ends at Astro-definedstop pins

Two types of stop pins:

Sync pins: Clock pins ofsequential and macro cells

Ignore pins:Everything

else.

D Q

FF2

D Q

FF1

D Q

FF3

Gated

clock

start

Clock tree passes throughGating logic by default


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25

Sync pins and Ignore Pins

Sync pins:

CTS optimizes forbuffering constraints(maxtran/cap) and clock treetargets (clock skew,insertion delay)

Ignore pins: CTS adds a small buffer

to isolate all pins

ignores bufferingconstraints and clock tree

targets.

D Q

FF2

D Q

FF1Gated

clock

Clock tree passes throughGating logic by default

IP

clk_out

Implicit IGNORE pins D Q

FF4

D Q

FF3


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Explicit Sync Pins

The design spec requires that the delays from the clock port, through themux selects, to all output ports must be balanced.

1

0

clock

Skew and insertion

delay are ignored

Isolation BufferD Q

FF1

D Q

FF2

Dummy MUX is used to

match the delay

Implicit Ignore Pins

M

U

X

M

U

X


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27

Adding Explicit Sync Pins

How we can force CTS to balance these delays?

1

0

clock

Isolation BufferD Q

FF1

D Q

FF2

M

U

X

M

UX

Explicit sync pin

Skew and insertion

delay are optimized


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28

Optimization Behaviour

D Q

FF1

D Q

FF2

D Q

FF3

D Q

FF4

D Q

FF5

clock combo

create_clock

create_generated_clock

To different

clock domainor output port

To different

clock domain

or output port

To different

clock domain

or output port


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29

Optimization during CTS

Buffer sizing and Gate sizing

AfterBefore

FF

FF

FF

FF

FF

FF

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FF

FF

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FF

FF

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FF

FF

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FF

FF

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FF

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FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

2x3x 4x3x4x 4x


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Delay Insertion

AfterBefore

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

3x3x

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

3x3x

Delay Cell

4x 4x



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Buffer and Gate Relocation

AfterBefore

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

3x

3x

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FF

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FF

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FF

FF

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FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

3x3x4x4x 4x



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Dummy load

AfterBefore

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

3x3x

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

3x3x4x 4x



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Level Adjustment

AfterBefore

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

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FF

FF

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FF

FF

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FF

FF

FF

3x3x4x

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FF

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FF

FF

FF

FF

FF

FF

FF

3x3x4x

FF

FF

FF

FF

FF

FF

F

F

FF

FF



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Reconfiguration

AfterBefore

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

FF

3x3x

4x

FFF

F

FF

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FF

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FF

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FF

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FF

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FF

FF

FF

FF

FF

FF

3x3x4x

F

F

FF

FF



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Reconnect the Scan Chains

Scan chains were disconnected prior to placement to allow placement tofocus on the functional paths.

Reconnect scan chains so that they are included for hold time fixingduring the next optimization step

- Same grouping of FF, as traced prior to disconnect

- Different ordering : based on placement, to minimize routing

resources.


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Post CTS Placement Optimizations

Post CTS placementOptimizations

Stage : Post-CTS

Effort : Medium

Optimizations tasks : Fix Hold also


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Post CTS Placement Optimization : As needed

It can be executed iteratively, ifneeded.

If violations are too tight, betterto choose one option at a timewith high effort , Ex: Fix

Transition.


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Effect of Post CTS Placement Optimization

Fixing timing and max cap/tranviolations through logicoptimizations and cell relocationmay disturb the clock networks

FF may be moved . This can

affect the skew and insertiondelay.

Keep the size and location fixed


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Clock Tree Analysis

Clock tree analysis : dump theproper reports

Use proper clock name

Check skew (both global andlocal)


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Clock Tree Optimization

Further clock tree optimization ,if needed before routing


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Effects of CTS

Clock buffers added (lots of them!)

Congestion may increase

Non clock tree cells may have been moved to less ideal locations

Can introduce new timing and max tran/cap violations.

* How can you improve congestion and timing?


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Module Takeaway

After completion of this program students will be familiar with the CTSflow,challenges in CTS, interdependencies and will be ready tosynthesize a clock tree for any design.


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References

Algorithms for VLSI Physical Design Automation by Naveed A.Sherwani.

From Basics to ASICs by Harry Veendrick

Himanshu Bhetnagar, Advanced ASIC Chip Synthesis, SecondEdition, Kluwer Academic Publishers.

https://solvnet.synopsys.com

pd design 7

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