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Transcript of Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor...
![Page 1: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/1.jpg)
Pass Transistor Logic
![Page 2: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/2.jpg)
Agenda
Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated Electronics Static CMOS Logic Circuits Pseudo nMOS Logic Circuits Pass Transistor Logic Circuits Dynamic Logic Circuits Case Studies
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Pass Transistor Logic Circuits
nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
![Page 4: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/4.jpg)
nMOS Pass Transistor – Logic ‘1’ Transfer
![Page 5: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/5.jpg)
nMOS Pass Transistor – Logic ‘0’ Transfer
![Page 6: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/6.jpg)
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PASS TRANSISTORS IN SERIES
![Page 8: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/8.jpg)
PASS TRANSISTOR LOGIC CIRCUITS
nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
![Page 9: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/9.jpg)
TRANSMISSION GATES
NMOS pass transistor passes a strong 0 and a weak 1. PMOS pass transistor passes a strong 1 and a weak 0. Combine the two to make a CMOS pass gate which will
pass a strong 0 and a strong 1.
![Page 10: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/10.jpg)
TRANSMISSION GATE
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PROBLEMS WITH TRANSMISSION GATES
No isolation between the input and output. Output progressively deteriorates as it passes through
various stages.
However designs get simplified.
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TRANSMISSION GATE - LAYOUT
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PASS TRANSISTOR LOGIC CIRCUITS
nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
![Page 14: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/14.jpg)
Multiplexor
![Page 15: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/15.jpg)
Pass Transistor Logic Circuits
nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
![Page 16: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/16.jpg)
XOR gate
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PASS TRANSISTOR LOGIC CIRCUITS
nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
![Page 18: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/18.jpg)
D – Latch
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TIMING ISSUES
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D LATCH
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D - LATCH
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D LATCH – ALTERNATE CIRCUIT TOPOLOGY
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PASS TRANSISTOR LOGIC CIRCUITS
nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
![Page 24: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/24.jpg)
Static Flip Flop
0
1
D1
0
Q
ClkClk
Transparent when Clk=0
Transparent when Clk=1
At Clk= 0 1, Q = D. Else Q is held.
![Page 25: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/25.jpg)
D Flip Flop – Circuit Diagram
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D Flip Flop - Operation
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D Flip Flop - Waveforms
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Pass Transistor Logic Circuits nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
![Page 29: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/29.jpg)
Handling Clock Skew
Clk-in Clk
Clk'
![Page 30: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/30.jpg)
Pass Transistor Logic Circuits
nMOS Pass transistor – transmission properties Transmission Gates Transmission Gate Applications
Mux XOR D Latch D Flip Flop Clock Skew management
Pass Transistor Logic Families
![Page 31: Pass Transistor Logic. Agenda Introduction VLSI Design methodologies Review of MOS Transistor Theory Inverter – Nucleus of Digital Integrated.](https://reader031.fdocuments.us/reader031/viewer/2022031813/56649ca65503460f94968abd/html5/thumbnails/31.jpg)
Pass Transistor Logic Families
Complementary Pass Transistor Logic Family Dual Pass Transistor Logic Family Swing Restored Pass Transistor Logic Family
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Problems
Design 4 to 1 multiplexor using transmission-gates. Implement an XOR gate using minimum number of
transistors. Implement a full adder using transmission gates.
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Solution - 1
C'0
C0
C1
C'1
Y
A0
A1
A2
A3
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Solution - 2
C'0
C0 C'1
A0
A1
A2
A3
C1 Y
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XOR Gate
A B
AB