Parallel Routing for FPGAs based on the operator formulation Yehdhih Ould Mohamed Moctar & Philip...
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![Page 1: Parallel Routing for FPGAs based on the operator formulation Yehdhih Ould Mohamed Moctar & Philip Brisk Department of Computer Science & Engineering University.](https://reader035.fdocuments.us/reader035/viewer/2022062423/5697bf991a28abf838c918d7/html5/thumbnails/1.jpg)
Parallel Routing for FPGAs based on the operator formulation
Yehdhih Ould Mohamed Moctar & Philip Brisk
Department of Computer Science & EngineeringUniversity of California Riverside
Design Automation Conference (DAC 2014)San Francisco, CA, USA, June 1-5, 2014
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Runtime of circuit design is dominated by P&R
Maze Expansion consumes over 65% of Runtime
Large number of non-conflicting operations executed at each iteration
Motivation
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Application of Speculative Parallelism to FPGA routing
Use of non-blocking priority queues for the Maze Expansion
Implementation of the parallel router in VPR
Contribution
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Find a physical path for every signal in the circuit Disjoint-path problem; NP-complete
FPGA Routing
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S
T2T1
Pathfinder: Negotiation-based algorithm
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Routing Resource Graph (RRG)
2-LUT
in1 in2
out
wire1
wire2
wire3 wire4source
sink
out
wire4
wire2
in2in1
wire1
wire3
RRG represents the routing resources of the FPGA
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Serial Pathfinder
We Parallelize the Maze Expansion
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Maze Expansion Operation
PQ contains nodes that have not been fully explored
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Galois
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Parallel program = Operator + Schedule + Parallel data structure
Software framework for parallelizing irregular algorithms
Employ speculation based approach to parallelism
Operator formulation of algorithms
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Operator formulation of algorithms
Operator Computation at active
element Activity: application of
operator to active element
Amorphous data-parallelism Multiple active nodes can
be processed in parallel subject to neighborhood and ordering constraints
: active node
: neighborhood
Parallel program = Operator + Schedule + Parallel data structure9
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Maze Expansion in Galois
Threads speculatively explore the node of RRG Each Thread has a local Priority Queue 10
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We selected 10 of the largest IWLS benchmarks. We target 65nm CMOS (BPTM)
Benchmarks
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Maze Router Speedup Achieved up-to 5.5x speedup (Using 8 threads)
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Steady Scalability up to 8 threads
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Maze Router – Configuration Options (Normalized Speedup) STM PQ + Iteration Coalescing achieved 5.46x speedup
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Maze Router - Critical Path Delay (CPD)
# of Threads has no impact on Critical Path Delay (CPD) Parallel implementation achieved better CPD than VPR
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Conclusion & Future Work Speculative parallelism can be good choice for parallel CAD algorithms
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Achieved Near-linear speedup (up to 5.5x) over Serial FPGA Router.
Future work includes applying this speculative model to parallelize Placement.