Optics Communications 310 (2014) 187–192

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Optics Communications

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journal homepage: www.elsevier.com/locate/optcom

1.31–1.55-mm Hybrid integrated optoelectronic receiverusing low-loss quasi-monolithic integration technology

Yang Luo n, Yongqing Huang, Xiaomin Ren, Xiaofeng Duan, Qi WangState Key Laboratory of Information Photonics and Optical Communications, Institute of Information Photonics and Optical Communications,Beijing University of Posts and Telecommunications, Beijing 100876, China

a r t i c l e i n f o

Article history:Received 12 June 2013Received in revised form26 July 2013Accepted 26 July 2013Available online 9 August 2013

Keywords:Hybrid integrated receiverQuasi-monolithic integration technology(QMIT)Opto-electronic integrated circuit (OEIC)Top-illuminated planar structurephotodetectorEye diagram

18/$ - see front matter & 2013 Elsevier B.V. Ax.doi.org/10.1016/j.optcom.2013.07.063

esponding author. Tel.: +86 18810529167.ail address: mddr@163.com (Y. Luo).

a b s t r a c t

In order to integrate photonic devices with electronic devices to realize the low-loss hybrid integrateddevices. A wide spectral hybrid integrated optoelectronic receiver was fabricated by using quasi-monolithic integration technology (QMIT) in this paper. It consisted of a 8.5 GHz InGaAs photodetectorand a 1.25 Gbps mature transimpedance pre-amplifier (TIA) complementrary metal oxide semiconductor(CMOS) chip. The Au layer was deposited on a designed Si platform to form planar waveguide electrodewhich replaced a part of bonding wire, so it reduced the parasitic parameters of the optoelectronicreceiver, and then enhanced high-speed response characteristics and the stability of the hybridintegrated receiver. Finally, a 3 Gbps clear open eye diagram of the hybrid integrated optoelectronicreceiver was obtained.

& 2013 Elsevier B.V. All rights reserved.

1. Introduction

Demands for high-speed datacom and wireless communica-tions, such as a huge data streaming transmission, cloud comput-ing and real-time data streaming. The rapid development of dataservice prompts high-speed optoelectronics receivers to becomemain technology in the high-speed communication systems. Therequirements for these high-speed optoelectronics receivers arehigh-performance, compact size, high level of integration and lowmanufacturing cost [1]. Therefore, it is necessary to study low-lossand cost efficient chip-to-chip integrated solution [2].

Recently, high-speed optical interconnects for chip-to-chipintegration solution have received a lot of attention. Most of therecent progress targets are 40 Gbps/100 Gbps class array wave-length division multiplexing (WDM) systems. However, in anoptical receiver system, transimpedance pre-amplifier (TIA) playsan important role that converts the photodetector current intovoltage which only can be processed by behind end large-scaleintegration circuits (LSIC). Hence, most basic optoelectronic hybridintegrated receiver should base on the photodetector with TIAcomplementrary metal oxide semiconductor (CMOS) chip. Inte-grated photodetectors receiver based on CMOS LSIC had beenreported for optical communication system [3–8]. The reports

ll rights reserved.

presented in [3–6] are low-data-rate while [7,8] present high-data-rate integrated receiver systems. In high-speed applicationssystem, photonics devices and electronics devices are integratedtogether to reduce bandwidth limitation of electronic links wireand reduce the level of interferences generated by the electricallinks under increasing bit rate also points towards the use of theoptical system. So different forms of integration solutions arepresented [9]. Up to now, there are two main integrated solutionsto integrate the photonic devices and electronic devices: (1) Theon-chip integrated solution [10]. Because the on-chip integrationprogram must reserve a certain area as a carrier platform forholding the photonic devices [11], it is suitable for ultra-large-scaleintegrated circuits and custom circuit modules [12]. (2) The inter-chip integrated solution [13]. The inter-chip integrated solutionhas an advantage that its carrier platform is manufactured inde-pendently, it is not necessary to reserve a certain areas in theproduction of integrated circuits to save the expensive CMOS diearea, so it is more suitable for optoelectronic multichip modules(OE-MCM's) using the bonding wires to integrate on a platform.Hence, the total cost will be significantly reduced. Overall, forimplementing optical interconnects, the optoelectronic integratedmodule has to have as small a footprint and power consumption aspossible [8]. Moreover, it is inevitable that the bonding wire isused in a device package, therefore, when short the bonding wireand narrow bonding pad size to encapsulate thereby reducing theparasitic parameters introduction to enhance the totally per-formance of the hybrid integrated receiver [7]. The packaging

Y. Luo et al. / Optics Communications 310 (2014) 187–192188

technology is a key step to affect the modern high-speed hybridintegrated receiver, and it is also the final step of applications. Afailure design of package will lead to the dramatic decline of theentire device characteristics, so the research efforts of the pre-viously chips and development were in vain [14].

In this paper, we describe a low-loss optical-electronic linksystem designed for gigabit optical fiber communication applica-tion. The combination of a InP-based top-illuminated planarstructure photodetector (PD) and a 1.25 Gbps CMOS TIA withautomatic gain control (AGC) and monitor achieves CMOS/InPhybrid integrated optoelectronic receiver. The monolithic photo-detector and CMOS LSIC chip are bonded on a Si substrate platformby metal medium chip bonding technology. The devices wereplaced on the silicon platform by the suitable position to shortenthe distance of the bonding wire, and the distance between thebonding pad and the package pin, to reduce parasitic parametersand further to improve the overall performance of the hybridintegrated receiver. It had been reported that the CMOS TIA withAGC and photodetector were built on a common silicon carrier byinter-chip integrated solution [15–17]. But in this experiment,there are three purposes for the customized production of thesilicon platform. (1) Multiple chips were placed on the Si platformwhich is conducive to the integration of waveguide devices.(2) The silicon material is the common material which is currentlymanufactured LSIC. Some characteristics of the LSIC can besimulated by the silicon substrate via CMOS processing. (3) Themetal bonding technology with superior stability and good ther-mal conduction is compatible with the CMOS process. Comparedwith other hot melt bonding technology, it is conducive to releasechip heat. Due to this low loss integrated solution (hardly any lossand the parasitic parameter introduction), The 3-dB bandwidth ofthe hybrid integrated receiver is 1.69 GHz, Resistive Load (RL)¼50 Ω. Therefore, clear eye diagram at 3 Gbps is measured for thedata transmission performance of hybrid integrated receiver. Usingthis low-loss hybrid integrated technology, it was found that thedevices not only can be packaged in the small space to achievemore functions, but also improve the overall performance of theoptoelectronic hybrid integrated receiver. The following sectionspresent the system design as well as measurement results.

2. Design and fabrication

2.1. Top-illuminated planar structure photodetector

The epitaxial layer structure of the high-performance photo-detector was grown by metal-organic chemical vapor deposition

Fig. 1. (a) Schematic diagram of photodetector and (b) to

(MOCVD) on semi-insulating InP substrate. The structure of thetop-illuminated planar photodetector consists of a 1.5-mm-thickN+ InP buffer layer (45�1018 cm�3), a 0.05-mm-thick undopedInP collector layer (1�1016 cm�3), a 2-mm-thick undoped InGaAsabsorption layer (1�1015 cm�3) for low capacitance and highquantum efficiency, a 1.0-mm-thick N� InP diffusion block layer(1�1016 cm�3), and a-0.15-mm thick N� InGaAs contact layer(1�1016 cm�3) was transformed into P+ layer by ion implantation.The epitaxial wafer was immersed in H2SO4: H2O2: H2O¼1:1:2 topartial etch InGaAs to form a contact ring. Subsequently, A SiO2

film diffusion mask layer was deposited onto the epitaxial layer,standard photolithography was used to form a 55-mm-diameteropening circle to accomplish the diffusion window. The Diethyl-zine (DEZn) was introduced through the diffusion window in theMOCVD reactor. Subsequently, standard photolithography wasused again to remove the SiO2 diffusion mask ring and then theunetched InGaAs contact ring was exposed. Then, the Pt-Ti-Pt-Auwas deposited onto the unetched InGaAs contact ring layer to forma 55-mm-diameter electrode ring as the P ohm contact electrode.Pt-Ti-Pt-Au was evaporated and patterned by a lift-off process toform the p-type bonding pad. The polished backside was coatedwith Pt-Ti-Pt-Au as n-contact metal pad. Thenceforward the270 mm�270 mm photodetector chip was fabricated. The verticalP–I–N structure photodetector with a 55-mm-diameter of theincident surface has a 2.0 mm thick intrinsic In0.53Ga0.47As absorp-tion layer in order to maintain the high quantum efficiency andlower dark current. Fig. 1(a) shows the schematic diagram ofphotodetector. Fig. 1(b) shows the top-view photograph of thefabricated photodetector.

2.2. Hybrid integrated receiver

A 1.25 Gbps mature pre-amplifier electronic circuits (typical�30 dBm optical sensitivity, 3 dBm overload input when assum-ing photodetector responsibility of 0.9 A/W, extinction ratio of10 dB and bit error rate (BER) of 10�10, drive a load 100 Ω) wereused in this experiment. The CMOS chip is mainly used in gigabitethernet passive optical network (GEPON) optical network unit(ONU), Gigabit Fast Ethernet (GFE), small form factor (SFF), smallform-factor pluggables (SFP), gigabit interface convertor (GBIC)and other optical fiber communication fields. Because the InP-basedPD and CMOS process chip are quite sensitive to temperature andstress-induced degradation, the bonding medium materials shouldbe chosen to have high thermal conductivity and stress-relief. Forthat reason, we chose AuSn20 alloy (eutectic temperature: 280 1C)as the bonding medium. Symmetry face bonding pads are bothused in the bottom of the photodetector and as metal bonding

p-view photograph of the fabricated photodetector.

Fig. 3. Dark current curve of the single photodetector.

Y. Luo et al. / Optics Communications 310 (2014) 187–192 189

medium at the same time. The AuSn20 alloy metal bondingtechnique was used to fabricate the hybrid integrated receiverand the receiver consisted of an InP photodetector and a low-costpure CMOS process chip which were designed according to the0.18 mm design rule. Specific steps are as follows: First, a semi-insulating silicon platform carrier is fabricated to use the standardCMOS processing including cleaning, dicing and so on. Second, a400 nm thick SiO2 layer is deposited on top of the silicon substrateto prevent the silicon substrate from conducting electricity to theCMOS chip. The Si wafer is cut into the 1.2 mm�1.4 mm chip.Third, A rectangle of SIO2 layer area where was subsequentlyplaced on Au as a bonding pad to soldering n-contact metal pad ofthe PD was removed by using the wet etch. The AuSn20 alloy asmetal bonding medium was used between Au bonding pad andn-contact electrode of the PD that they were bonded togethersecurely. The P electrode of the PD attached to the input port of theTIA chip. The CMOS chip was placed on the top of the SiO2 layer bymetal bonding technique which uses AuSn20 alloy as the bondingmedium. Finally, the bonding wire was used to attach the bondingpads of the CMOS chip to the package corresponding pin-out. Sisubstrate platform not only provides a platform to place deviceson a major to-can package shell, but also serve as a heat sink for itsgood thermal conductivity [18]. After to-can package, we test thehybrid integrated receiver on a test printed circuit board (PCB).The kind close up of the proposed hybrid integrated receiver isshown in Fig. 2.

Fig. 4. 3-dB bandwidth of the single photodetector.

3. Measurement results

3.1. Performance of the single photodetector

The dark current of the single photodetector is less than1�10�10 A at a reverse bias of 5 V. It increases rapidly over thereverse bias voltage of 55 V. The dark current curve of the singlephotodetector is shown in Fig. 3. By contrast, the dark currentperformance is better among the available conventional PDs[19,20] and buried heterostructure photodetector (BH-PD) [21]when bias voltage is over �30 V. The capacitance of the singlephotodetector is 0.42 pF at reverse voltage (VR)¼5 V, f¼1 MHz.Reverse voltage characteristics and capacitance characteristics arefar beyond the dual-wavelength mesa-type photodetector [22].But the capacitance of the single photodetector which wasfabricated in this report was much higher than the commercial

Fig. 2. The kind close up of the proposed hybrid integrated receiver.

Y. Luo et al. / Optics Communications 310 (2014) 187–192190

mesa-type PDs [21]. This high capacitance characteristic is deter-mined by the planar-type structure. At �3 V bias, the singlephotodetector responsivity is 0.9 A/W at 1310 nm, and it is0.95 A/W at 1550 nm, the 3-dB bandwidth at 1550 nm is8.5 GHz. The quantum efficiency of the single photodetector canbe estimated by

η¼ R� ℏCqλ

ð1Þ

where η is the quantum efficiency. ħ is the Planck constant. C is thespeed of light. q is the charge of the electron. λ is the wavelength ofincident light. Then, at the reverse bias of 3 V, the externalquantum efficiency of the single photodetector was 85.4% at1310 nm, 76.2% at 1550 nm, respectively. The frequency responseof the single top-illuminated planar structure photodetector isshown in Fig. 4.

3.2. Performance of hybrid integrated receiver

The cut-off frequency of hybrid integrated receiver was mea-sured at 1550 nm basing on the use of a 38 GHz SHF modulatordriver, a 40 GHz intensity LiNbO3 modulator and a NEW FOCUSstandard 45 GHz infrared (IR) photodetector. Results were given bya 40 GHz PNA Network analyzer from Agilent Technologies

Fig. 5. Test board with a packaged hybrid integrated receiver.

Fig. 6. The normalized optical frequency response of hybrid integrated receiver.

(E8363C) at the output power of vertical bare fiber with 1 mW.Firstly, a test board was fabricated to test the hybrid integratedreceiver. The hybrid integrated receiver was packaged in the shellwhich was soldered to the test board and output port pin of thepackage shell was attached to a sub-miniature-A (SMA) radiointerface. Besides the power supply interface of hybrid integratedreceiver was connected to the power supply source pin. The testboard with a packaged hybrid integrated receiver is shown inFig. 5. Due to chip output was the differential signal, one of theoutput signal pins was suspended. The measurement results areobtained by the applied bias of �3.3 V and �10 V on thephotodetector respectively. The measurements showed that thebandwidth of hybrid integrated receiver was about 1.69 GHz.Because the carriers of the photodetector reached saturationvelocity at the bias of �3 V, when the bias of photodetector wasboosted, the bandwidth variation is negligible, and then thefrequency response test curves of the hybrid integrated receiverunder two different voltage conditions are almost consistent. Thenormalized optical frequency response of hybrid integrated recei-ver is shown in Fig. 6.

In order to verify the signal transmission performance of thehybrid integrated receiver, a radio frequency (RF) signal from apseudorandom bit sequence (PRBS) generator was used to drivemodulator and then it modulated the optical signal. One of theoutput channel pins of the hybrid integrated receiver was con-nected to a Agilent sampling oscilloscope. The eye diagrams fromthe hybrid integrated receiver were obtained at 800 Mbps, 1 Gbps,1.25 Gbps, 2 Gbps and 3 Gbps under �3 V bias of photodetector.The hybrid integrated receiver was packaged in the shell whichwas soldered on the test board (Fig. 4). Because the tube shell pinsare too long, the eyelids of the eye diagrams are too thick. The datatransmission performance was detected at only 3 Gbps, since weconsidered the transimpedance pre-amplifier chip bandwidthlimitation. Eye diagrams at 800 Mbps, 1 Gbps, 1.25 Gbps, 2 Gbpsand 3 Gbps under �3 V bias of photodetector is shown in Fig. 7.

4. Discussion

In this work, we have demonstrated the possibility to integratemultiple chips on a Si platform. When there is a Very Large ScaleIntegration(VLSI) circuit which can replace the Si platform, thehybrid integrated device can integrate more functions takingvertical space rather than horizontal space or customizing thespecial package footprint. In this experiment, common photode-tector five pins package was used. Once there are suitable electricsignal process circuits based on Si, this solution would realize thelarge scale integration of photonic device and electronic device.Furthermore, we can obtain the following four conclusionsthrough the experiment. (1) There are some chip islands in thetraditional standard package shell, the chip must be placed on thechip island, so packaging multiple chips are relatively time-consuming and complicated to operate. However, it was signifi-cantly reduced the operating times when the chips were placed onthe platform. (2) There are lots of contact wires and the distance ofthe contact wire is too long in traditional packaging solutions,therefore, it will introduce a lot of parasitic parameter. But in thissolution, the chips are more closer and contact wires are moreshorter that will benefit to realize high-speed performance. (3) Inthis experiment, the performance of metal medium bondingtechnology was verified, it can achieve to bonding the Si-basedchips and the III–V materials devices. (4) The effect of siliconsubstrate as a heat sink has been verified that although the hybridintegrated devices used in the excess-standard conditions (such ashigher voltage than rated voltage; high light power). It remainsvery stable for a long time.

Fig. 7. The eye diagrams at 800 Mbps, 1 Gbps, 1.25 Gbps, 2 Gbps and 3 Gbps under�3 V bias of photodetector.

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Due to this low-loss opto-electronic integrated circuits (OEICs)integration solution shorted the bonding wire, the value of theparasitic capacitance which limited the resistance–capacitance (RC)bandwidth in hybrid integrated device was extremely low (almostno parasitic parameter). The Au-pad layer plays an important role as

an electromagnetic waveguide. Once the high-speed photodetectorand CMOS processing circuit were applied in this solution by usingflip–chip technology, the integration solution will fabricate coplanarwaveguide (CPW) electrodes on the silicon platform surface to gainlower performance loss. It will enhance the overall performance ofthe hybrid integrated receiver. Undoubtedly this integration solu-tion is suitable for integrating array devices. We can imagine that ifwe use the thickness of the gold layer and thickness of the SiO2 toadjust each device height, let it make the height of the top of therespective devices which are at the first layer almost consistent, andthen greater than the first layer of these silicon chips use the CMOSprocessing technology and the through-silicon vias (TSVs) technol-ogy. So manufacture of multilayer devices would to be the stackintegrated chip.

5. Conclusion

In summary, we had integrated the InP-based top-illuminatedplanar structure P–I–N photodetector with an active CMOS circuitsby using the low temperature metal medium bonding techniqueon a Si-based platform. The dark current of the single photode-tector is less than 1�10�10 A at a reverse bias of 5 V. The responserange of the photodetector is from 900 nm to 1650 nm, thephotodetector responsivity is 0.95 A/W at 1550 nm, we setRL¼50 Ω, then the single photodetector obtains a 3-dB bandwidthexceeding 8.5 GHz at a wavelength of 1550 mm. The capacitance ofthe single photodetector was 0.42 pF at VR¼5 V, f ¼1 MHz. A cleareye diagram at 3 Gbps is measured for the data transmissionperformance of hybrid integrated receiver. With the applicationsand development of the photonics devices which have high-speedand high bandwidth and electronic devices, the low-loss hybridintegrated technology is compatible with standard CMOS proces-sing and will be extensively used for heterogeneous devicesintegration in optical fiber communication system. It will towardnew generations of complicated hybrid integrated structuresmerging high-speed photonic and electronic devices.

Acknowledgment

The author wishes to thank Yongqing Huang, Xiaofeng Duan, andXiaomin Ren for their encouragement. The author would also like tothanks Professor Xianjie Li for his assistance. This work was sup-ported by the National “973” Program of China (No. 2010CB327600),the National Nature Science Foundation of China (No.61274044) andBeijing Nature Science Foundation (No. 4132069), the FundamentalResearch Funds for the Central University (No. BUPT2011RC0403), theProgram for Chang Jiang Scholars and Innovative Research Team inthe University (No. IRT0609), the National Natural Science Founda-tion of China (No. 61020106007), and the “111” Project of China(No. B07005).

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