Paper-3 FPGA Based Gate and RTL Level Fault Injection Technique and Tool for Fault Tolerance Designs

7/28/2019 Paper-3 FPGA Based Gate and RTL Level Fault Injection Technique and Tool for Fault Tolerance Designs

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International Journal of Computational Intelligence and Information Security, March 2013, Vol. 4 No. 3,ISSN: 1837-7823

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FPGA based Gate and RTL Level Fault Injection Technique and Tool for

Fault Tolerance Designs

P Venkata Konda Reddy1, Akhilesh Kumar2, Amrit Anand3

1PG scholar in Department of E&C Engineering, NIT Jamshedpur, Jharkhand, India2Associate Professor in Department of E&C Engineering, NIT Jamshedpur, Jharkhand, India

3UG scholar in Department of E&C Engineering,BRCM CET, Bahal, Bhiwani, Haryana, IndiaAbstract

This paper presents the FPGA based fault injection technique and tool which allows the designers to injectthe faults at gate and RTL level, where structural model of a digital system is written in VHDL. The approachutilizes the FPGA devices for emulation of VHDL designs. By using this tool we can observe the systembehavior before and after injecting the faults into the fault tolerance designs. The developed tool provides boththe features of hardware based and simulation based fault injection features including good graphical userinterface. As a case study double ALU based fault tolerance processor was taken and evaluated using SpartanFPGA.Keywords: Fault Injection, s-a-0, s-a-1, SEU, Graphical User Interface, gate Level, RTL Level.

1. IntroductionIn last two decades there has been a growing interest in techniques for validating the fault tolerance

properties of critical digital systems and evaluation of their reliability. Because of rapid increase in thetechnology the integration level of electronic systems are increasing, which is making difficulty to generate anacceptable degree reliability as a consequence of the higher chance of faults in the system that can affect thebehavior of the system.

So fault injection is a valid solution to the problem of dependability validation. There are so many faultinjection techniques have been developed and practically experimented. They are grouped into the followingtypes.

1. Simulation based fault injection2. Physical based fault injection

Hardware Based fault injection Software based fault injectionIn simulation based fault injection a model of the system under test, which can be developed at different

abstraction levels, is simulated by altering the logical values of the model elements.

Hardware fault injection uses additional hardware to introduce faults into the target systems hardware.Typical hardware based fault injection tools are Messalina [1], FIST [2], MARS [3]. Software fault injectionchanges the contents of memory or Registers to simulate the occurrence of Hardware or software faults.FERRARI [4], DOCTOR [5], Xception [6]. Hardware fault injection has disadvantages like low probability andactions of target system are not easy to observe and result is difficult to collect. Simulation based fault injectionhas advantage of high controllability and observability but very high time consuming. One way to provide goodcontrollability and observability including with speed in the fault injection experiments is to use FPGA basedfault injection techniques and tools.

An effecting FPGA base fault injection tool must support properties as below

1) High controllability and observability.2) High speed fault injection techniques.3) Capability of injection of multi- Level fault models.


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2. Modeling approach of Fault Models

Fault modeling is realized by building fault models. The developed tool supports the followingsynthesizable fault models for injecting into any VHDL designs, which are designed at Gate Level and RTL

Level.

Permanent faults Transition faults Single event upset faults (or) Bit-flip.Fault injection process can be done by applying some extra gates and wires to the original design description

and modifying the target VHDL model of the system. One of these extra wires is the Fault injection system (FIS)which playing the key role in the fault injection experiments. If a FIS takes the value 1, fault would be activatedand if it takes the value 0, the fault would become inactive.

2.1. Permanent faults

For supporting the permanent faults in VHDL design, the developed tool nominates wires for faultinjection and applies the FIS signal with one extra gate. So by selecting the FIS signal high at fault injectiontime, the permanent fault into the specified wire will be injected.

Figure 1: Synthesizable s-a-0 fault model Figure 2: Synthesizable s-a-1 fault model

Figure 1 and figure 2 show the synthesized model for supporting the permanent faults those are s-a-1and s-a-0 faults. Our developed tool uses timer for determining the fault injection time and duration time andinjection module at the time of fault injection. Once the injection time reached one timer starts counting until thespecified time at the time of fault injection.

2.2. Transient faults

For injecting a transient fault, after reaching the fault injection time, the FIS signal will be made highand the timer, which have been loaded with the duration of the transient fault injection start to count. Therefore,the FIS will be high (at logic 1) for the specified duration of time. As similar to the permanent fault, theadditional wire (TX) will be used and each wire, namely X will be replaced with TX.


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Figure 3: Synthesizable transient fault model2.3. Bit-Flip faults

The fault model that is used by the tool at this level is bit-flip (or single event upset). SEUs are therandom events and may flip the content of the memory element at unpredictable times. Our tool generatesmodified circuit for each memory element that is specified for fault injection. The modified circuit for supportingbit flip fault model is shown in below figure 4.For supporting the bit-flip model, tool produces the additionalsignals such as Bit and FIS with one multiplexer.The inverted input will go to the flip-flop for the next clockwhen the FIS and bit are 1. The fault injection manager part of tool is responsible for setting and resetting theFIS and bit signals.

Figure 4: Synthesizable Bit-flip fault model

3. Design of fault injection tool

This tool environment consists of three parts

(1) Source code modifier and fault list generator.(2) Fault injection manager(3) Results capturing with FPGA emulation

Source code modifier and fault list generator are the software parts of the tool. This is implemented with twotools.

Eclipse editor

C programs to insert faults on a specific port.

These are located on host (PC) computer. Separate C scripts are developed for inserting each fault. AGUI facilitates invoking the scripts by mouse right click. Fault injection manger is responsible for performing


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the real time fault injection. The fault injection manager is implemented in VHDL. The fault injection manager ishaving

VHDL package (dynamically updated by C programs) Fault scheduler Fault insertion componentsThe VHDL package is implemented to capture all the constants, type definitions, component

declarations and fault injection time for each fault. The package also consists of number of total faults. ThisVHDL file is automatically updated by C programs every time when a fault is injected in code. The faultscheduler runs multiple counters to schedule each fault with required fault activation time and fault propagationtime as per the package. The fault scheduler produces output fault number which is currently being active. Thismodule generates the parallel fault injection signals for every fault. These signals are routed to all fault sites.

Fault insertion components are gates with FIS (fault injection signal) control to inject the faults whenthe FIS is active high. These components instances are automatically made whenever faults are injected.Result analysis will be carried out with FPGA emulation results and fault list generated by C program. Theanalysis shall summarize the fault responses for each injected fault.

4. Fault injection process

The fault injection process for our tool is as shown in the following figure5.

Figure 5: Fault Injection process


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4.1. The setup/fault injection phase

Main objective of this phase is to generate modified VHDL source code of the test design. In this phasethe VHDL model is opened through the tool editor and then user should select the signal or port to inject thefaults. After selection of type of faults to be injecting and fault injection properties such as fault duration, fault

latency, bus size, injection time the tooltakes the responsibility to generate modified synthesizable source codein addition with fault injection manager which is responsible for real time fault injection in FPGA board.In the next step the modified source code is synthesized by using synthesis tool which generates the gate levelsource code which is used to configure the FPGA.

4.2. The emulation phase

In this phase we emulate fault free model and fault model. Main objective of this phase is to capture theinformation of the performance parameters of the emulated designs. This capture results are sent to the hostcomputer through serial port.

4.3. The evaluation phase

In this phase evaluation of the model is achieved by tracing difference between golden run and faultytrace files. This can be done by the result analyzer. Analyzer is a part of our tool.

5. Case study

Double ALU based fault tolerance processor [8] has been chosen as benchmark to be evaluated by thistool. This is a synthesizable VHDL model. The architecture of processor has been coded by VHDL in 520 linesof code. We chose it because of its high reliability for soft errors. This processor can be used as a typicalcalculator. A fixed point system is used to implement calculations.

Figure 6: Processor architecture

The faults are injected in different parts of the processor as ALU1, ALU2, data registers, and decoder.

The trace files contain the data from address bus, data buses and registers. Three different workloads were run onthe target system: multiplication, division and square root operations are performed to test processor.


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5.1. List of faults injected and tested

Table 1: list of fault models and fault targets

Type of fault Fault model No.of Faults

Injected

Fault target

Permanentfaults

Stuck-at-0 62 Comp, ALU1,d_reg1

Stuck-at-1 50 d_reg1, ALU2

Transient Faults Transient 10 Comp,ALU1,d_reg3

Bit-FlipFaults

Flip-to-0 40 d_reg4, ALU2

Flip-to-1 43 d_reg2, ALU1

Table 2: Performance results

Work Load Observation Points % of errors in programresults

Division ALU1 3.5%

d_reg1 2.9%

Square Root ALU1 4.5%

d_reg1 3.2%

The workloads used to run on this processor are division and square root. Table 1 shows the number offaults and types of faults injected in the specified parts of the processor. Table 2 presents the workloadsimplemented with injected faults in processor. From the output of result analyzer we can say that our processor ismore reliable for division than the square root.

6. Simulation and Emulation results

Modelsim Xilinx Edition is Used for simulation of the individual modules and final top level (afterinserting the faults) module. Xilinx ISE is used for synthesis, P&R and bit file generation. Xilinx Chipscope isused for capturing the results at FPGA emulation phase.

6.1. Fault_tolerant_processor (without injecting faults)

Figure 7: simulation results of Fault_tolerant_processor (without injecting faults)


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6.2. Fault_tolerant_processor (After injecting faults)

Figure 8: simulation results of Fault_tolerant_processor (After injecting faults)

7. Synthesis results

7.1. without injecting faults

Figure 9: chip scope pro results without injecting faults into Processor


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7.2. After injecting faults

Figure 10: chip scope pro results with injecting faults into Processor

8. Conclusion

This paper presented a totally new fault injection tool that injects faults based on the synthesizability ofthe circuit models described by VHDL. It has been shown that how the tool was designed and implemented andhow it injects faults into models. Fault injection into VHDL models has been designed at provided abstractionlevels and fault models in VHDL. System emulation is achieved by using SPARTAN 3E FPGA. Furthermoresystem evaluations are done by comparing signal values of faulty circuit with fault free one that gathered duringemulation. Finally emulation of two bench marks those are multiplication, division and square root were done.The results show that the effects of faults were more on d_reg1, d_reg2 than the ALU1, ALU2.

9. References

[1] I Arlat, Y Crouzet, and IC Laprie, "Fault Injection for Dependability Validation of Fault-Tolerant ComputerSystems," Proc. 19th Ann. Ins Symp. Fault-Tolerant Computing, IEEE CS Press, LosAlamitos,Calif, 1989,

pp. 348-355(massaline).[2] Gunnetlo, I Karlsson, and I Tonn, "Evaluation of Error Detection Schemes Using Fault Injection by Heavy-

ion Radiation," Proc. 19th Ann. Int'! Symp.Fault-Tolerant Computing,IEEE CS Press, Los Alamitos, Calif,1989, pp. 340-347.(FIST)

[3] I Karlsson, I Arlat, and G. Leber, "Application of Three Physical Fault Injection Techniques to theExperimental Assessment of the MARS Architecture," Proc. Fifth Ann. IEEE Intel WorkingConf.Dependable Computing for Critical Applications, IEEE CS Press, Los Alamitos, Calif, 1995, pp. 150-161.

[4] G.A. Kanawati, N.A. Kanawati, J .A. Abraham, FERRARI: A Flexible Software-Based Fault andErrorInjection System, IEEE Trans. on Computers, Vol 44, N. 2, February 1995, pp. 248-260

[5] S. Han, K.G. Shin, and B.A. Rosenberg, "Doctor: An Integrated Software Fault-Injection Environmentfor Distributed Real-Time Systems," Proc. Second Annual IEEE Intel Computer Performance and

Dependability Symp.,IEEE CS Press, Los Alamitos, Calif, pp. 204-213, 1995.(DOCTOR)


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[6] J . Carreira, H. Madeira, and J.G. Silva, "Xception: Software Fault Injection and Monitoring in ProcessorFunctional Units," Proc. Fifth Ann. IEEE Inn Working Conf.Dependable Computing for CriticalApplications, IEEE CS Press, Los Alamitos, Calif, pp. 135-149, 1998.

[7] E. Jenn, J . Arlat, M. Rimen, J. Ohlsson, J . Karlsson, Fault Injection into VHDL Models: the MEFISTOTool, Proc. FTCS 24, 1994, pp. 66-75

[8]

M. Nikoladis, Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies, IEEEVTS,199, pp. 86-94[9] Z. segall, D. Vrsalovic, D.Siewiorek,D.Yaskin, J.Kownacki, J . Barton, D . Rancey, A. Robinson, and T.Lin,

FIAT fault injection based automated testing environment, in Proc. 18th Int.symp. On Fault tolerantcomputing(FTCS-18), 1988.

[10] L. Antoni, R. Leveugle and B. Feher, Using Run-Time Reconfiguration for Fault Injection in HardwarePrototypes, Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,2002, pp. 245-253.

[11] P. Civera, L. Macchiarulo, M. Rebadengo, M. S. Reorda, M. and A. Violante, Exploiting FPGAforaccelerating fault injection experiments, Proc. of the International On-Line Testing Workshop, 2001pp.9-13.

[12] P. Civera, L. Macchiarulo, M. Rebadengo, M. S. Reorda, M. and A. Violante, FPGA-based FaultInjectionfor Microprocessor Systems, Proc. of the Asian Test Symposium, Nov. 2001, pp. 304-309.

Paper-3 FPGA Based Gate and RTL Level Fault Injection Technique and Tool for Fault Tolerance Designs

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