P-MOS field inversion voltage enhancement via a chromic acid clean
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Solid-Sfale Ekcfmnics Vol. 22. pp. 43-684 NOTES P-MOS FIELD INVERSION VOLTAGE ENHANCEMENT VIA A CHROMIC ACID CLEAN (Received 12 June 1978; in mised form 29 December 1978) INTRODUCTION EXFZRIMENTS Historically the development of MOS integrated circuits has required a method for increasing the field oxide inversion voltage while not influencing any of the normal transistor parameters (see Refs. [l-g]). A method where the enhanced field oxide is self aligned to ,the transistor gate regions and where no additional complex processing steps are required is the ultimate goal. Here we describe such a method which is suitable for p-channel MOS integrated circuits constructed on [ill] oriented silicon wafers. For p-channel MOS integrated circuits the procedure starts by performing the initial wafer clean in chromic acid. Then a high temperature wet field oxide is grown and chromium atoms are incorporated into this oxide; these chromium atoms increase the field oxide inversion voltage. In this experiment the geld oxide is grown at 105oqC; for temperatures lower ,than 1WC the inlbrence of the chromium atoms is reduced. blext; the diffusion- gate masking step removes the field oxide in the diffusion-gate regions. Where the field oxide is removed there will be no influence of the chromium atoms, hence we have a self aligned (field oxide to gate oxide) method for enhancing the field oxide inversion voltage. A group of [l I I] oriented 3.0-3.1 ohm-cm phosphorus doped wafers, group A, were cleaned in chromic acid. A second group, B, were cleaned via a HsSQ:HsOs solution followed by a Hf: HsO dip. A field oxide of 1.3p was then grown on all wafers. The wafers were then organized into pairs from both cleaning groups and the field oxide etched back to five intermediate oxide thickness values. The value of the resulting oxide thickness was calculated from a measurement of the value of the oxide capaci- tance in the accumulation mode. MOS transistors and CV dots were then fabricated via a contemporary silicon gate process beginning with the gate oxidation step. High frequency CV (see Refs. [M-13]) and held inversion voltage measurements were made on each wafer in five separate locations. The measured voltage shift in the CV measurement between a wafer in group A and a wafer in group B was in agreement with the diRerence in field inversion voltage measured on the transistors. The difference in field inversion voltage as a function of oxide thickness is given in Fig. I. Our experiences show a reproducable and stable increase of IO-15V for the field oxide inversion voltage and no reduction in the junction breakdown voltage. In an effort to determine how the chromium atoms are incorporated into the held oxide we have performed experiments to determine the position and quantity of these atoms under certain assumptions. In order to further study the behavior of the chromic acid clean three additional groups of wafers were processed; these groups were [Ill] p-type, [1Of1] n-type, and [IOO] p-type. For these materials ahtmium CV dots were made over an etched back field oxide. High frequency CV measurements were then made as before and the results are shown in Fig. 2. Also shown in Fii. 2 are additional results for [Ill] n-type material which was pro- cessed as a check. The spread in data shown in Fig. 2 is attributed to the simplified processing. THEORY The simplest model for the enhanced field oxide inversion voltage is that chromium atoms are incorporated into the field oxide and each contributes a positive charge. In this case the field inversion voltage difference AVTF between two samples, one with and one without chromium, is given by (see Ref. [9]), I4 I2 I e I e AvTF = - (x,x - xc,) Ncr. &OX (2) In this sample case a linear relationship between A V~F and X,,, will be found. For a series of samples with different values of X0.; NC, and X, are determined from the slope and intercept of the linear relationship. For any other distribution a linear rela- tionship between AVTF and X0. will not be found. This simple explanation of charged chromium atoms incorporated into the field oxide requires that the magnitude of N, and X. be in- dependent of substrate doping type and crystal orientation. As shown next we did find a linear relationship between A VrF and X0., an independence on substrate doping type, however, our results show a dependence on crystal orientation. T/ / /i / /I ‘6 k ?I /!lopc NC,-- 2.2 x IO” cm-* / 0.2 0.4 0.6 0.6 1.0 I.2 1.4 xc., (/I) Fig. I. Field inversion voltage shift, AVrp, due to chromium atoms vs field oxide thickness, X0., for [l Ill n-type silicon. 683
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Transcript of P-MOS field inversion voltage enhancement via a chromic acid clean
Solid-Sfale Ekcfmnics Vol. 22. pp. 43-684
NOTES
P-MOS FIELD INVERSION VOLTAGE ENHANCEMENT VIA A CHROMIC ACID CLEAN
(Received 12 June 1978; in mised form 29 December 1978)
INTRODUCTION EXFZRIMENTS
Historically the development of MOS integrated circuits has required a method for increasing the field oxide inversion voltage while not influencing any of the normal transistor parameters (see Refs. [l-g]). A method where the enhanced field oxide is self aligned to ,the transistor gate regions and where no additional complex processing steps are required is the ultimate goal. Here we describe such a method which is suitable for p-channel MOS integrated circuits constructed on [ill] oriented silicon wafers.
For p-channel MOS integrated circuits the procedure starts by performing the initial wafer clean in chromic acid. Then a high temperature wet field oxide is grown and chromium atoms are incorporated into this oxide; these chromium atoms increase the field oxide inversion voltage. In this experiment the geld oxide is grown at 105oqC; for temperatures lower ,than 1WC the inlbrence of the chromium atoms is reduced. blext; the diffusion- gate masking step removes the field oxide in the diffusion-gate regions. Where the field oxide is removed there will be no influence of the chromium atoms, hence we have a self aligned (field oxide to gate oxide) method for enhancing the field oxide inversion voltage.
A group of [l I I] oriented 3.0-3.1 ohm-cm phosphorus doped wafers, group A, were cleaned in chromic acid. A second group, B, were cleaned via a HsSQ:HsOs solution followed by a Hf: HsO dip. A field oxide of 1.3 p was then grown on all wafers. The wafers were then organized into pairs from both cleaning groups and the field oxide etched back to five intermediate oxide thickness values. The value of the resulting oxide thickness was calculated from a measurement of the value of the oxide capaci- tance in the accumulation mode. MOS transistors and CV dots were then fabricated via a contemporary silicon gate process beginning with the gate oxidation step.
High frequency CV (see Refs. [M-13]) and held inversion voltage measurements were made on each wafer in five separate locations. The measured voltage shift in the CV measurement between a wafer in group A and a wafer in group B was in agreement with the diRerence in field inversion voltage measured on the transistors. The difference in field inversion voltage as a function of oxide thickness is given in Fig. I.
Our experiences show a reproducable and stable increase of IO-15 V for the field oxide inversion voltage and no reduction in the junction breakdown voltage. In an effort to determine how the chromium atoms are incorporated into the held oxide we have performed experiments to determine the position and quantity of these atoms under certain assumptions.
In order to further study the behavior of the chromic acid clean three additional groups of wafers were processed; these groups were [Ill] p-type, [1Of1] n-type, and [IOO] p-type. For these materials ahtmium CV dots were made over an etched back field oxide. High frequency CV measurements were then made as before and the results are shown in Fig. 2. Also shown in Fii. 2 are additional results for [Ill] n-type material which was pro- cessed as a check. The spread in data shown in Fig. 2 is attributed to the simplified processing.
THEORY
The simplest model for the enhanced field oxide inversion voltage is that chromium atoms are incorporated into the field oxide and each contributes a positive charge. In this case the field inversion voltage difference AVTF between two samples, one with and one without chromium, is given by (see Ref. [9]),
I4
I2
I e I
e A vTF = - (x,x - xc,) Ncr.
&OX (2)
In this sample case a linear relationship between A V~F and X,,, will be found. For a series of samples with different values of X0.; NC, and X, are determined from the slope and intercept of the linear relationship. For any other distribution a linear rela- tionship between AVTF and X0. will not be found. This simple explanation of charged chromium atoms incorporated into the field oxide requires that the magnitude of N, and X. be in- dependent of substrate doping type and crystal orientation. As shown next we did find a linear relationship between A VrF and X0., an independence on substrate doping type, however, our results show a dependence on crystal orientation.
T/
/ /i
/
/I
‘6 k
?I /!lopc NC,-- 2.2 x IO” cm-*
/
0.2 0.4 0.6 0.6 1.0 I.2 1.4
xc., (/I)
Fig. I. Field inversion voltage shift, AVrp, due to chromium atoms vs field oxide thickness, X0., for [l Ill n-type silicon.
683
Notes
-10 t
-12 t
“\ P
\
process on [I I l] oriented silicon wafers to enhance the field oxide inversion voltage. With a silicon gate process the influence of the chromium atoms is to introduce nominally 2.2 x IO” cm-* posi- tive charges at the wafer-oxide interface. This charge and a conventional field oxide will increase the field oxide inversion voltage by IO-15 V. The influence of the chromic acid clean is removed by etching the field oxide in the normal diffusion-gate masking step hence, the enhanced field oxide is self aligned to the gate regions. This self alignment and the simplicity of the chromic acid clean makes this method ideal for manufacturing p-channel MOS integrated circuits.
Acknowledgements-1 thank Mr. Anthony Pyne, Dr. P. Denham and Dr. K. Eisele for their comments on this work.
ITT In~ermetall Hans-Bunte Srtasse 19 7800 Fniburg Wesf Germany
FRANCIS HARPER
Fii. 2. Field inversion voltage shift, AVrp, due to chromium atoms vs field oxide thickness, X,,=, for: X 111 l] n-type, 0 [ll I]
p-type, [IOO] n-type and A [lOO] p-type silicon.
DISCUSSION
The shift in the field inversion voltage due to the chromic acid clean deoends linearly on the oxide thickness as shown in Figs. 1 and 2 fo; [ll I] n- or b-type silicon wafers. This dependence is in agreement with the simple result given by eqn (2). By fitting can (2) to the data given in Fig. 1 we ‘conclude that 2.2 X ldl’ cm-’ positively charged &o&urn atoms are located at the wafer oxide interface. The result for [ill] p-type material shown in Fii. 2 is in agreement with this conclusion.
1. H. Yamamotot, M. Shiiaishi and T. Kurosawa, 1%9 IEEE ht. Solid-State Cit. Conf. Louis Winner, New York, p. 40 (1%9).
2. W. M. Penney el al., MOS Integrated Circuik pp. 116-122 and 171-176. -Van Nostrand Reinhold, New York (1972).
3. P. Richman and J. Hayes, Electronics 45, 111 (1972). 4. K. H. Christie and W. S. Johnson, Inf. Electron Deu. Meeting,
Washington, DC., p. 464. IEEE, New York (1973). 5. S. A. Abbas, C. A. Barile and R. C. Dockerty, Inl. EIccrron
Dsu. Meeting, Washington, D.C., p. 371. IEEE, New York (1973).
6. J. D. Sansbury, IEEE Trans. E/ectron Deu. ED 20,473 (1973). 7. 3. W. Hanson, R. J. Huber and J. N. Fordemwalt, Inr.
Electron Deu. Meeting, Washington, DC., p. 383. IEEE, New York (1974). From measuring the field oxide threshold voltage on standard
wafers over several months we believe that the density of chromium atoms is 2.0-2.5 X 10” cm-‘. In addition this is true for the chromic acid temperature from 100 to 140°C.
The measurements on [lo01 n- or p-type wafers given in Fig. 2 show no influence from the chromic acid clean. Since the chromium atoms are located at the wafer-oxide interface this result requires that the bonding of the chromium atoms on [lOOI silicon is such that they are not in a charged state.
8. N. Kuboto, T. Shibata, K. Ohuchi, K. Hjtabayashi and S. Haruichi, Inl. E/e&m Deu. Meeting, Washington, D.C.. p. 295. IEEE, New York (1975).
9. E. H. Snow, A. S. Grove, B. E. Deal and C. T. Sah, J. Appl. Phys. 36, 1664 (1%5).
10. L. k. Terman, So/id-Sk Eleclron. 5,285 (1%2). 11. A. S. Grove. B. E. Deal. E. H. Snow and C. T. Sah, Solid-St.
CONCLUSION
Elecmn. 8,’ 145 (1%5). 12. K. H. Zaininger and F. P. Heinman, Solid-State Tech. 13,49
(1970). A chromic acid clean prior to a high temperature wet field 13. K. H. Zaininger and F. P. Heinman, So/id-State Tech. lo,46
oxidation can be used with a p-channel MOS integrated circuit (1970).
Solid-slate Efectnmics Vol. 22, pp. W-6& Pergamon Press Ltd., 1979. Printed in Great Britain
EMISSION COEFFICIENTS FOR ELECTRON AND HOLE TRAPS IN SILICON
(Received 12 August 1978; in noisedfom 5 January 1979)
Transient capacitance measurement techniques are valuable deep levels on the same plot of thermal emission rate vs tem- means of &dying emission from electron and hole traps in perature. Such plots have been made by Martin cl aL[tl and SCmiconductors because of their sensitivity and simplicity. Mitonneau et al. [+I for electron and hole traps in GaAs and have Emission data have been published for many-deep impurities in been found useful in inter-relating impurity studies in diflerent silicon in recent years but no summary has been made of the laboratories.
Fiie 1 shows accumulated data for the electron emission coefficients plotted as T*/e,, vs ltXHl/T to match the Martin and
tG. M. Martin, A. Mitonneau and A. Mircea, Eleelmn. I&. 13, Mitonncau presentation. It is assumed for the purpose of these 191 (1977). plots that the capture cross sections are indcpcndeat of tem-
SA. Mitonneau, G. M. Martin and A. Mircea, Electron. Lell. 13, pcraturc so that corrections are not needed to the raw energy 666 (1977X levels, and the degeneracy factors for the levels have been taken
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