Separate Extraction Technique for Intrinsic Donor- and Acceptor-like Density-of-States over Full-Energy Range Sub-Bandgap in Amorphous

Oxide Semiconductor Thin Film Transistors by Using One-Shot Monochromatic Photonic Capacitance-Voltage Characteristics

Hagyoul Bae, Sungwoo Jun, Hyunjun Choi, Chunhyung Jo, Yun Hyeok Kim,

Jun Seok Hwang, Jaeyeop Ahn, Sung-Jin Choi, Dae Hwan Kim, and Dong Myong Kim

School of Electrical Engineering, Kookmin University Jeongneung-ro, Seongbuk-gu, Seoul 136-702, Republic of Korea

Abstract

We report an extraction technique based on experimental data

for intrinsic donor- and acceptor-like subgap density-of-states

(DOS) over the full-energy range (EC<E<EV) by using one-shot

monochromatic photonic capacitance-voltage (MPCV)

characteristics in n-channel a-IGZO TFTs.

Author Keywords

Amorphous oxide semiconductor thin-film transistors; indium-

gallium-zinc-oxide; density-of-states (DOS); donor- and acceptor-

like DOS; extraction; photonic capacitance-voltage measurement.

1. Introduction

Amorphous Indium-Gallium-Zinc-Oxide thin film transistors

(a-IGZO TFTs) are known to be prospective devices for possible

applications to active-matrix organic light-emitting diode displays

(AMOLEDs) and flexible displays due to process at a low

temperature, large uniformity, and high carrier mobility [1].

Among electrical properties, experimental modeling and

characterization of the subgap density-of-states (DOS) is

important to estimate the reliability and stability caused by the

fabrication process, layout, and long-term performance associated

with robust circuits and systems. There have been works on the

analysis and extraction of subgap DOS in a-IGZO TFTs [2-3].

Especially, a quantitative analysis of the subgap DOS for

instability under the negative/positive bias illumination stress

(N/PBIS) has become a significant issue [4-5].

In this work, we report a technique for extraction of the full-

energy range subgap DOS (gD(E) & gA(E)) by using a

capacitance-voltage data under dark and photonic states with

subgap optical source (h=Eph≈2.6eV<Eg) as a monochromatic

photonic capacitance-voltage (MPCV) technique. Through the

proposed technique, it is possible to extract the full range subgap

DOS over the bandgap in the active amorphous semiconductor

layer. Using only one-shot C-V measurement as a function of the

gate bias (VGS), the subgap DOS can be characterized for the

dependence on material, fabrication process, and electrical stress

of the active layer. We expect that the proposed method is a

powerful tool for characterization of amorphous active layers in

TFTs without iteration procedure and/or complicated calculation.

2. Device Structure

Fig. 1 shows the schematic of the fabricated a-IGZO TFTs

with a staggered bottom-gate structure. For the formation of

source/drain (S/D) electrodes, Mo is sputtered at RT and patterned

by dry etching. A passivation layer (SiOX; thickness = 200 nm)

was deposited on the top of TFTs. The channel width (W), the

channel length (L), and gate-to-S/D overlap length (Lov) are

designed to be W = 24 μm, L = 12 μm and Lov = 4.8 μm,

respectively.

Gate insulator

Gate

Glass

Etch stopper

a-IGZO

Passivation

DrainSource

Fig. 1. The schematic of integrated a-IGZO TFT with the

used inverted staggered bottom gate structure.

3. Proposal of Extraction Technique for Donor- and Acceptor-like Subgap DOS with Monochromatic photonic Capacitance-Voltage Characteristics (MPCV)

0.00

0.05

0.10

0.15

0.20

-15 -10 -5 0 5 10 15 2010

-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6 D

rain

Cu

rren

t, IDS [

A]

Gate-to-Source Voltage, VGS

[V]

Dra

in C

urr

en

t, I

DS [

A]

Sample A

WxL=25x25 m2

TIGZO=50 nm

VDS

=0.1 V

a-IGZO TFTs

0 5 10 15 200

4

8

12

16

Sample A

Dra

in C

urr

en

t, I

DS [A

]

Gate-to-Drain Voltage, VDS

[V]

VGS

= 4V ~ 20 V, 4 V step

(b)(a)

Fig. 2. The measured (a) IDS-VGS curve in linear scale and log scale, and (b) IDS-VDS curve of a-IGZO TFTs

Measured transfer characteristics (IDS-VGS) and the output

(IDS-VDS) characteristics of the fabricated a-IGZO TFTs are shown

in Fig. 2 (a) and (b), which were measured using Agilent 4156

semiconductor parameter analyzer at room temperature (RT)

under a dark condition. The typical DC parameters are obtained to

be VT=1.4 [V], the subthreshold swing SS=0.4 [V/dec], and the

ION/IOFF ratio=1.4106. Fig. 3 shows the concepts of the proposed

monochromatic photonic capacitance-voltage method for

extraction of subgap DOS over subgap energy. Fig. 3(a), (b)

shows the energy band diagram for extracting gD(E) and gA(E),

separately. The trapped electrons generated from localized trap in

specific energy by employing an optical source

(h=Eph≈2.6eV<Eg). In the Fig. 3(c), photo-responsive charges

excited from donor-like trap states (gD(E)) are dominant in

depletion region (VON<VGS<<VFB). In contrast, charges generated

from acceptor-like trap states (gA(E)) are dominant in

accumulation region (VFB<<VGS<VT).

Distinguished Poster Paper P-14 / H. Bae

SID 2013 DIGEST • 1033ISSN 0097-966X/13/4403-1033-$1.00 © 2013 SID

VGS1VGS3

VFB

Photo darkCm[F]

gD(E)

dominant

gA(E)

dominant

VGS[V]

VGS5

VGS4

VT

VON VGS2 VGS6

(c) (d)

Fig. 3. (a), (b) The energy band diagram for concept of

extracting of gD(E) and gA(E) in depletion region (VON<VGS<<VFB) and weak accumulation region (VFB<<VGS<VT) under photonic state (c) schematic view of C-V characteristics under dark and photonic states with VGS. (d) photographic view under photonic state

Extraction range : Eph ≈ 2.6 eV

ECEV

Incident ray (Green)

0 eV2.6 eV

gTD(E):tail state

gTA(E):

tail state

gDA(E):deep state

gD(E) gA(E)Superposition of exponential tail and deep

states from extracted gD(E) and gA(E)

≈A

CDA TA

DA TA

C

( )

exp expN Nk

g E

E E E

T T

E

k

instability/reliability issue

T

D

VD

TD

DD

D

V

D

( )

exp

exp

g E

E EN

kT

E EN

kT

gDD(E):deep state

Fig. 4. Schematic diagram for energy distribution of subgap

DOS over full energy range in AOS TFTs based on monochromatic photonic capacitance-voltage method. (gTA(E) and gDA(E) : exponential tail and deep acceptor states, gTD(E) : exponential tail donor state).

The energy distribution of donor- and acceptor-like DOS in

AOS TFTs is shown in Fig. 4. It is described by a superposition of

exponential tail and deep states. The tail and deep acceptor states

related to process, active materials, and structure are characterized

with optical source. Furthermore, the tail donor states related to

negative bias and illumination stress are obtained by an incident

ray (≈532 nm) to photon energy (Eph≈2.6 eV). Therefore, we can

extract subgap DOS from conduction band (EC) to almost valence

band (EV) in active layer of AOS TFTs by one-shot photonic C-V

measurement. Fig. 5 shows cross-sectional view and setup for the

C-V measurement of n-channel a-IGZO TFTs with an inverted

staggered bottom gate. Fig. 5 (a) and (b) show an equivalent

capacitance model under dark and photonic states. Capacitive

equivalent circuit with photo-responsive capacitance (Cph,D)

include the carriers generated from the localized traps in the

amorphous active layer. Therefore, the measured capacitances

under dark state (CD,m) [F], photonic state (CP,m) [F], and

source/drain overlap capacitance (Cov) as a function of VGS can be

CIGZOChannel region (Leff)

InsulatorGate

Source Drain

Cox

uac

~

Vsweep

+

-

+

-

Cdep

Cph,D

Iph

CIGZO

Cdep

Cph,D

Photo (Green)

Depletion

region

Lm

Fig. 5. A cross sectional view and setup for C-V

measurement of n-channel a-IGZO TFTs with an inverted staggered bottom gate and equivalent circuit under dark (black) and photonic (green) states in depletion region (VON<VGS<<VFB).

described as

ov dep ov D,m

dep

D,m GS ov dep ov D,m

1

( )

C C C CC

C V C C C C

(1)

dep ph,D ov

P,m GS dep ph,D ov

( )1[F]

( ) ( )

C C C

C V C C C

(2)

IGZO oxov ov

IGZO ox

2 [F]C C

C WLC C

(3)

with Cox=εox/Tox[F/cm2], CIGZO=εIGZO/TIGZO[F/cm2] [6], and

depletion capacitance Cdep[F]. As shown in Fig. 5, the channel

region is fully depleted under the gate-bias VGS<<VFB; the flat

band voltage. Also, the capacitance (Cph,D) caused by the charges

excited from the localized states in the energy range ((EC-Eph)~EF)

is described as

P,m dep ov P,m dep ov

ph,D

ov P,m

( ) [F]GS

C C C C C CC V

C C

(4)

In order to obtain gD(E) at a specific energy level, the

extracted ΔCph,D for a differential VGS (or ϕS) from experimental

C-V data is obtained from

ph,D GS_j ph,D GS_j+1 -3

ph,D

eff IGZO

F cm .C V C V

ΔCW L T

(5)

Finally, we extract gD(E) through

ph D -1 -3

D

i F GS_j i F GS_j+1

( ) eV cm

( )( ) ( )( ) with j=1, 2, 3.

2

ΔCg E =

q

, E - E V < E < E - E V

,

(6)

We also note that the photo-responsive charges generated

from acceptor-like trap states (gA(E)) in the energy range ((EC-

Eph)~EF) are dominant in the accumulation region (VGS>VFB) as

shown in Fig. 6. Therefore, dark and photonic C-V data can be

modeled as

D,m GS ox m acc GS

1 1 1

( ) ( )C V C WL C V

(7)

P,m GS ox m acc GS ph,A GS

1 1 1

( ) ( ) ( )C V C WL C V C V

(8)

with the accumulation capacitance Cacc and additional capacitance

Cph,A for the optically generated charges from localized traps over

the energy ((EC-Eph)~EF). Combining Eq.(7) with Eq.(8), Cph,A [F]

can be obtained through

P,m D,m

ph,A GS ox

ox P,m ox D,m

( ) .

C CC V = C -

C - C C - C

(9)

P-14 / H. Bae Distinguished Poster Paper

1034 • SID 2013 DIGEST

For the differential gate bias ΔVGS (or ϕS) as a measurement step,

we obtain ΔCph,A and gA(E) through

ph,A GS_k+1 ph,A GS_k -3

ph,A

eff IGZO

F cmC V C V

ΔCW L T

(10)

ph,A -1 -3

A

F i GS_k+1 F i GS_k

( ) eV cm

( )( ) ( )( ) with k=3, 4, 5.

2

ΔCg E =

q

, E - E V < E < E - E V

(11)

Channel region (Leff)

InsulatorGate

Source Drain

Cox

uac

~

Vsweep

+

-

+

-

Cacc

Cph,A

IphCacc

Cph,A

Photo (Green)

Accumulation

region

Lm

Fig. 6. A cross sectional view and setup for C-V

measurement of n-channel a-IGZO TFTs with an inverted staggered bottom gate and equivalent circuit under dark (black) and photonic (green) states in accumulation region (VFB<<VGS<VT).

4. Extraction of Intrinsic Subgap DOS The extraction of intrinsic subgap DOS is based on the

previous de-embedding the parasitic capacitance through C-V

measurement with structure parameters (Lov, Lm, W, L, etc.). Fig. 7

shows a concept for the de-embedding of the parasitic

capacitances (Cpar=(Cpar,S+Cpar,D)×Apar [F]) and obtaining the

overlap capacitance (Cov=(Cov,S+Cov,D)×2WLov [F]) as a part of

the intrinsic capacitance (Cint) including modulated channel

capacitance (CCH) by VGS in the active layer. The measured

capacitance-voltage characteristics under dark (CD,m) and

photonic state (CP,m) depend on the gate bias (VGS) (oxide

capacitance (Cox [F/cm2])).

Cpar

COV

Cm [F]

Cint

Under photo

state

(Green)

Under

dark state

VGS [V]

Weak

accumulation

region

Depletion

region

accumulation

region

CCH

(a)

(b)

Fig. 7. (a) The schematic view of measured capacitance (b) dark and photonic C-V data after de-embedding VT-shift by photovoltaic effect and parasitic capacitance.

In the measured capacitance under dark state (CD,m) and

photonic state (CP,m), the minimum capacitance Cmin [F] under full

depletion (OFF) state at the gate bias (VGS) much below the flat

band voltage(VG <<VFB) can be modeled as

min par,S par,D par ov,S ov,D ovC C C A C C WL (12)

with the parasitic area (Apar) [7]. This is a sum of Cpar,S and Cpar,D for

the parasitic area caused by a specific layout and overlap

capacitances (Cov,S, Cov,D) for the overlapped region of the gate (G)

and source (S) /drain (D) metal contacts. The Cov [F] for TFTs with symmetric source and drain overlap length (Lov) is described by

ox IGZOov ov,S ov,D ov ov

ox IGZO

2 2C C

C C C WL WLC C

(13)

with Cox=εox/Tox [F/cm2] and CIGZO=εIGZO/TIGZO [F/cm2].

On the other hand, the maximum capacitance Cmax [F] under a

strong accumulation (ON) state at the gate bias much above the

threshold voltage (VGS >>VT) is described by Fig. 8 shows an

equivalent circuit including source/drain parasitic capacitance in

C-V configuration. The parasitic source/drain capacitances (Cpar,S

and Cpar,D) between source/drain and gate metal are parallel with

intrinsic capacitances (CCH, Cov,S, and Cov,D) in active layer.

max par int par ox mC C C C C WL (14)

Precision LCR meter

Cox

COV,D

Cpar,D

CCH

ES

vac

VDC

+

-

+

-

COV,S

Cpar,S

Source Drain

Insulator

Gate

Active

Layer

Fig. 8. Cross sectional view of a-IGZO TFTs and setup for

C-V measurement.

with CCH as the channel capacitance in the active channel under dark

state and Lm as the metallurgical length of the bottom gate. Using eqs.

(12) and (13), the parasitic capacitance Cpar [F] is obtained from

par min ovC C C (15)

Therefore, we extract the intrinsic capacitance Cint,d and Cint,p in

the dark and photo state by de-embedding the parasitic

capacitance as

int,d GS D,m GS par( ) ( ) [F]C V C V C (16-1)

int,p GS P,m GS par( ) ( ) [F].C V C V C (16-2)

For extraction of the intrinsic subgap DOS (gD,int(E)), Cint,d

[F], and Cint,p [F] are combined to be

int,d GS ov par dep par

1 1 1

( )C V C C C C

(17)

int,p GS ov par dep ph,D par

1 1 1.

( )C V C C C C C

(18)

In the same way, for extraction of gA,int(E), Cint,d [F], and Cint,p [F]

can be model by

int,d GS ox m par acc par

1 1 1

( )C V C WL C C C

(19)

int,p GS ox m par acc ph,A par

1 1 1

( )C V C WL C C C C

(20)

We note that the threshold voltage shift (ΔVPV) by the photovoltaic

effect can be occurred in the measurement under photo state. In order to

eliminate this phenomenon [7], we shift Cint,p-VGS curve for ΔVPV by the

charges (ΔQPV) resulted from photovoltaic effect in eqs. (21-1) and (21-

2). Then Cph,D(VGS) and Cph,A(VGS) [F] as an additive component under

photo state without VT shift is described as

int,p GS PV dep

ph,D

ov int,p GS PV

ov int,p GS PV dep ov

ov int,p GS PV

( )

( )

( ).

( )

C V V CC

C C V V

C C V V C C

C C V V

(21-1)

int,p GS PV int,d GS

ph,A ox

ox int,p GS PV ox int,d GS

( ) ( )

( ) ( )

C V V C VC C

C C V V C C V

(21-2)

Distinguished Poster Paper P-14 / H. Bae

SID 2013 DIGEST • 1035

5. Experimental results and Discussion

(a) (b)

(c) (d)

Fig. 9. (a), (b) Extraction of intrinsic full range subgap DOS

(c), (d): subgap DOS before (blue line) and after (red line) de-embedding parasitic capacitance).

Extraction sequence for obtaining intrinsic full energy range

subgap DOS (gD,int(E) and gA,int(E)) after de-embedding parasitic

capacitance components and photovoltaic effect is shown in Fig.

9. we measure dark and photonic C-V curves at saturated optical

power (Popt=5 mW). At the second step, shift of threshold

voltage (VT) caused by photovoltaic effect as well as parasitic

capacitance are eliminated as Fig. 7 (b). Then, extracted gD,int(E)

and gA,int(E) is shown in Fig 9(a) and (b). To compared with

extracted subgap DOS (open symbol) before de-embedding

parasitic components, intrinsic subgap DOS (red line : Fig. 9 (c)

and (d)) slightly decrease in deep and tail energy level over

subgap. We note that subgap DOS in AOS TFTs is confirmed to

be overestimated due to parasitic capacitances between

source/drain and gate metal overlap. Therefore, we can extract

the intrinsic subgap DOS over full energy range only for the

active layer. Also, we verified that C-V characteristics before

and after photo-responsive measurement are not changed.

Therefore, our proposed method is applicable to reliability and

instability assessment through one-shot dark and photonic

measurement. For the energy distribution of gD,int(E) and

gA,int(E), the nonlinear relation between the surface potential S

for the energy level can be obtained from the VGS-dependent C-

V data through

FB GS

GS VFB

D,m D,m

S,A GS S,D GS

ox ox

1 , 1 [eV]V V

V V

C CdV dV

C C

(22)

Fig. 9 (e) shows extracted gD,int(E) and gA,int(E) from the

MPCV can be modeled as a superposition of deep and tail states

in exponential relations as

V VD,int TD,int DD,int

TD,int DD,int

( ) exp expE E E E

g E N NkT kT

(23)

C CA,int DA,int TA,int

DA,int TA,int

( ) exp exp .E E E E

g E N NkT kT

(24)

Extracted parameters obtained from before and after de-

embedding Cpar are comparatively summarized in Table I. As a

result, we verified that the DOS after de-embedding parasitic

components is smaller than initial DOS values.

Table I. Extracted full energy range subgap DOS

parameters after de-embedding parasitic components.

6. Conclusions

We reported a MPCV technique based on experimental data for

extraction of the subgap DOS over the full energy range through

the subgap photo-responsive C-V characteristics of n-channel a-

IGZO TFTs. In particular, in our proposed method, we applied de-

embedding technique to obtain parasitic area-independent

intrinsic subgap DOS (gD,int(E) and gA,int(E)). Thus, full energy

range intrinsic subgap DOS could be fully separated by de-

embedding the parasitic capacitance with overlap areas between

the gate and the source/drain metal. The extracted intrinsic subgap

DOS is fully separated into donor- and acceptor-like states

(gD,int(E) and gA,int(E)) by using one-shot C-V measurement as

first approach based on experimental data. The proposed method

can be a powerful tool for a robust characterization of structure-,

material-, process-, and stress-dependent variation of the intrinsic

subgap DOS in amorphous oxide semiconductor TFTs without

simulation and complicated equations. Furthermore, we expect

that the extraction of parasitic area-independent gD,int(E) and

gA,int(E) through the proposed technique is useful for systematic

design of AOS-based circuits, optimizing the fabrication process,

material engineering to improve stability, and to explore

prospective thin-film materials for mass production-level AOS

TFTs to be innovatively used in near future.

7. Acknowledgements This work was supported by the National Research Foundation

of Korea (NRF) grant funded by the Korea government (MEST)

(No. 2010-0013883 and 2009–0080344). CAD softwares were

supported by IC Design Education Center (IDEC).

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[2] K. Nomura, et al., Nature., vol. 432, no. 7016, pp. 488-492,

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[2] H.-H. Hsieh, et al., Applied Physics Lett., vol. 92, no. 13, p.

133503-1, 2008.

[3] C. Chen et al., IEEE Trans. Electron Devices, vol. 56, no. 6,

pp. 1177-1183, 2009.

[4] Y. Kim et al., IEEE Trans. Electron Devices, vol. 59, no. 10, pp.

2689-2698, 2012.

[5] Y. Kim et al., IEEE Trans. Electron Devices, vol. 59, no. 10, pp.

2699-2706, 2012.

[6] S. Lee et al., Solid-State Electronics, vol. 56, no. 1, pp. 95-99,

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2013.

P-14 / H. Bae Distinguished Poster Paper

1036 • SID 2013 DIGEST