OXU311x PCB Design Guidelines...Chapter 3 PCB Layout You can achieve USB 3.0 and SATA electrical...

by PLX Technology

OXFORDStorage Solutions

© PLX Technology, Inc. 2011. All Rights Reserved.

OXU311x PCB Design Guidelines

Version 1.00April 18 2011GS-0109

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OXU311x PCB Design Guidelines

© PLX Technology, Inc. 2011. All Rights Reserved. The information in this document is proprietary and confidential to PLX Technology. No part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from PLX Technology.

PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time.

PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology products.

PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.

All product names are trademarks, registered trademarks, or servicemarks of their respective owners.

Document number: GS-0109

GS-0109, Version 1.00ii © PLX Technology, Inc. 2011. All Rights Reserved.

GS-0109, Version 1.00© PLX Technology, Inc. 2011. All Rights Reserved. iii

Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v

Revision Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi

Chapter 1 Component Selection

Serial Flash Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Power Supply Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Chapter 2 Crystal Selection

Crystal Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Crystal Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Chapter 3 PCB Layout

Initial Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

USB 3.0 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

SATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Internal Switch Mode Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Serial Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

General Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

REXT and Crystal I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Chapter 4 Reset Guidelines

Contents OXU311x PCB Design Guidelines

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GS-0109, Version 1.00iv © PLX Technology, Inc. 2011. All Rights Reserved.

GS-0109, Version 1.00© PLX Technology, Inc. 2011. All Rights Reserved. v

Preface

This document gives guidelines to get you started with designing the PCB for your product using the PLX Technology OXU3110 and OXU3111 devices.

In the text the devices are jointly referred to as OXU311x. Information applies to both devices, unless specifically stated otherwise.

Correct components and good PCB design are critical for the satisfactory operation of the OXU311x. The guidelines in this document assist you with good PCB design and help you avoid potential pitfalls.

This guide assumes that you have a working knowledge of PCB design. You must have access to the relevant reference schematics for the device; to obtain the latest version, contact your PLX Technology representative.

Typographic Conventions

In this document, the following conventions apply.

Convention Meaning

Italic Letters With Initial Capital Letters A cross-reference to another publication

Title A cross-reference to another section within the document

1, 2, 3 A numbered list where the order of list items is significant

A list where the order of items is not significant

Significant additional information

Courier Software code

Bold Significant names, for example of files or directories Text you type

Preface OXU311x PCB Design Guidelines

GS-0109, Version 1.00vi © PLX Technology, Inc. 2011. All Rights Reserved.

Revision Information

The following table lists the revisions of this document.

Version Date Modification

1.00 April 18 2011 No longer preliminary; document version number update only

0.20 March 01 2011 New document

GS-0109, Version 1.00© PLX Technology, Inc. 2011. All Rights Reserved. 1

Chapter 1

Component Selection

Serial Flash Selection

The following flash devices have been tested on the OXU311x:

EON EN25F05—64KB

EON EN25F10—128KB

EON EN25F20—256KB

Winbond W25X10A—128KB

Winbond W25X20A—256KB

The OXU3110 does not require a serial flash device, as it uses an internal application ROM. If you need to customize the firmware, the flash size must be a minimum of 64KB for the OXU3110. For the OXU3111 a flash device of 128KB is recommended. The actual size is determined by the size of the firmware, so may need to be larger depending on the features you implement. Flash devices that support 4KB sectors are recommended as an efficient size for storing configuration information while keeping sufficient space for the firmware image. Flash devices that support page programming are recommended, as this greatly reduces programming time.

Power Supply Selection

The OXU311x has no special power supply requirements.

You can use linear or switch mode power supplies.

When designing your power supply it is important to ensure that the power regulators have adequate heat dissipation, this is particularly important if linear regulators are used.

Component Selection OXU311x PCB Design Guidelines


GS-0109, Version 1.002 © PLX Technology, Inc. 2011. All Rights Reserved.


Chapter 2

Crystal Selection

This chapter gives guidelines for choosing the crystal and designing the circuit for it.

The crystal oscillator and the circuit surrounding it is a critical factor in the performance of OXU311x devices. So the choice of crystal and the circuit used are key decisions.

Crystal Circuit Design

Figure 1 shows the circuit that we recommend for OXU311x devices.

Figure 1 Crystal Circuit

The crystal operates in parallel resonant mode. The inverter, which is internal to the chip, acts as a class AB amplifier and provides 180-degree phase shift. The network formed by the crystal, C1 and C2 provides an additional 180-degree phase shift, resulting in a total phase shift of 360 degrees, which satisfies one of the conditions for oscillation. The other condition for proper startup and oscillation is that the closed loop gain should be ≥1.

For reliable crystal start-up for the oscillator, you must have an external feedback resistor (Rf).

25 MHz

Rf = 1 MΩ

X_CLKI X_CLKO

X1

C1 C2

where X is a 25-MHz crystal site

Rs = 330Ω

Crystal Selection OXU311x PCB Design Guidelines


Crystal Specification

The following table lists specifications of typical crystals to be used with OXU311x devices.

Overall frequency tolerance should be < 100ppm.

The oscillator circuit must have the following characteristics:

Feedback resistor Rf = 1MΩ

Series resistor Rs = 330Ω

Circuit board ≤ 12pF (= Cl)

If the ESR, shunt capacitance and load capacitance are too high, the loop gain of the circuit is reduced, potentially resulting in start-up problems.

Load Capacitance

The load capacitors, shown as C1 and C2 in Figure 1, combine with other circuit capacitance to form the load ‘seen’ by the crystal. The capacitance affects the frequency at which the crystal oscillates. The crystal manufacturer trims the crystal to oscillate at its nominal frequency for the specified load capacitance. Typically a variance of 1pF in the load capacitance adjusts the frequency of the oscillation by 10ppm.

The magnitude of the load capacitance significantly affects the power dissipated in the crystal. For this reason we recommend crystals with Cl ≤ 12pF.

Parameter Symbol Value

Nominal frequency Fo 25.000000MHz

Oscillation mode Fundamental

Frequency tolerance (@25C) ± 30ppm

Load capacitance Cl 12pF (max)

Shunt capacitance Cs 7pF (max)

Effective Series Resistance (ESR) Resr ≤ 50Ω

Maximum drive level 500μW (min)

Stability over temperature ± 50ppm

Operation temperature range -10° to +70°

Aging +/-5ppm/year

OXU311x PCB Design Guidelines Crystal Selection


The equation to calculate the values of C1 and C2 is:

Where:

Cxo is the device output capacitance, including package parasitics

Cxi is the device input capacitance, including package parasitics

CT is the intertrace capacitance between the crystal and device

Where C1 is made the same as C2, this simplifies to:

C1 = C2 = (CL – CS) x 2

Typically, Cxo = Cxi = 4pF; and CT = 1pF, therefore:

C1 = C2 = (12 – 3) × 2 = 18pF

We recommend that you use 5% C0G capacitors for C1 and C2.

As part of the board verification process, we recommend that you measure the frequency of oscillation using a frequency counter with an accuracy of 6 digits or better. If the frequency is too high, add more load capacitance; if too low, decrease the load capacitance.

Crystal Layout The layout of the crystal is important for ensuring the correct oscillator frequency, minimizing the noise introduced to the integrated circuit PLLs and minimizing emissions.

Consider the crystal and the load capacitors as a unit when laying out the board. Place them as close together as possible so that the loop area of the three components is a minimum. In addition, place the crystal components as close as possible to the XI and XO pins to minimize trace lengths. Try to do this without compromising decoupling and the placement and tracking of Rext.

CL = C1 x C2

+ CSC1 + C2

CS = Cxo x Cxi

+ CTCxo + Cxi

Crystal Selection OXU311x PCB Design Guidelines




Chapter 3

PCB Layout

You can achieve USB 3.0 and SATA electrical compliance with 2-layer and 4-layer boards.

2-layer board

The recommended 2-layer stack with impedence control is:

1 Components and differential pairs, with unused plane flooded with ground

2 Mainly ground, with cut-outs for power nets

For a 2-layer board, use a 0.8mm thick FR4 PCB. Any PCB thicker than 0.8mm leads to unacceptable distances between differential pairs and reference ground planes. Track the USB and SATA traces on the component side of the PCB running over the unbroken GND plane.

With a 2-layer design, it is very important to consider the following:

AC current return path of the internal PMU

Cross talk between the differential pairs of the USB and SATA traces

The component side must carry the 100Ω/90Ω differential pairs for the SATA and USB interfaces. Before laying out your board, to obtain this impedance, you must obtain board stack information from the board manufacturer. Trace widths and spacing must be adjusted to achieve this figure.

It is advisable to use wide traces to minimize the effects of etching tolerance; however, it is possible to obtain good results using standard board stacks with the OXU311x.

USB and SATA high-speed traces must never cross over broken power planes. It is recommended that you place these high-speed traces on the top layer with solid ground plane on the layer below.

Keep USB and SATA traces away from other traces, components and vias, and keep the pairs away from each other. Separate the differential pairs from other traces by 3 times the distance between the traces in the pair.

PCB Layout OXU311x PCB Design Guidelines


4-layer board

The recommended 4-layer board stack with impedance control is:

1 Component/Signal 1

2 Ground

3 Power

4 Solder/Signal 4

To achieve ideal high frequency decoupling, you must place the capacitors beneath the pins to be decoupled.

The Signal layer 1 must carry the 100Ω/90Ω differential pairs for the SATA and USB interfaces. Before laying out your board, to obtain this impedance, you must obtain board stack information from the board manufacturer. Trace widths and spacing must be adjusted to achieve this figure.

It is advisable to use wide traces to minimize the effects of etching tolerance; however, it is possible to obtain good results using standard board stacks with the OXU311x.

The power plane must be predominantly net VCC3V3, with smaller areas for VCC1V2 and VDDIO as necessary. Leave the Ground plane undisturbed.

USB and SATA high-speed traces must never cross over broken power planes. It is recommended that you place these high-speed traces on the top layer with solid ground plane on the layer below.

Keep USB and SATA traces away from other traces, components and vias, and keep the pairs away from each other. Separate the differential pairs from other traces by 3 times the distance between the traces in the pair.

Avoid vias in any of the clock or SFLASH traces; if vias must be used, it is important to consider the AC current return path.

Initial Placement

We recommend that you place and track components in the following order:

1 OXU311x

2 USB 3.0 components

3 SATA components

4 PMU components

5 Decoupling capacitors

6 Oscillator module

7 Serial flash

8 Main power regulators

9 GPIO/miscellaneous components

OXU311x PCB Design Guidelines PCB Layout


USB 3.0 interface

The USB 3.0 interface runs at 5Gbps: clean layout of these traces is crucial.

The USB 3.0 traces must track directly from the OXU311x to the USB 3.0 connector in a clean fashion. There are six nets running from the OXU311x to the USB 3.0 connector:

One USB 3.0 RXP/RXM differential pair

One USB 3.0 TXP/TXM differential pair

One USB 2.0 D+, D- pair

Route these pairs on the top layer with a differential impedance of 90Ω. Ensure that the positive and the negative pairs are very similar in length. The pin ordering of the device is arranged to allow these lengths to be identical. Keep the overall length of these traces as short as possible, typically <5cm.

When routing these traces, avoid 90o bends or tight angles. The OXU311x evaluation board implements curved traces, as shown in Figure 2. This may be unnecessary but demonstrates a layout with the minimum of reflections.

Figure 2 USB 3.0 Traces on the OXU311x Evaluation Board

When using a 4-layer board, in addition to the curved traces, you must use anti-pads to reduce impedance discontinuities of the USB 3.0 signal path. This may be unnecessary, but this layout implements best practices. To use anti-pads, place the ground plane directly under the AC coupling capacitor and USB IC pads. Note this is under the pads only, the capacitors must still have a strip of ground between the two pads. This layout is illustrated in Figure 3. Do not use anti-pads in a 2-layer board.



Figure 3 Ground Cut-outs

When using a 2-layer board, the distance between USB 3.0 traces and the reference GND plane is relatively large. To reduce the cross talk between the RX and TX pairs, use an isolating GND trace to separate the differential pairs, as illustrated in Figure 4. The isolating GND trace contains vias to the main GND plane.

Figure 4 Isolating GND Trace

SATA Interface The traces running from the OXU311x to the SATA connectors (through some 10nF capacitors) are SATA differential pairs. Route these on the top layer with a differential impedance of 100Ω. Ensure that the length of the traces in each pair is of very similar length. We recommend that you keep the overall length of these pairs as short as possible. These traces must be routed over unbroken ground plane with no tight bends or angles.

When the OXU311x and SATA connector are placed on the same side of the PCB, the differential pairs intuitively track directly from the device to the connector. If the connector is placed on the opposite side of the PCB then the traces may need to route in from the rear side of the connector. See Figure 5.

Ground the cut-outs under the AC coupling capacitors(4-layer board only)

Isolating trace(2-layer board)



Figure 5 Recommended SATA Tracking

Internal Switch Mode Supply

The 4.7uH inductor and 10uF capacitors associated with pins 44 and 45 are part of the internal switch mode regulator. Place these on the component side of the PCB as close to the OXU311x device as possible. The 10uF input and output capacitors must have a common separate ground that attaches to the main ground close to the regulator power pad of the OXU311x. The nets around these components and the VCC1V2 trace must be rated to at least 2A, preferably by creating a small power island on the component side of the PCB. Pin 47 is the voltage feedback pin for the integral switch mode supply and must track directly from this power island into the pin.

When using a 2-layer board, the AC return currents can have a detrimental effect on the performance of the OXU311x. To prevent this, you must use a common separate ground, as illustrated in Figure 6 on page 12.



Figure 6 Common Separate Ground

Decoupling Capacitors

Decoupling capacitors must be placed close to the OXU311x power pins, in line with normal decoupling requirements. As this package has no physical ground pins and only has a central ground power pad, all decoupling capacitors should be referenced to this power pad. Figure 7 shows the ideal placement for the decoupling capacitors.

Figure 7 Placement of Decoupling Capacitors

When placing decoupling capacitors, the aim is to minimize the inductance of the capacitor. This is generally achieved by minimizing the loop area associated with the capacitor, and can be achieved by careful design of the vias and tracks connected to it. In general, we recommend putting the vias that connect to the decoupling capacitors at the side of the capacitor, not at the end (shown as the ideal position in Figure 7). This is a recommendation that may have to be compromised, as you may have to use micro vias to fit vias between the power

Single GND path to OXU310x

4.7uH inductor

10uF input and output capacitors

Separate ground

Input decoupling capacitor

Ideal

Compromise



pad and pins. This may not be a preferred manufacturing process; in this case the placement of decoupling capacitors marked as the compromise in Figure 7 is sufficient.

The track connecting the via and the pad must be as short as possible, and the track width must be at least as wide as the via pad diameter. To minimize the inductance of the vias, avoid using thermal reliefs.

Figure 8 gives examples of placement ranging from unacceptable to optimal.

Figure 8 Good and Bad Via Placement for Decoupling Capacitors

For decoupling, use 100nF 0402 (X5R or X7R dielectric) capacitors, mounted on the solder side of the PCB.

Each power pin on the following rails must have its own dedicated decoupling capacitor:

VDD(VCC1V2)

SATA_VDD3V3

USB_VP

USB_VPTX

VDDIO (VCC3V3)

The VCC3V3 and VCC1V2 power rails must have a minimum of one larger 4.7uF bulk-decoupling capacitor, which must be placed close to the OXU311x.



Serial Flash Interface

The OXU3111 has an external serial flash interface that runs at up to 37.5MHz. Place series termination resistors close to the OXU3111 device for the following signals:

FLASH_SS_N

FLASH_SCLK

FLASH_MOSI

General Power Linear regulators are the ideal choice for generating the quietest and cheapest 3.3V supply. However, using a good quality switch mode power supply may be required in some USB 3.0 cable power solutions.

These supplies should be clean and isolated from any high speed signals. If you use a linear regulator, ensure that it has sufficient heat dissipation. Refer to the relevant OXU311x data sheet for current requirements.

The OXU311x has an exposed die pad: the vias used for the decoupling capacitors should provide adequate grounding and thermal transfer for this. We recommend that there is an even spread of more than 9 vias across the thermal pad.

It is important to ensure that your board manufacturer includes suitable holes in the solder resist and in the solder paste. To ensure manufacturability, the hole should not be solid, as this results in too much solder being put down. The following picture illustrates the approach used by PLX Technology.

The green square is the exposed die pad of the OXU311x, and the lighter filled areas are the holes in the paste screen.

Exposed die pad

Holes in paste screen



REXT and Crystal I/Os

Keep the trace from the USB and SATA REXT resistors as short as possible. We recommend that you put the relevant resistors on the solder side of the board and as close to the via associated with the pin as possible. Any noise picked up on these nets can affect the signal integrity of the associated SATA or USB port.

The oscillator pins, XTAL_O and XTAL_I, are sensitive to noise. Keep the tracking from the crystal and associated components away from all other signals. Noise picked up by these nets has a direct impact on the USB and SATA signal integrity.


Chapter 4

Reset Guidelines

To ensure that all initial conditions are met after power up, the OXU311x requires a reliable timed reset. If the device comes out of reset too early after power up, it may result in unreliable operation.

Hold the OXU311x in reset for at least 3ms once the 25MHz crystal has fully started up. The power supply must also be stable by this point. This 3ms ensures that all internal PLLs are fully stable, and that the logic is reset correctly.

A conservatively designed RC circuit should provide a reliable timed reset on power up. The OXU311x uses a Schmitt input on the reset pin, to assist with generating a reliable reset.

In practice, a crystal following the guidelines detailed in Chapter 2 Crystal Selection, should start up within 5ms, once stable power supplies are applied.

Generally, the greatest timing variance that needs to be accounted for is the start up of the supply voltage. This is completely dependent on the power supply components you use.

The reference schematics for the OXU311x shows an RC circuit with a time constant of 47ms. This is more than sufficient in most applications. However, we strongly recommend that you test the reset on any new design, with realistic power supplies and loads, before committing to production.

The following figure illustrates verification of the reset circuit operation. It shows the reset pin of an OXU311x reference design (the bottom trace), against the 25MHz crystal oscillator (the top trace). You must verify that the crystal has been oscillating for at least 3ms before the reset passes 1.52V (the minimum positive going threshold of the OXU311x).

The figure shows that the crystal has been oscillating for at least 20ms before reset is de-asserted.

Reset Guidelines OXU311x PCB Design Guidelines


OXU311x PCB Design Guidelines...Chapter 3 PCB Layout You can achieve USB 3.0 and SATA electrical...

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