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Overview of C4 Array Probing

Justin Leung

Intel Corporation

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OUTLINE

• C4 probing technologies• C4 probecards• Electrical and Mechanical Characterization• Process Integration challenges• Future requirements

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C4 Probing Technologies at Intel

Resilient ContactTechnology

Buckling BeamTechnology

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Buckling Beam Probes

Typical characteristics: • precision die drilling, manual assembly• 4-mil diameter, 225-mils length probes• Paliney-7 or BeCu probes • 1-mil alignment, 3-mils planarity, 2.5-3g/mil force, • probe replacement, head interchangeability

Upper Die

Lower Die

Mylar

MLC

Swage

MLC substrate

upper die

lower die

probes

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Resilient Contact Probes

Typical characteristics: • plated gold core springs with custom tip geometry• 5-mil tip diameter, 70-mil length probes• 13-um alignment, 13-um planarity, 1.2-3.0 g/mil

probe tips

springs anchored to MLC cover pad

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C4 ProbeCard Cross-section

PCB

MLC

interposer (BGA, PGA, etc..)

decoupling caps

decoupling caps

(PCB, space transformer, probes)

Performance Limiters:

pogos

probe length probe resistance

Cresprobe count

Packageelectrical design

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Electrical Characterization &Modeling

DC Electrical characterization:• Probe max current capability• Pwr/Gnd DC resistance

AC Electrical characterization:• TDR characterization

• Network analyzer measurements

• MDS and HFSS circuit modeling

• High speed current switch “Slammer” which switches

40 Amps in 5 ns to simulate DUT VCC turn-on transient.

• Measured performance matched model within 10%.

Power Integrity system design is the key challenge.

Requires accurate knowledge of product specs,power supply performance, component parasitics, etc..

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C4 probecard bandwidths in the range of 1.3-1.5 GHz.

Bandwidth limiters includepogo interface, interposer, and probes.

Supplier ASupplier BSupplier C

Pogo landsInterposerArea

Space TransformerStripline

Load Board Stripline

AC Characterization

0 ns 3.0 ns

Volta

ge

Time (ns)

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Mechanical Characterization

Experiments include:• Cres experiments• Lifetime robustness studies• PCB, chuck and probe deflection characterization• Array force measurements (single probe measurements inadequate)

S9k testhead emulatorand test system:

• Sort Process development

• Probecard mechanicalcharacterization.

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Cres ResultsDuring processdevelopment,

Cres serves as chiefsort process healthmonitor duringdevelopment.

Bin-switch criteriatakes over oncesilicon is available.

Monitor bothaverage and maximum Cres.

Lifetest studyAverage

0

1

2

3

4

5

0 10000 20000 30000 40000 50000 60000 70000 80000 90000 100000

Touchdowns

Ave

rage

Cre

s

Cres Data:Runs 1 to 6

0

1

2

3

4

5

0 1000 2000 3000 4000

Die No.

Cre

s VAVEVMAX

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Cres Optimization

Sort recipe #1 Sort Recipe #2

Average Cres vs. TDs

0.00E+00

1.00E+00

2.00E+00

3.00E+00

4.00E+00

5.00E+00

6.00E+00

7.00E+0078

291

410

4611

7913

1114

4415

7617

0818

4019

7321

0522

3723

6925

0126

3327

6528

9730

2931

6132

9334

25

Number of TDs

Avera

ge C

res (o

hm)

Series1

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Bump Impact

Bump alignment and impact marks generally not a problem.

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Process Integration Considerations• Prober

-- PTPA recognition -- PTPA robustness -- scrub plates -- chuck force / deflection

• Sort Process -- clean recipe optimization -- OT optimization -- bump interaction -- bump defects

• Probecard Repair -- offline PM procedures -- repair processes

• Metrology -- crash protection -- tip recognition -- supplier matching

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Burnt Probes

Burnt probes was keymanufacturing issue early on.

Addressed on several fronts:• bin limit triggers• testtape modifications• bump defect inspection• repair processes• etc...

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Dual Technology

Currently, both technologies in HVM despiteincompatible process recipes

Technology runoff resulted in high rates ofimprovement as competing teams leveraged sortprocess learnings.

Both technologies now in production on multiple sortfloors.

Supplier selection criteria:• Manufacturing performance• Manufacturing cost of ownership• Next Generation Capability• Supplier Health• Second Sourcing

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Future C4 probing requirementsTrends:

• Higher DUT currents (>100 A)• Lower Vcc (< 1 V)• Severe di/dt transients (>50 A/ns)• Power (>150 W)• High speed clocks, Rambus• Increasing Test Costs

Required Probecard Development:

• Higher probe counts• Lower Cres• Shorter probes• Robust probes• High performance chucks• Microwave design techniques• Parallel sort

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Colleagues in the SIU Engineering Groupinvolved in C4 Probing Technology Development:

Straty ArgyrakisCharlie BoettcherArthur FraserDean GonzalesAli JafariBarry Lieberman

ITTO, Virtual Factory, TD, and Supplier Partners.

Acknowledgements

Jeanette Roberts Arun Ramamoorthy Melissa ShellTim SwettlenRichard Yoshimoto