Outline Memory characteristics SRAM Content-addressable memory details DRAM © Derek Chiou & Mattan...

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Outline Memory characteristics SRAM Content-addressable memory details DRAM

© Derek Chiou & Mattan Erez

© Derek Chiou & Mattan Erez 3

What Memory Should I Use? Depends on access characteristics

How often is it written? How often is it accessed in general? How fast should the accesses be?

Latency? Bandwidth? What should the capacity be?

Bytes? Kilobytes? Megabytes? Gigabytes? Terbytes? How long should the data last?

Microseconds? Seconds? Years? Decades? Granularity of access Cost

Dollars, watts or joules, … Different memories optimized for different access types


Memory Types ROM (non-volatile Read Only Memory) RAM (volatile, Random Access Memory) “Disk” Non-mainstream

Really misnomers today RAM is often not truly random access ROM is writable, just more slowly than RAM


Random Access Memory (RAM) Static RAM (SRAM)

“Static” indicates that as long as you apply power, the value will be maintained

6 transistors/bit

Dynamic RAM (DRAM) What does dynamic mean? Capacitor stores data (1 cap + 1 transistor/bit)

Interfaces DDR – double data rate Burst mode – most DRAMs have a burst of at least 4 (now 8)

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SRAM



SRAM Cell (6T)

word line

=


SRAM Array

word line 0

word line 1

b0 b0 b1 b1 b2 b2 b3 b3

word line 2

word line 3


Accessing SRAM Can read/write (modulo bus turnaround) every cycle Generally 1 cycle latency (could be longer based on

pipelining) Large SRAMs are slower than smaller SRAMs

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DRAM


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DRAM Cell

What happens when you read?


DRAM Cell

What happens when you read?

Infineon 80nm


DRAM Refresh Capacitor holding value leaks, eventually you will lose

information (everything turns to 0)

How do you maintain the values in DRAM?


Simplified DRAM Internal Structure

Row

Column

RAS

CASAddr


Simplified DRAM Internal Structure

Row

Column

RAS

CAS

Addr

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DRAM Array


Accessing DRAM (RAS)

Operation Resource Utilization

Cycle

Activate Row

Request

Data

request

data

Simplified Bank State Diagram

act

pre wr

rd

Row

dec

oder

Sense amplifier

Column decoder

DRAM

Memory array

bank 0


Accessing DRAM (CAS)


Row

dec

oder

Sense amplifier

Column decoder

DRAM

Memory array

bank 0

request

data


act

pre wr

rd

Read Row

Request

Data

Cycle


Accessing DRAM (re-writing “lost” data)


Precharge Row

Request

Data

request

data


act

pre wr

rd

Row

dec

oder

Sense amplifier

Column decoder

DRAM

Memory array

bank 0

Cycle


DRAM RAS/CAS Summary Assert RAS to specify row address Assert CAS to specify column address Why separate RAS/CAS?

Can pulse CAS to read more from the same row Faster Implications?

Called Fast Page Mode

What to do while waiting for Act/Pre/…?


request

data

bank n-1bank 1

Row

dec

oder

Sense amplifier

Column decoder

DRAM

Memory array

bank 0


DRAM Hierarchy/Banks

Row

Column

RAS

CAS

Bank[1:0]

Why have banks?

Cannot access banks back-to-back. Why?


Memory Interfaces How much data per column command?

Interface width (x4, x8, …) How much data per bus transfer Note: each column DRAM address refers to width bits

Burst length (4, 8, …) How many bus transfers per CAS

SDRAM Synchronous DRAM – more when we discuss buses

DDRx Double-data rate – multiple data transfers per clock (rising and

falling edge, or even faster) DDR, then DDR2, then DDR3 – just different standards for

defining sizing, timing, and electrical parameters


Tradeoffs: SRAM vs DRAM

Criteria SRAM DRAM

Speed Low Latency High Bandwidth

Static Yes No

Access Easy Harder

Process Logic DRAM

Refresh No Yes

Density Low High


“Experimental” Memory Technology Not yet mainstream, but making headway Embedded DRAM

DRAM in logic process, integrated with the processor In between SRAM and DRAM in terms of properties

STT-RAM – Spin torque transfer RAM Based on Spintronics – manipulation of electron spins Works like 60’s “core memory”, but nano-sized “best of all worlds”, but still low density and experimental

PC-RAM – Phase-change RAM Based on heat-related changes to physical structure of cell FLASH replacement May replace DRAM


Memory Modules (DIMMs) Dual In-line Memory Module (DIMM)

Standard memory interface today Multiple chips on independent module

Easy to build and maintain systems DIMMs have one or more “ranks” Rank is multiple chips that share same CE


Memory Modules (DIMMs) Dual In-line Memory Module (DIMM)

Standard memory interface today Multiple chips on independent module

Easy to build and maintain systems DIMMs have one or more “ranks” Rank is multiple chips that share same CE

x8

8

x8

8

addr

MAR

CE CE WEWE

0

logic

x8

8

x8

8

CE CE WEWE

1

Width?Ranks?Chips/rank?

Outline Memory characteristics SRAM Content-addressable memory details DRAM © Derek Chiou & Mattan...

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