OptoelectromcBackplane Interconnect Technology Development ... · the plastic structure for...

Invited Paper

Optoelectromc Backplane Interconnect Technology Development- POINT

Y. S. Liu1, W.B. Hennessy1, R. Wojnarowski1, J. P. Bristow2, Yue Liu2 J. Rowlette3, J. Stack3,J. Y&d1ey, L. Eldada4, R.M. Osgood5, R. Scarmozzino5, S.H. Lee6, S. Patra6

1 GE Corporate Research & Development Center, Schenectady, NY 12301

2 Honeywell Technology Center, Minneapolis, MN 554183 AMP, Optical Interconnect Systems, Harrisburg, PA 171054 AlliedSignal Research & Technology Center, Morristowm, NJ 07960

5 Columbia University, Dept. of EE, New York, NY 10027

6 UCSD, Dept. of ECE, La Jolla, CA, 92093

ABSTRACT

This paper describes the technical approach and progresses of the POINT (Polymer Optical InterconnectTechnology) program. This project is a collaborative effort among GE, Honeywell, AMP, AlliedSignal,Columbia University and University of California at San Diego (UCSD), sponsored by DARPAIETO todevelop affordable optoelectronic packaging and interconnect technologies for board and backplaneapplications."2 this paper, we report the development of a backplane interconnect structure usingpolymer waveguides (Polyguide®) to an interconnect length of 280 mm to demonstrate high density (100urn channel spacing) and high speed (- 1 Gbps) interconnect, and the related technical developmentefforts on: (a) a high density and high speed VCSEL array packaging technology that employs planarfabrication and batch processing for low-cost manufacturing, (b) passive alignment techniques forreducing recurrent cost in optoelectronic assembly, (c) low-loss optical polymers for board and backplanelevel interconnects, and (d) CAD tools for modeling multimode guided wave systems and assistingoptoelectronic packaging mechanical design.

Key words: optical interconnect, optoelectronic packaging, high speed optical links, backplane andboard interconnect, VCSEL packaging, polymer waveguide, Polyguide®

1. INTRODUCTION

Since early development in 1970's, optical interconnects have successfully demonstrated all the keymerits of this technology in telecommunication, namely, wide bandwidth, low EMI, reduced cross-talk,low loss and reduced size and weight. In the meantime, the cost for deployment of the technology interms of data transferred rate per distance (bits per second per kilometer) has reduced significantly. Thecombined higher performance and reduced cost of this technology constitute the key ingredient for theexplosive growth of the telecommunication industry in the two decades that followed.

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Since 90's, the rapid advance in the processor speed and processing power, and the emerging super-computer technology using multiple processors have drastically increased the data transfer rates requiredbetween modules, board, backplane and cabinets. As a result, applications such as distributed computingsystems, interactive multimedia and high speed switching network communication systems now requiredata transfer rates exceeding Gbps. Meanwhile, the rapid development of high speed networkcommunication has significantly increased the data transfer bandwidth among local and wide areanetwork systems. These technological advancements impose a similar challenge to the deployment ofoptical interconnect for data communication.

To address these needs, the US government and industry have sponsored several major programs in thelast few years to develop optical interconnect technology for short haul data communication applications.Fig. 1 . 1 summarizes these activities and their respective targeted applications.39 As the technologymoves from local loops to the board and backplane levels, where the POINT program was focused on,optoelectronic materials, devices, packaging and processing have to be compatible to those technologiesalready used in the electronic board assembly. Successful insertion of this new technology has to leveragethe existing infrastructure in the electronic industry for material handling, device processes and fmalmodule assembly and packaging. In addition, the introduction of optical components, devices, andpackaging into electronic circuits has to be relatively transparent to electronic circuit designers. Handlingof discrete components in building optoelectronic modules and the sequential process of optical sub-systems assembly have to be replaced by batch processes in order to significantly reduce the overallassembling cost. These considerations dictate many the technical approaches selected for development inthe POINT program, and are addressed in the following sections.

Various Optoelectronic Interconnects and Packaging Technologies10

1

- Backplane - Workstation Cluster - Telecommunication

__ - MCM-to-MCM - High Speed Network - WAN

Chip-to.Chip - Super Computers - LAN

- 1 n çQ EJ POLO(io/i0)

POINT r-g 0 0OETC 32/32Jitney (20/20)

O OptoBus (1 0/10)0.1 • Cost-Sensitive

• Interconnect Density• Routing Flexibility• Interfaces and Connectors

Compatibility to ElectronicTechnologies (Packaging, Processes)

1 10 100 1000Transmission Distance (Meters)

YSLIGE A394.Oi

Fig. 1.1. Several major US government and industry sponsored programs in development ofoptical interconnect technologies for short haul data communication applications (OETC-ref. 5,OptoBus- ref.6, Jitney-ref. 7 and POLO-ref. 8.)

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2. HIGH DENSITY BACKPLANE INTERCONNECT

As the speed, performance and the number of the processors increase, the backplane interconnectbetween board-to-board and frame-to-frame will soon become an interconnect bottleneck.1° The presentstate-of-the-art in electrical backplane interconnects is 2 mm centerline spacing with eight rows and 60pins per row. This gives an effective board edge pitch of 100 pins per board edge inch. However, tominimize the peak noise voltage in high speed applications, the signal to ground ratio needs to be 1:1.This gives an effective density of 50 signal lines per board edge inch. Deployment of optical backplaneinterconnect can offers much higher interconnect density, and is demonstrated in our design goal ofproviding 250 signal lines per board edge inch. In addition, the cross-talk has been modeled and isestimated to be less than 35 dB . Another significant advantage of optical backplane interconnect is thelow insertion force, only the alignment pins contribute to the insertion force. Unlike, in the electricalbackplane, all pins contribute to the insertion force. As the pin density increases, the force per pinincreases till limited by the reliability of the mechanical structure.

A prototype backplane test structure was developed at AMP to demonstrate high density and high speedinterconnect that uses polymer waveguides. It has 144 channel multirnode waveguides with 50 urn coreson 100 urn pitches. On one end of the structure is terminated with MT-type interconnects to interfacewith Rx and Tx. There are 24 waveguides in each of the MT connector and 6 MT-connectors are used tointerconnect 144 waveguides. The other end of the structure is terminated into the high densityinterconnect. A backplane test structure is fabricated to go between the two backplane interconnects. Thereceiver side is similar to the transmitter side. The backplane optical link test structure is shown inFig.2.l.

Fig. 2.1. A high density backplane optical link test structure developed for backplaneinterconnect evaluation.

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3. OPTOELECTRONIC PACKAGING TECHNOLOGY

For board and backplane applications, the transmitter and receiver packaging have to provide a highinterconnect density, small packaging footprint, and low cost. To satisfy these requirements, we applieda thin-film embedded chip electronic module packaging technology developed at GE with demonstratedperformance and potentially low cost advantages to transmitter and receiver packaging. In this approach,the transmitter including a VCSEL array, driver chips, and passive components are placed on an Al203substrate (1"x 0.567".) The 50-ohm impedance matched electrical interconnect lines were fabricated onthe dielectric layers laminated over the die using the standard planar thin-film metallization processessuch as resist patterning, sputtering, electroplating and etching. Since the whole process used for thetransmitter module fabrication is batch operation, multiple modules of hundred units can be fabricatedsimultaneously in a single run with improved yields, as shown in Fig. 3. 1. In addition, we alsodemonstrated a plastic version of VCSEL array packaging. In this configuration, the VCSEL array isembedded inside a molded plastic enclosure with electrical interconnects fabricated on a laminatedpolymer dielectric layer. This kind of plastic packaging could leverage the flexible circuit technologyrapidly developed in the electronic packaging industry to further reduce the recurrent cost inoptoelectronic packaging. On the receiver end, a compact receiver was developed using the samepackaging structure and processes.

- make optoe!ectronics fully compatible with electronics

Fig. 3. 1. An optoelectronic packaging for VCSEL that leverages the planar fabrication and batchoperation developed in the CMOS technology to allow multiple transmitters fabricated in singleprocess run.

An optical link was developed for backplane evaluation and is shown in Fig. 3.2. The optical link consistsof a pair of transmitter and receiver interfaced to MT-type connectors through polymer waveguides(Polyguide®) mounted on a test board. The optical link was tested at Honeywell to 1Gbps. Ourdevelopment demonstrated, for the first time, an optoelectronic packaging technology for VCSELdevices that leverages the planar fabrication and batch processing already well developed in the ICindustry for low cost and large volume manufacturing.

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Fig. 3.2. The optical links for backplane evaluation consists of a transmitter, receiver, polymerwaveguides (Polyguide®), MT connectors, and ribbon fibers and a test result showing the eyediagram to 1 Gbps.

4. PASSIVE ALIGNMENT

In the POINT program, the thin film module packaging technology attaches the die to a planarinterconnecting layer, as shown in Fig. 4.1. This packaging approach provides high speed interconnectwithout wire bonds and a planar surface for polymer waveguide attachment to a VCSEL package andthus provides a continuous optical path without an air gap, and the VCSEL is enclosed inside a moldedplastic body.


Fig. 4. 1. The thin film module packaging technology developed in this program attaches the die toa planar interconnecting layer that eliminates the air gap between VCSEL and waveguideinterface.

A passive alignment process that uses a high precision excimer laser machining system for adaptivelyplacing alignment structures was developed at AMP and is shown in Fig. 4.2. In this passive alignmentprocess, an excimer laser micromachined precision kinematic passive alignment wells were fabricated inthe plastic structure for placement of precision micro-spheres with a diameter of 400 +1-0.12 microns.We have demonstrated the laser micro-machining process produces an accurate and reproducible processthat allows passive alignment of an array of polymer waveguides to a VCSEL array with an 1 micronaccuracy. Several other passive alignment techniques were also evaluated including adaptivelyplacement of pedestals using a pick-and-place machine and laser-trimmed polymer pedestals at GE,fabrication of the alignment pedestals using laser direct patterning of photosensitive polymers atAlliedSignal and fabrication of the alignment pedestals directly on the VCSEL device at Honeywell.

Fig. 4.2. A passive alignment process uses a high precision excimer laser machining system foradaptively placing alignment structures for the VCSEL alignment.

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5. CAD MODELING

Under this program, we have carried out a systematic analysis to model a multimode guided wave systemusing the software tool package BeamProp developed at Columbia University originally for single modesystems. As a result of this effort, a software tool designed specifically for modeling multimode guidedwave system was developed and is being released as an add on package to the BeamProp software. Inour development, the tool was extensively used to investigate the guided wave propagation under variousboundary conditions including tapered multimode waveguides, effects in index change in the multimodeguides on intensity fluctuation. It has also been used to calculate the optical losses introduced as functionsof various types of waveguide bends, shown in Fig. 5.1. A series of CADfiles for assisting multimodewaveguide designs has been developed to automatically generate a series of simulations and performstatistical analysis to calculate average transmission and the S/N of a statistical ensemble of devicemeasurements. The cross-talks for Polyguides of 30 urn core/100 urn pitch, and for 50 urn core/250 urnpitch were studied by modeling and experiments. Both showed about -27dB cross-talks between theadjacent channels. In addition, cross-talks of polymer waveguides under various fan-out geometries werealso modeled, and effects on cross-talk due to waveguide misalignrnents were investigated

Be€anFROP Simulation Results andExperimental Measurements of Multimode

Po1ynr Waveguides Bends

Fig. 5.1. Development of CAD tool for modeling multimode guided wave systems under variouscoupling geometry and the calculated losses are compared with the experimental data.

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To assist optoelectronic packaging design, we have also investigated at UCSD the stress distributionwithin the waveguide on a transmitter using 3D finite element thermal modeling software and analyzedthe impacts of various device thermal loading on the optical characteristics of the waveguides as functionof number of channels as shown in Fig. 5.2.

Fig. 5.2. A 3D thermal analysis of transmitter packaging under various thermal loadingconditions.

6. SUMMARY

In this paper, we described the POINT program in developing affordable optoelectronic packaging andinterconnect technologies for board- and backplanelevel optical interconnect applications. This is acollaborative effort among GE, Honeywell, AMP, AlliedSignal, Columbia University and UCSD,sponsored by DARPA/ETO. A prototype backplane test structure was developed to demonstrate highdensity and high speed interconnect using polymer waveguides. It has 144 channel multimode waveguideswith 50 um cores on 100 urn pitches. A thin fthn embedded chip optoelectronic packaging was developedfor VCSEL to provide high density, high speed and low cost packaging. This development demonstrated,for the first time, an optoelectronic packaging technology for VCSEL devices that employs the planar andbatch processes to fully leverage the processing technologies well developed in the CMOS technology forlow cost and large volume manufacturing. In addition, CAD tools are developed to model multimodeguided wave system and used to assist mechanical and thermal performance in optoelectronic packaging.

7. ACKNOWLEDGMENT

This work is supported by ARPA/ETO (Dr. Anis Husain), and the program is managed by WrightLaboratory, USAF, (Dr. James Grote) under the contract number F33615-94-C-1530.

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8. REFERENCES:

1 . Y.S.Liu, R.J. Wojnarowski, W.A. Hennessy, J.P. Bristow, Yue Liu, A. Peczalski, J.R. Rowlette, A.Plotts, J.D. Stack, J.T.Yardley, L. Eldada, R.M. Osgood, R. Scarmozzrnno, S.H. Lee, and V.H.Ozgus, "Polymer Optical Interconnect technology (POINT): optoelectronic packaging andinterconnect for board and backplane applications," in SPIE's "Critical Review of Optical Sciencesand Technology," ed. by Ray T. Chen, and Peter Guilfoyle, Vol. CR62, p. 405, 1996

2. Y.S.Liu, R.J. Wojnarowski, W.A. Hennessy, J.P. Bristow, Yue Liii, A. Peczalski, J.R. Rowlette, A.Plotts, J.D. Stack, J.T.Yardley, L. Eldada, R.M. Osgood, R. Scarmozzinno, S.H. Lee, and S. Patra,"Polymer Optical Interconnect technology (POINT)," Proc. IEEE's "Electronic Components andTechnology Conference," p. 308, 1996.

3. Y.S.Liu, H.S.Cole, J.P.Bristow and Yue Liu, "Polymer-based optical interconnect technology: aroute to low-cost optoelectronic packaging and interconnect," in Optical Interconnect III, ed. byR.Chen, SPIE, p. 80, 1995.

4. Y.S.Liu, H.S.Cole, J. Bristow and Yue Liu, "Hybrid integration of electrical and opticalinterconnects," in "Optical interconnect 11," ed. by R. Chen, Proc. SPIE, 1993. Also, J. Bristow, C.Sullivan, S. Mukherjee, Yue Liu and A. Husain, "Progress and status of guided wave opticalinterconnect technology," in "Optical interconnects,", ed. by R. Chen, Vol. 1849, Proc. SPIE, pp. 4-10, (1993)

5. Y.M. Wong et al, "Technology development of a high density 32-channel 16 Gbps optical data linkfor optical interconnect applications for the optoelectronic technology Consortium (OETC)," to bepublished in IEEE Journal of Lightwave Technology.

6. M. Lebby, et. a!., "Characteristics of VCSEL arrays for parallel optical interconnects," ECTC'96, p.279, 1996.

7. J. Crow, et. a!., "The Jitney parallel optical interconnect," ECTC'96 p.292, 1996.

8. K.H. Hahn, et. al., "Gigabytes/sec data communications with the POLO parallel optical link,"ECTC'96, p. 301, 1996.

9. S. Swirhun, et. al., "The P-VixelLink multichannel optical interconnect," ECTC'96, p. 316, 1996.

10. L. Meichior and J. R. Kropp, "A High Density optical backplane connector,", ECTC'96, pA.53,1996.

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