Operational Amplifiers: Theory and Design - Mead … · Operational Amplifiers, Theory and Design 2...

Operational Amplifiers: Theory and Design

TU Delft, the Netherlands, November 6-10, 2017

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© 2017 TU Delft

These lecture notes are solely for the use of the registered course Participants and Instructors teaching in the course.

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Operational Amplifiers, Theory and Design1

Lesson 1

A quick start

Burak GönenNovember 2016


Hands-on SessionsThere are totally 7 hands-on simulation sessions

Ø Lesson 1: Introduction, Macromodels and NoiseØ Lesson 2: Input stageØ Lesson 3: Output stageØ Lesson 4: Overall designØ Lesson 5: Two-stage configurationsØ Lesson 6: Three-stage configurationsØ Lesson 7: Fully differential amplifiers


Hands-on Sessions

In each lesson, you will complete several assignments, which are divided into three levels: A, B and C

Ø Assignments on Level A is for everyoneØ Assignments on Level B is for higher level participantsØ Assignments on Level C is for advanced participants

A manual with simulation instructions and these presentation slides are included in the folders.

Relax and keep yourself busy!

When you are stuck, please ask for help!


The Simulation Tool:Cadence Virtuoso 6.1.6


Libraries

The relevant Library for all the Hands-On Sessions is:

OPAMP

Most assignments have a top cell schematic, or a test bench, to test the circuit under test.

The relevant top cell and the circuits to be tested are shown for each assignment.

Library

CellsViews


Simulation ModelsThe models used in hands-on simulations are provided by NCSU Cadence Development Kit.

In case you need to manually place them, the transistor cells are:

NMOS = Library: NCSU_Analog_Parts, Cell: nmos4, View: symbol

PMOS = Library: NCSU_Analog_Parts, Cell: pmos4, View: symbol

Feature size is 0.3um

For more information: http://www.eda.ncsu.edu/wiki/NCSU_CDK


Adding Transistors

Edit properties of the transistor

1 -Press “I” to insert a new instance

2- Click “Browse” to see the Component Browser

3- Select the library, click “flatten” and select nmos4 or pmos4

4- Return back to “Add Instance” window to edit properties of the transistor

5- Make sure that the view is symbol

6- Your new transistor is ready!

2

3

4

5

6


Cadence Virtuoso: Beginners

We are assuming for all participants to have a basic knowledge of designing and simulating in Cadence environment.

For participants not familiar with the Cadence Virtuoso:

There is a short Cadence tutorial included in handout. It explains how to open and edit a schematic, how to simulate and how to choose important parameters for simulation.

You can also find detailed manuals on Cadence tools on your desktop.

The first lesson is an excellent way to get acquainted with the tools.


Boyle Macromodels


Boyle Macromodels

Input stage


Boyle Macromodels

1st gain-stage


Boyle Macromodels

2nd gain-stage


Boyle Macromodels

MillerCompensation


Boyle Macromodels

Output current limit


Boyle Macromodels

Output saturation


Boyle Macromodels

Common-modefeedback


Top Cell: 01_BoyleMacroModels

Assignment 1 Level A• Check DC biasing [ADE-L > Analyses > Choose > DC > Save DC Op.]• Run AC simulation to see the open-loop gain of the amplifier

Assignment 2 Level A• Add a capacitive load, and run the AC again

• Check: DC gain, unity gain-bandwidth (UGBW), and phase-margin

• Set the load capacitance as a variable and run parameter analysis together with AC simulations to see the open-loop gain and phase margin[ADE-L > Tools > Parametric Analysis > Add Variable (Cap Name) > From/To: 1p/1u > Total Steps: 10]

Assignments - I

Bode-Plots


DC gain

UGBW

Phase-margin


Top Cell: 02_Applications_DynamicRange

Assignment 4 Level A

• Here we have an inverting and an non-inverting amplifier.

• Please calculate the gain of the each amplifier

• Check the input common-mode voltages of the each amplifier

• What do you expect as output voltage?

Assignments - II




• Check DC biasing [ADE-L > Analyses > Choose > DC > Save DC Op.]• Do the output voltages of the each amplifier correct?• Can you comment on the virtual-ground voltages?

• Run AC simulation to see the closed gain of the amplifiers• Do the results match with your expectations?

Assignment – III




• Run transient simulation [1s] to see the step response of the amplifier in closed loop configuration

• Observe the output voltages• Observe the virtual-ground voltages

• Increase the input signal amplitude [V1=0 and V2=2.5V], and do the previous simulation again

• What difference you see compared to the previous case• Please define the output range• What is the maximum input range?• Can you comment about the dynamic-range?

Assignment - IV

Operational Amplifiers: Theory and Design - Mead … · Operational Amplifiers, Theory and Design 2...

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