OPEN-LOOP TEMPERATURE-COMPENSATED DIGITAL PREDISTORTION ... · digital predistortion scheme...

OPEN-LOOP TEMPERATURE-COMPENSATED DIGITAL

PREDISTORTION FOR POWER AMPLIFIERS

by

Rosanah Murugesu

A thesis submitted in conformity with the requirements for the degree of

Master of Applied Science

Graduate Department of Electrical and Computer Engineering

University of Toronto

© Copyright by Rosanah Murugesu 2015

ii

OPEN-LOOP TEMPERATURE-COMPENSATED DIGITAL PREDISTORTION

FOR DOCSIS 3.1 UPSTREAM POWER AMPLIFIER

Rosanah Murugesu

Master of Applied Science, 2015

Graduate Department of Electrical and Computer Engineering

University of Toronto

Abstract

Cable communication standards are migrating to multicarrier modulation schemes with wider

bandwidths and high-order constellations. However, stringent linearity specifications, aggressive

transmit bandwidth requirements and higher-order modulation schemes necessitate inefficient power

amplifier operation. The proposed digital predistortion scheme employs several strategies to save

power, thus enabling low-power operation of the amplifier without linearity degradation across a

bandwidth that is almost double the largest bandwidth encountered in predistortion literature. The

digital predistortion scheme accounts for temperature and board variations by virtue of temperature

compensation techniques and per-board coefficient calibration. The effectiveness of the proposed

digital predistortion scheme is demonstrated on a DOCSIS 3.1 upstream power amplifier supporting

simultaneous bandwidths of 200MHz. The proposed strategy overcomes novel challenges specific to

DOCSIS 3.1 upstream applications: digital passband input signals and spectral overlapping of

intermodulation and harmonic distortion products. The proposed technique reduces net power

consumption by 25% while suppressing distortion by 11.7dB in the best case and -0.4dB in the worst

case.

iii

Acknowledgements

I would like to thank my advisor Professor Glenn Gulak for his dedication, enthusiasm and remarkable

resourcefulness. I would like to acknowledge the members of my MASc committee: Prof. Antonio

Liscidini, Prof. Wai Tung Ng, Prof. Aleksandar Prodic and Prof. Glenn Gulak for their valuable time and

expert comments.

I would like to thank to Curtis Ling, Tim Gallagher and Madhukar Reddy at MaxLinear Inc for the

opportunity to realize the subject of this thesis. I would like to extend my gratitude to Sridhar Ramesh,

Ali Shahed, Pawandeep Taluja, Anand Anandakumar, Javad Samedi, Rahul Bhatia, Raja Pullela, Jorge

Grillo, Sheng Ye, SeungChul Hong, and Hossein Zareie for stimulating review meetings, engineering

guidance and an unparalleled commitment to the company. I cannot express how integral you have all

been to the materialization of this thesis.

I would like to thank Prof. Paul Chow for the donation of an FPGA board and Ruediger Willenberg for

guidance in Xilinx SDK and FPGA design.

I would like to thank Shahriar Shahramian and Timo Pfau for their wide range of expertise and their

readiness to share it. You were both a source of guidance and a source of inspiration.

I would like to thank my friends Dineshan Poopalaratnam and Michal Fulmyk for keeping my spirits high

and my sugar consumption low during the trying times of graduate school. I appreciate the support of

everyone in BA5000.

I would like to acknowledge my friends Anith Selvakumar and Janahan Ramanan for all of the fun times

we’ve had – 8 years worth of Tim Horton’s XL English Breakfast tea. We have grown up together; I drink

coffee now. The laughs and adventures we’ve shared will be cherished, and probably recounted for

years to come.

iv

I would like to thank my friends Nivethika Sivabalan, Nitharsana Sivabalan, Nishanthy Selvarajah and

Mariyam Nauffer for their support. Your presence has kept me sane.

Finally, I would like to thank my family for their unrelenting belief in me. In particular, I would like to

thank my parents, Bavani Murugesu and Murugesu Sithamparappillai, for their unwavering commitment

to ensuring I achieve my goals. You are my greatest strength.

v

Contents

List of Figures ...................................................................................................................................... viii

List of Tables .......................................................................................................................................... xi

List of Symbols ..................................................................................................................................... xii

List of Acronyms ................................................................................................................................. xiv

1 Introduction .................................................................................................................................... 1

1.1 Motivation ..................................................................................................................................... 1 1.2 Objectives ...................................................................................................................................... 2 1.3 Thesis Outline ................................................................................................................................ 3

2 Power Amplifier Predistortion Overview ............................................................................ 4

2.1 Introduction ................................................................................................................................... 4 2.2 Nonlinearities in Power Amplifiers ................................................................................................ 4

2.2.1 Nonlinearity Constraints and Metrics ................................................................................... 4 2.2.2 AM-AM, AM-PM Effects ........................................................................................................ 6 2.2.3 Memory Effects ..................................................................................................................... 9

2.3 Predistortion Models ................................................................................................................... 12 2.3.1 Introduction ........................................................................................................................ 12 2.3.2 Memory-less Polynomial..................................................................................................... 14 2.3.3 Volterra Series ..................................................................................................................... 14 2.3.4 Memory Polynomial ............................................................................................................ 14 2.3.5 Hammerstein Model/Weiner Model .................................................................................. 15 2.3.6 Artificial Neural Networks ................................................................................................... 17

2.4 Predistortion Architectures ......................................................................................................... 18 2.4.1 Learning Schemes ............................................................................................................... 18 2.4.2 Coefficient Estimation Algorithms ...................................................................................... 19 2.4.3 Adaptive Digital Pre-distortion ........................................................................................... 20 2.4.4 Static Digital Predistortion .................................................................................................. 22

2.5 Real-world PA Example: The DOCSIS 3.1 Specification .............................................................. 23 2.5.1 Introduction ........................................................................................................................ 23 2.5.2 Frequency Allocation .......................................................................................................... 24

vi

2.5.3 Modulation Requirements .................................................................................................. 24 2.5.4 Emission Specifications ....................................................................................................... 25

2.6 Challenges of Predistortion for DOCSIS 3.1 ................................................................................. 25 2.6.1 High PAPR of OFDM Modulation Scheme ........................................................................... 26 2.6.2 Large Bandwidth ................................................................................................................. 26 2.6.3 Digital Pass-Band Input Signals ........................................................................................... 27 2.6.4 Correcting HD and IMD ....................................................................................................... 27 2.6.5 Stability ............................................................................................................................... 28 2.6.6 Large Memory Order........................................................................................................... 29

3 Simulation Model ........................................................................................................................ 31

3.1 Introduction ................................................................................................................................. 31 3.2 Power Amplifier Frequency Response ......................................................................................... 31 3.3 AM-AM Effects ............................................................................................................................ 32 3.4 AM-PM Effects ............................................................................................................................ 33 3.5 Post-Distortion Test Procedure ................................................................................................... 34

3.5.1 DPD Training........................................................................................................................ 35 3.5.2 Post-Distortion Testing ....................................................................................................... 35

3.6 DPD Model Selection ................................................................................................................... 36 3.7 Post-distortion Simulation Results across Temperature and Process ......................................... 38

3.7.1 Post-distortion Training Signal Selection ............................................................................ 38 3.7.2 Post-Distortion Results with Temperature and Process Variations .................................... 39

3.8 Summary ..................................................................................................................................... 42

4 Pre-distortion Test Bed Implementation ........................................................................... 44

4.1 Introduction ................................................................................................................................. 44 4.2 Requirements and Specifications ................................................................................................ 44 4.3 A/D Converter ............................................................................................................................. 45 4.4 D/A Converter ............................................................................................................................. 47 4.5 Clock Considerations ................................................................................................................... 49

4.5.1 Clock Jitter ........................................................................................................................... 50 4.5.2 Clock Drift ............................................................................................................................ 50

4.6 FPGA Implementation Details ..................................................................................................... 52 4.6.1 AD9739A DAC Evaluation Board ......................................................................................... 52 4.6.2 Serial Peripheral Interface Module ..................................................................................... 53 4.6.3 DAC Interface Module ......................................................................................................... 53 4.6.4 Video Direct Memory Access Module ................................................................................. 53

4.7 Summary ..................................................................................................................................... 53

5 A High-performance PA Case Study: Measured Results ................................................ 54

5.1 Introduction ................................................................................................................................. 54 5.2 Power Amplifier Characterization ............................................................................................... 55

5.2.1 Fundamental Frequency Response ..................................................................................... 55 5.2.2 Harmonics ........................................................................................................................... 55 5.2.3 P1dB and Psat .......................................................................................................................... 56

vii

5.3 AM-AM and AM-PM Effects ........................................................................................................ 57 5.3.1 AM-AM, AM-PM and MER for 100MHz Bandwidth and 69dBmV Power ........................... 57 5.3.2 AM-AM, AM-PM and MER for 195MHz Bandwidth and 65dBmV Output Power .............. 59

5.4 DPD Model Selection ................................................................................................................... 59 5.4.1 DPD Model Constraint and Considerations ........................................................................ 60 5.4.2 Impact of Severe Linear Memory Effect ............................................................................. 61 5.4.3 Modified DPD Training Scheme .......................................................................................... 62 5.4.4 Designing Equalization Filter ............................................................................................... 63 5.4.5 Results with Proposed DPD Training Scheme ..................................................................... 64

5.5 Measured Predistortion Results .................................................................................................. 66 5.5.1 Test Procedure .................................................................................................................... 66 5.5.2 Predistortion Results for 100MHz Bandwidth 69dBmV Test Set ........................................ 68 5.5.3 Predistortion Results for 195MHz Bandwidth 65dBmV Test Set ........................................ 74

5.6 Power and Area Estimates .......................................................................................................... 78 5.6.1 Power and Area Estimates for 100MHz Bandwidth 69dBmV Case .................................... 79 5.6.2 Power and Area Estimates for 195MHz Bandwidth 65dBmV Case .................................... 79

5.7 Summary ..................................................................................................................................... 80

6 Conclusion ..................................................................................................................................... 81

6.1 Summary of Contributions .......................................................................................................... 81 6.2 Future Directions ......................................................................................................................... 83

Appendix A: Matlab ............................................................................................................................ 84

A.1 Matlab Code for Solving and Applying Equalization Filter ............................................................... 84 A.2 Matlab Code for Solving and Applying DPD Coefficients .................................................................. 85 A.3 Matlab Code for Capturing ADC Samples ......................................................................................... 87 A.4 Matlab Code for Downloading Waveforms to DAC .......................................................................... 89

Appendix B: Measurement Results ............................................................................................... 90

B.1 Results with Temperature Variations for 100MHz 69dBmV ............................................................. 90 B.2 Results with Process Variations for 100MHz 69dBmV ...................................................................... 92 B.3 Results with Temperature Variations for 195MHz 65dBmV ............................................................. 95

Appendix C: Test Bed Board Modifications ................................................................................ 97

C.1 Modifications to AD9739A DAC Evaluation Board ............................................................................ 97 C.2 Modifications to AD9625 ADC Evaluation Board .............................................................................. 98

Appendix D: Data Sheets and Product Briefs ............................................................................ 99

References .......................................................................................................................................... 104

viii

List of Figures

Figure 2.1: Summary of MER, ACLR, In-Band and Out-Of-Band Distortions ................................................. 5

Figure 2.2: P1db and Psat for typical class AB biased PA .................................................................................. 6

Figure 2.3: AM-AM curve for class AB PA ..................................................................................................... 7

Figure 2.4: AM-PM curve for class AB PA [3] ................................................................................................ 7

Figure 2.5: AM-AM plot for class AB biased PA with memory effect [3] ...................................................... 9

Figure 2.6: Phase of IM3 Lower Sideband as a Function of Tone Difference [10] ...................................... 11

Figure 2.7: General Memory Model of a PA ............................................................................................... 12

Figure 2.8: Cascade of DPD and PA [11] ..................................................................................................... 13

Figure 2.9: Original PA Response and PA Response with Linearization [11] .............................................. 13

Figure 2.10: Block Diagram of Memory Polynomial ................................................................................... 15

Figure 2.11: Block diagram of Hammerstein Model ................................................................................... 16

Figure 2.12: Block Diagram of Weiner Model ............................................................................................. 16

Figure 2.13: ANN DPD model with Two Hidden Layers .............................................................................. 17

Figure 2.14: Direct Learning Scheme .......................................................................................................... 18

Figure 2.15: Indirect Learning Scheme ....................................................................................................... 18

Figure 2.16: Temperature Compensated DPD Scheme Proposed by Hammi and Ghannouchi [33] .......... 23

Figure 2.17: RF Modules in Upstream Transmit Chain of DOCSIS 3.1 Cable Modem ................................. 24

Figure 2.18: Training with Equalized Output Signal Proposed by Braithwaite [45] .................................... 26

Figure 2.19: Example of DOCSIS 3.1 Case Exhibiting Transmit signal, IMD and HD Spectral Overlap. ....... 28

Figure 3.1: Simulated PA Gain and Phase at 10dB backoff from required output RMS level .................... 32

Figure 3.2: PSD of Simulated PA Output Under Typical Operating Conditions (80°C and TT process) with DOCSIS 3.1 Mask ......................................................................................................................................... 32

Figure 3.3: AM-AM Behaviour of Simulated PA with Wideband (195MHz Bandwidth, 102.5MHz Center Frequency) OFDM Signal ............................................................................................................................. 33

Figure 3.4: AM-PM Behaviour of Simulated PA with Wideband (195MHz Bandwidth, 102.5MHz Center Frequency) OFDM Signal ............................................................................................................................. 33

Figure 3.5: Simulation Post-Distortion Test Set Up .................................................................................... 34

ix

Figure 3.6: Power Spectral Density of PA Output, Post-Distortion and Residual Error when Modelling with Memoryless 5th Order Polynomial Model ........................................................................................... 36

Figure 3.7: Power Spectral Density of PA Output, Post-Distortion and Residual Error when Modelling with Memory Polynomial Model with 4 Taps for First, Third, Fifth and Seventh Order Nonlinearities (Condition=1.3e11) ..................................................................................................................................... 36

Figure 3.8: Power Spectral Density of PA Output, Post-Distortion and Residual Error when Modelling with Orthogonal Memory Polynomial Model with 4 Taps for First, Third, Fifth and Seventh Order Nonlinearities and R=4 (Condition=131) ..................................................................................................... 38

Figure 3.9: Worst In-Band Distortion and Worst Out-of-Band Distortion for 25MHz OFDM Signal at 20MHz Center Frequency Across Temperature and Process ..................................................................... 40

Figure 3.10: Worst In-Band Distortion and Worst Out-of-Band Distortion for 25MHz OFDM Signal at 100MHz Center Frequency Across Temperature and Process ................................................................... 40

Figure 3.11: Worst In-Band Distortion and Worst Out-of-Band Distortion for 25MHz OFDM Signal at 188MHz Center Frequency Across Temperature and Process ................................................................... 41

Figure 3.12: Worst In Band Distortion and Worst Out of Band Distortion for 195MHz OFDM Signal at 102.5MHz Center Frequency Across Temperature and Process ................................................................ 42

Figure 4.1: AD9625-2.5EBZ ADC evaluation board and HSC-ADC-EVALEZ FIFO board ............................... 45

Figure 4.2: Measured SFDR of AD9625 at 10MHz, 90MHz and 200MHz ................................................... 46

Figure 4.3: Measured IM3 for AD9625 ADC with Varying Tone Spacing Vs. Center Frequency ................. 47

Figure 4.4: AD9739A-FMC-EBZ DAC evaluation board and ML605 FPGA ................................................... 48

Figure 4.5: Measured SFDR of AD9739A DAC Evaluation Board vs. Frequency ......................................... 49

Figure 4.6: Measured IM3 of AD9739A DAC Evaluation Board vs. Frequency ............................................ 49

Figure 4.7: Time Domain Effects of Relative Frequency Drift Between ADC and DAC ............................... 51

Figure 4.8: DPD Test Bed with ADC and DAC Locked to the Same Clock .................................................... 51

Figure 4.9: FPGA System Architecture ........................................................................................................ 52

Figure 5.1: Measured IM2 vs. Center Frequency of MxL235 at Bias 0 with Varying Tone Spacing and at 69dBmV output RMS .................................................................................................................................. 56

Figure 5.2: Measured IM3 vs. Center Frequency of MxL235 at Bias 0 with Varying Tone Spacing and at 69dBmV output RMS .................................................................................................................................. 56

Figure 5.3: P1dB and Psat relative to P1dB and Psat at 5MHz of MxL235 at Bias 0 Vs. Frequency ................... 57

Figure 5.4: Output Constellation of MxL235 with 100MHz Bandwidth, 55MHz Center Frequency OFDM Signal at 69dBmV output RMS .................................................................................................................... 58

Figure 5.5: Output Constellation of MxL235 with 195MHz Bandwidth, 102.5MHz Center Frequency OFDM Signal at 65dBmV output RMS ......................................................................................................... 59

Figure 5.6: DPD Test Bed Set Up ................................................................................................................. 60

Figure 5.7: Power Spectral Density of PA Output, Post-Distortion and Residual Error when Modelling with Orthogonal Memory Polynomial with N1=1, N2=2, N3=3, N5=1 and R=5 (MSE = 22.7dB) .................. 62

x

Figure 5.8: Power Spectral Density of PA Output, Post-Distortion and Residual Error when Modelling with Orthogonal Memory Polynomial with N1=42, N2=2, N3=3, N5=1 and R= 5 (MSE = 44.5dB) ............... 62

Figure 5.9: Proposed PA Model .................................................................................................................. 63

Figure 5.10: Proposed DPD Training Scheme ............................................................................................. 63

Figure 5.11: Frequency Response of the Equalizing Filter for MxL235 at 19dB backoff from Psat ............. 64

Figure 5.12: Frequency Response of PA and Equalizing Filter for MxL235 at 19dB backoff from Psat ........ 64

Figure 5.13: Power Spectral Density of PA Output, and Residual Error when Modelling with Orthogonal Memory Polynomial with N1=(1,5,10,20), N2=2, N3=3, N5=1, and R= 5 (MSE = 44.1dB, 46dB, 48dB and 49dB) and Training with Proposed Equalization Training Scheme ............................................................. 64

Figure 5.14: Output Constellation of MxL235 with 100MHz Bandwidth, 55MHz Center Frequency OFDM Signal at 69dBmV output RMS after Equalization (MER=-43.1dB) ............................................................. 66

Figure 5.15: Training Phase of DPD Test Procedure ................................................................................... 67

Figure 5.16: Test Phase of DPD Test Procedure .......................................................................................... 67

Figure 5.17: Output Constellation of MxL235 with 100MHz Bandwidth, 55MHz Center Frequency OFDM Signal with DPD at 69dBmV output RMS after Equalization (MER=-45.3dB) ............................................. 69

Figure 5.18: Worst In-Band and Worst Out-Of-Band Distortion for 24MHz OFDM Signal at 93MHz Fc Across Temperature with MxL235 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test Set #1 ....................................................................................................................... 71

Figure 5.19: Worst In-Band, Worst Out-Of-Band and Notch ACLR for 48MHz OFDM Signal at Fc=29MHz and 81MHz Across Temperature with MxL235 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test Set #1................................................................................................ 71

Figure 5.20: Worst In-Band and Worst Out-Of-Band Distortion for 100MHz OFDM Signal at 55MHz Fc Across Temperature with MxL235-2 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test Set #1 (Training with Original MxL235) ................................................................... 73

Figure 5.21: Worst In-Band and Worst Out-Of-Band Distortion for 24MHz OFDM Signal at 17MHz Fc Across Temperature with MxL235 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test Set #2 ....................................................................................................................... 77

Figure 5.22: Worst In-Band and Worst Out-Of-Band Distortion for 195MHz OFDM Signal at 102.5MHz Fc Across Temperature with MxL235 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test Set #2 ....................................................................................................................... 77

Figure 5.23: Implementation of Orthogonal Memory Polynomial DPD Model .......................................... 78

xi

List of Tables

Table 1.1: Increase in Number of Broadband Cable Subscribers in 2013 for Top Eight Cable Internet Providers ....................................................................................................................................................... 1

Table 5.1: Measured Results for MxL235 PA at Bias 2, Bias 0 and Bias 0 with Predistortion at Room Temperature ............................................................................................................................................... 68

Table 5.2: MxL235 Junction Temperature at Bias 2 and Bias 0 for 5 Ambient Temperature Points .......... 69

Table 5.3: Summary of Suppression Achieved Across Temperature with MxL235 at Bias 0 with the Temperature Compensated Predistortion Scheme for Test Set #1 ............................................................ 70

Table 5.4: Measured Results for MxL235-2 PA at Bias 2, Bias 0 and Bias 0 with Predistortion Trained with MxL235 and MxL235-2 at Room Temperature ........................................................................................... 72

Table 5.5: Measured Results for MxL235 PA at Bias 2, Bias 0 and Bias 0 with Predistortion at Room Temperature ............................................................................................................................................... 74

Table 5.6: Summary of Suppression Achieved Across Temperature with MxL235 at Bias 0 with the Temperature Compensated Predistortion Scheme for Test Set #1 ............................................................ 75

Table 5.7: Power and Area Cost of Common Arithmetic Logic Units in 28nm ........................................... 78

Table 5.8: Power and Area Cost Estimates of DPD model for Test Set#1 in 28nm .................................... 79

Table 5.9: Power and Area Cost Estimates of DPD model for Test Set#2 in 28nm .................................... 79

Table 5.10: Summary of MxL235 Power Consumption, Efficiency and Linearity Performance at Bias 2, Bias 0 and Bias 0 with DPD .......................................................................................................................... 80

xii

List of Symbols

Clock Parameters:

SNRjitter SNR degradation due to clock jitter

tjitter Root Mean Squared clock jitter

Digital Predistortion:

γp Pth order basis function

( ) Vector of basis functions applied to sample n

Vector of updates to predistortion coefficients

Vector of errors when using indirect learning

µΔ Convergence constant

Vector of predistortion coefficients

Vector of predistortion coefficients from the i-1 iteration

Coefficient of the term with order p and delay m

Fc Test Signal Center Frequency

fin Test tone frequency

Jresidual Sum of the squared residuals

M Memory order

Np Half the taps for the Pth order nonlinearity in memory polynomial

P Nonlinearity Order

( ( )) P order orthogonal polynomial applied to x(n)

( ( )) P order orthogonal polynomial applied to y(n-(-R·N1))

R Order of sparse delay taps

X(n) Input passband sample

Xb(n) Input baseband symbol

xiii

XDPD(n) Predistorter output sample

Vector of predistorter output samples

Xmax Outermost constellation point

Y(n) Output passband sample

Yb(n) Output baseband symbol

Input estimation matrix for Least Squares

Field Effect Transistor:

Λ Output impedance constant

µn Electron mobility

Cox Gate capacitance per unit area

Cj Junction capacitance

ic Capacitive current

id Transistor drain current

L Transistor gate length

Vds Transistor drain to source voltage

Vgs Transistor gate to source voltage

Vth Transistor threshold voltage

W Transistor gate width

Power Amplifier:

Η PA efficiency

G0 Nominal Gain

G(x(n)) Gain modulation of PA

Ibias Average current consumed by PA

IM3 Third-Order Intermodulation

P1dB Power Amplifier output power at 1dB compression point

Pout Output Power

Psat Output power at the power amplifier’s saturation point

xiv

List of Acronyms

ACLR Adjacent Channel Leakage Ratio

ADC Analog to Digital Converter

ALU Arithmetic Logic Unit

ANN Artificial Neural Network

API Application Programming Interface

BW Bandwidth

BPSK Binary Phase Shift Keying

CATV Cable TV

CDMA Code Division Multiple Access

CM Cable Modem

CMTS Cable Modem Termination System

DAC Digital to Analog Converter

DDR Double Data Rate

DOCSIS Data Over Cable Service Interface Specification

DPD Digital Predistortion

ENOB Effective Number of Bits

EVM Error Vector Magnitude

FET Field Effect Transistor

FF Fast Process

FFT Fast Fourier Transform

FIR Finite Impulse Response

FMC FPGA Mezzanine Card

FPGA Field-Programmable Gate Array

HD Harmonic distortion

HPC High Pin Count

xv

IDFT Inverse Discrete Fourier Transform

IMD Intermodulation distortion

LMS Least Mean Square

LS Least Squares

LTE Long Term Evolution

LTI Linear Time Invariant

LUT Look Up Table

LVDS Low Voltage Differential Signalling

MER Modulation Error Ratio

MSE Mean Square Error

NMSE Normalized Mean Square Error

NSD Noise Spectral Density

OFDM Orthogonal Frequency-Division Multiplexing

PA Power Amplifier

PAPR Peak to Average Power Ratio

PSD Power Spectral Density

QAM Quadrature Amplitude Modulation

RF Radio Frequency

RLS Recursive Least Square

RMS Root Mean Square

SFDR Spurious Free Dynamic Range

SINAD Signal to Noise and Distortion

SNR Signal to Noise Ratio

SPI Serial Peripheral Interface

SS Slow Process

TT Typical Process

VCO Voltage Controlled Oscillator

VDMA Video Direct Memory Access

Introduction

1

1 Introduction

1.1 Motivation

In recent years, broadband service providers have seen rapid growth in subscribers as shown in Table

1.1. In fact, Forbes predicts broadband coverage to penetrate 74% of US households in the next four

years [1]. With an ever-increasing number of subscribers and industry trends towards higher data rates,

cable communication standards are migrating to multicarrier modulation schemes with multi-channel

aggregation and high-order constellations, resulting in transmit signals with wider bandwidths and high

peak to average power ratios [2]. However, aggressive transmit bandwidth requirements and higher-

order modulation schemes compounded by stringent linearity specifications make the design of a power

efficient power amplifier particularly difficult.

Table 1.1: Increase in Number of Broadband Cable Subscribers in 2013 for Top Eight Cable Internet Providers

Broadband Internet – Cable

Companies Subscribers at End of 2013 Net Adds in 2013

Comcast 20,662,000 1,296,000

Time Warner 11,606,000 211,000

Charter 4,640,000 371,000

Cablevision 2,780,000 17,000

Suddenlink 1,059,500 57,400

MediaCom 965,000 50,000

WoW (WideOpenWest) 740,000 31,000

CableONE 472,631 13,396

Other 6,385,000 115,000

Total 49,310,131 2,161796

The largest motivation to reduce power consumption and improve power amplifier efficiency is simply

to reduce cost. Reducing power consumption and power dissipation in the power amplifier reduces

extreme temperature conditions for other components on board thus simplifying thermal design efforts

Introduction

2

for these components. Furthermore, reducing power dissipation reduces heat mitigation costs in the

form of heat sinks. However, reducing power consumption while simultaneously meeting output

transmit power and linearity requirements using traditional analog design techniques is near impossible.

Traditionally, power amplifier design is a trade-off between linearity and efficiency. Operating the power

amplifier at a lower bias reduces power consumption and increases efficiency but reduces the dynamic

range, subjecting signals to more severe nonlinearities. Digital predistortion (DPD) enables more

efficient operation by compensating for these nonlinearities. However, digital predistortion consumes

power and that power is correlated with the amount of hardware required to implement the digital

predistortion system. Thus the trade-off now becomes one of power amplifier efficiency versus digital

predistortion complexity.

This thesis presents a digital predistortion scheme for power amplifiers designed for the latest cable

broadband DOCSIS standard: Data Over Cable Service Interface Specification (DOCSIS) 3.1. The proposed

scheme supports bandwidths up to 195MHz, almost double the bandwidth encountered in modern DPD

literature. Furthermore, unlike previous studies, predistortion is performed on the digital passband

signal as opposed to digital baseband or analog passband signal. Finally, the proposed digital

predistortion scheme corrects both intermodulation and harmonic distortion to DOCSIS 3.1 specification

while reducing total power consumption of the transmit chain.

1.2 Objectives

The main objective of this thesis is to reduce power consumption in the DOCSIS 3.1 upstream transmit

chain by developing a power-conservative digital predistortion solution for a DOCSIS 3.1 upstream

power amplifier. A successful solution should introduce minimal area and power overhead without

detracting from the original bandwidth, transmit power or linearity performance of the power amplifier.

The objectives of this thesis are to develop a digital predistortion scheme that:

1) Enables more efficient operation of the power amplifier by reducing power consumption,

2) Improves performance of the more efficient power amplifier to meet DOCSIS 3.1 applications as

measured by MER, in-band and out-of-band distortion levels,

Introduction

3

3) Demonstrates tolerance to predicted signal, temperature and process variations in the upstream

transmit chain.

The performance improvement and reduced power consumption of the digital predistortion strategy is

demonstrated with a commercially available DOCSIS 3.1 compliant upstream power amplifier with

simultaneous bandwidths of 195MHz.

1.3 Thesis Outline

The thesis is organized into six chapters. Chapter 1 provides a motivation for the topic, states thesis

objectives and presents the thesis outline. Chapter 2 describes sources of power amplifier nonlinearities

and common digital linearization approaches to mitigate them, subdivided into common linearization

models, architectures and training schemes. An overview of DOCSIS 3.1 specifications is introduced

along with the challenges they present. Chapter 3 reveals insights gained from a simulation model of the

DOCSIS 3.1 upstream power amplifier. Simulation results of the proposed digital predistortion model are

presented. Chapter 4 details the FPGA implementation of a predistortion test bed including measured

performance results of the test bed. Chapter 5 presents measured predistortion results using a recently

released DOCSIS 3.1 upstream power amplifier. Chapter 6 concludes the thesis with a summary of

contributions and future directions. Appendix A provides Matlab code describing predistortion model

training. Appendix B contains additional measured predistortion results from the high-performance

power amplifier case study. Appendix C outlines board-level modifications made to evaluation boards in

the predistortion test bed implementation. Appendix D provides data sheet summaries and product

briefs relevant to predistortion test bed implementation.

Power Amplifier Predistortion Overview

4

2 Power Amplifier Predistortion Overview

2.1 Introduction

Power Amplifiers (PAs) are critical components of the upstream and downstream transmit chain,

connecting individual subscribers to service providers. They are intrinsically nonlinear large signal

devices with a limited range of linear operation well below the maximum achievable output power, or

saturation level. Limiting operation to within the linear range poses efficiency concerns, particularly for

input signals with a large peak-to-average power ratio. Operating the power amplifier near saturation

improves efficiency but subjects input signals to more severe nonlinearities. Fortunately, PAs may

operate with higher efficiency if their nonlinear behaviour is compensated using digital predistortion

(DPD) techniques. This chapter provides an overview on sources of power amplifier nonlinearities in

section 2.2 and common digital linearization approaches to mitigate them in sections 2.3 and 2.4. An

overview of DOCSIS 3.1 specifications is introduced along with the linearity challenges they present in

sections 2.5 and 2.6, respectively.

2.2 Nonlinearities in Power Amplifiers

2.2.1 Nonlinearity Constraints and Metrics

In a transmit chain, digital data sequences are converted to analog signals and amplified using a PA.

Most communication standards require transmitted signals to be confined to an allocated bandwidth,

which is referred to as a channel. However, the interaction between the transmitted signal and the PA

sometimes generates distortion emissions wider than the allocated channel. Typically, strict emission

specifications dictate the maximum distortion emission at each frequency channel, called a spectral

mask. To meet the spectral mask, transmit chains employ a filter at the PA output to limit transmission

bandwidth. The passband of these filters tend to span multiple channels and though they may filter out

distortions that lie out-of-band, distortions that fall within adjacent channels or its own channel remain.


5

Figure 2.1: Summary of MER, ACLR, In-Band and Out-Of-Band Distortions

Figure 2.1 illustrates out-of-band distortion, in-band distortion, adjacent channel power and modulation

errors as viewed in power spectral density plots. Out-of-band distortion specifications outline the

permissible power spectra outside of the upstream or downstream transmission band, usually given in

absolute power levels. In-band distortion refers to distortion spectra inside of the transmission band and

outside of the signal band. The specification outlining the amount of distortion emission admitted into

an adjacent channel, called the Adjacent Channel Leakage Ratio (ACLR), is absorbed into the broader

group of in-band distortion specifications. Constraints for distortions within the signal band typically

come in the form of Modulation Error Ratio (MER) or Error Vector Magnitude (EVM) specifications [3].

MER is the root mean square (RMS) power in the error between received symbols in baseband (Yb(n))

and ideal symbols (Xb(n)) normalized by the RMS power of the ideal symbols, given in units of dB:

[∑

| ( ) ( )|

| ( )|

] (2.1)

Similar to MER, EVM is the RMS power of the error normalized by the outermost symbol power:

*

∑ | ( ) ( )|

| | + (2.2)

Pow

er/F

req

uen

cy

Frequency

Transmit Bandwidth

Use

r 1

Sig

nal

Ban

dwid

thM

ER

Use

r 2

Sig

nal

B

andw

idth

AC

LR

In-B

and

Dis

tort

ion

Ou

t-o

f-B

and

Dis

tort

ion


6

In-band distortion and MER may be improved in one of two ways: linearization techniques or inefficient

operation of the PA at large backoffs from saturation.

The efficiency of the PA (η), which is defined as the ratio of PA output power (Pout) to power consumed

by the PA, increases with Pout. However, at higher Pout levels, the PA experiences gain compression and

behaves more nonlinearly. The resulting distortion manifests itself as spectral regrowth, both harmonic

(HD) and intermodulation (IMD) distortion products. HDs are polynomial functions of the carrier

frequency and IMDs are modulation terms that result from mixing between two or more carrier

frequencies. Multicarrier modulation schemes, such as OFDM, are particularly difficult to amplify

efficiently due to its large number of subcarriers leading to signals with large bandwidth and high Peak

to Average Power Ratio (PAPR). Traditionally, to linearly amplify a signal with a high PAPR (e.g. 13dB),

the PA must be backed off from its compression region by the PAPR amount.

2.2.2 AM-AM, AM-PM Effects

Figure 2.2: P1db and Psat for typical class AB biased PA

Figure 2.2 depicts the power transfer function for a class AB biased PA. The Pout at which nominal gain

(G0) compresses by 1dB is defined to be P1dB. As Pout increases beyond P1dB, gain continues to compress

until the PA reaches its saturation point (Psat) at which the gain is zero. Thus, PAs are compressive and

linearization techniques must be expansive. However, DPD cannot increase the power capability of the

PA and, as a result, becomes ineffective as the saturation point is reached [4]. Hence, in the context of

DPD, Psat is defined to be P3dB due to power limitations in compensating a signal compressed by more

than 3dB [5].

Pou

t (d

Bm

)

Pin (dBm)

1dBP1dB


7

It can be noted from Figure 2.2 that the PA output (y(n)) can be modelled as a function of the

input magnitude:

( ) (| ( )|) ( ) (2.3)

Where x(n) is the PA input and the gain (G) is a function of input magnitude. This gain function G(|x(n)|)

is referred to as the AM-AM curve because amplitude modulation in the input signal produces

amplitude modulation in the PA gain. A sample AM-AM curve for a class AB biased power amplifier is

demonstrated in Figure 2.3. Sources of AM-AM effects include clipping on supply rails and active devices

operating beyond their linear region [4].

Figure 2.3: AM-AM curve for class AB PA

Figure 2.4: AM-PM curve for class AB PA [3]

The drain-current gate-voltage relationship of a transistor is nonlinear and can be expressed as:

(

) ( )

( ( ))

(2.4)

Where id is the drain current, µn is electron mobility, Cox is the gate capacitance per unit area, W is

transistor gate width, L is transistor gate length, Vgs is gate to source voltage, Vth is the threshold voltage

of the transistor, Vds is the drain to source voltage and λ is the output impedance constant. Additional

non-idealities such as mobility degradation contribute further to the nonlinear nature of transistor

transconductance [4]. As a result, the transconductance of a transistor can be approximated by its

Taylor series expansion about the ideal value. Assuming PA gain to simply be transconductance

multiplied by a constant output resistance, the Taylor series expansion of the PA output can be

expressed as:

G(|

x(n

)|)·

|x(

n)|

|X(n)|

Arg

{G(|

x(n

)|)}

|X(n)|


8

( ) ∑ ( )

( ) (∑ ( )

) ( ) ( ( )) (2.5)

Where y(n) is PA output, x(n) is PA input and ap is the pth coefficient in the Taylor series expansion.

Therefore, PA gain and consequently AM-AM may be modelled using a polynomial.

PAs also exhibit unwanted nonlinear phase modulation effects where the output phase depends on the

input signal magnitude, called AM-PM effects [3, 4]. The AM-PM curve is measured by down converting

the input and output passband signal to baseband, time aligning the two waveforms and then plotting

the phase of the complex gain as a function of the input magnitude [3]. So, given the transfer function of

the PA at baseband:

( ) (| ( )|) ( ) (2.6)

Where the subscript b denotes baseband, the AM-PM curve is the phase of Gb(|xb(t)|). A sample AM-PM

curve for a class AB biased PA is illustrated in Figure 2.4.

AM-PM effects are often attributed to nonlinear capacitances and resistances [6]. Nonlinear junction

capacitances (Cj) are functions of the applied voltage and can be approximated by a Taylor series

expansion:

( ) ( ) (2.7)

Where ci are coefficients of the Taylor series expansion and y(t) is the output voltage. The current

through a capacitance (ic) follows:

( ) ( )

(2.8)

( ) (∑ ( )

) ( )

(2.9)

In discrete time, dy(t)/dt is approximated with delay or advance terms, such as y(n)-y(n-1). Using the

memoryless polynomial model for AM-AM effect, ( ) ∑ ( )

, the current through the


9

junction capacitance can be modelled as a function of the input voltage. In summary, modelling AM-PM

effects in passband require cross terms such as x(n)·x(n-1) or x(n)·x(n-2).

2.2.3 Memory Effects

2.2.3.1 Introduction

PA nonlinearities can either be classified as memoryless or memory-based. The AM-AM and AM-PM

curves presented thus far have been memoryless; the output gain and phase have been strictly a

function of the current input. Memory effects in PAs give rise to nonlinearities that depend on past input

values. In AM-AM and AM-PM plots, memory manifests itself as dispersion about the memoryless

curves. A sample AM-AM plot for a class AB biased PA with memory effect is demonstrated in Figure 2.5.

Figure 2.5: AM-AM plot for class AB biased PA with memory effect [3]

Memory effects are classified as electro-thermal memory effects or electrical memory effects [7].

Electro-thermal memory effects are the result of thermal capacitances and resistances forming thermal

filters [8]. Electrical memory effects are mainly attributed to a non-constant PA frequency response,

biasing networks and matching networks [9, 10]. Both of these types of memories affect modulation

frequencies up to several MegaHertz. As a result, PA models incorporating memory effects are effective

in PA applications involving wideband signals [11].

2.2.3.2 Electro-Thermal Memory Effects

Electro-thermal memory effects that arise from self-heating affect low modulation frequencies up to a

few MegaHertz [10]. The input signal envelope modulates the instantaneous junction temperature of

the PA, which in turn modulates PA nonlinearities. The varying thermal capacitances and resistances of


10

the PA form a distributed low pass filter with a wide range of time constants. However, the thermal filter

time constant is larger than the inverse of the signal bandwidth. As a result, temperature fluctuations

trail envelope changes and signals are subjected to nonlinearities spawned by past inputs.

2.2.3.3 Electrical Memory Effects

Electrical memory effects can be further categorized into linear and nonlinear memory effects. Linear

memory effects are derived from a non-constant fundamental frequency response whereas nonlinear

memory effects are related to impedance matching at harmonics and envelope frequencies [7]. Linear

memory effects in PAs simply translate to frequency dependent behaviour during linear operation of the

PA. For example, a linear PA with constant gain and phase for all input signal magnitudes may still have

memory due to non-constant gain and phase over its frequency range. A flat frequency response

corresponds to the Dirac delta function in the time domain, requiring a single tap to model. A varying

frequency response requires several filter taps, or larger memory order, to model accurately. A constant

frequency response is less attainable for wider bandwidths, hence wideband multicarrier modulations,

such as OFDM, are conducive to memory effects.

On the other hand, nonlinear memory effects are related to envelope frequencies and harmonic

frequencies, which have much larger frequency ranges than the fundamental. For example, the

envelope frequency range stretches from DC to the maximum modulation frequency [10]. As a

consequence of larger frequency ranges, higher-order nonlinearities experience larger impedance

variations, giving rise to large memory orders for nonlinearities. In some PA architectures, matching

networks are designed to attenuate harmonic responses, prompting huge impedance variations and

creating a significant source of nonlinear memory [10]. Similarly, envelope frequencies may fall close to

baseband where the bias circuit impedance matching conditions determines the frequency response [7].

Biasing networks inherently have large time constants in order to adequately filter power supply and

biasing noise sources. However, in the presence of intermittent large signals, the biasing condition may

shift and modulate the output signal at a phase angle that may be very different from the phase angle of

the input signal [4].

2.2.3.4 Tests for Memory Effects

Traditionally, two-tone tests with varying tone spacing are used to test for memory effects in a PA. A

two-tone signal applied to an ideal memoryless PA will generate intermodulation products (IM3) that are


11

independent of center frequency and tone spacing. In practice, PAs with memory rarely behave this

way. Figure 2.6 presents the lower sideband IM3 phase as a function of two-tone frequency spacing as

observed by Vuolevi et al [10]. Memory effects account for IM3 amplitude and phase deviations from

ideal memoryless values illustrated by the dashed line in Figure 2.6. At smaller tone differences, thermal

memory effects regulate intermodulation products [10]. At larger tone differences, electrical memory

effects dominate intermodulation products [10].

Figure 2.6: Phase of IM3 Lower Sideband as a Function of Tone Difference [10]

PAs also exhibit asymmetries in upper and lower IMD sidebands when tested with two-tone or

multitone signals. Studies cite electrical and electro-thermal memory effects as causes of IMD

asymmetry, and as a consequence, IMD asymmetry is a hallmark of PA memory. Carvalho and Pedro

[12] demonstrate the relationship between IMD asymmetry and terminating impedances at envelope

and baseband (bias circuitry) frequencies. Vuolevi et al [10] suggest that IMD asymmetry stems from

thermal filters having opposite phase at the positive and negative envelope frequencies, contributing to

one side and subtracting from the other side. Regardless of the cause, IMD asymmetry and IMD

dependence on tone spacing limit the amount of correction achievable with a memoryless DPD model.

2.2.3.5 Modelling Memory Effects

When memory effects are evident in a PA, memoryless PA models no longer suffice. PA memory adds

frequency dependent behaviour to PA distortion and increases the number of coefficients needed to

model the PA. Frequency dependent distortion is usually modelled as a linear time invariant (LTI) filter

preceding or following a memoryless nonlinear block. The number of LTI filter taps and the order of the

memoryless nonlinearity set the memory and nonlinearity orders of the model, respectively. A general

model of a PA with memory would include an LTI filter before and after a memoryless nonlinearity and

an LTI filter placed in feedback around the memoryless nonlinearity [3]. This configuration is illustrated


12

in Figure 2.7. Simpler memory models use only one LTI filter but their modelling capabilities are limited

to PAs with weak nonlinearities and small memory effects [3]. It should also be noted that nonlinear

blocks and LTI blocks are not commutative.

Figure 2.7: General Memory Model of a PA

2.3 Predistortion Models

2.3.1 Introduction

The objective of digital predistortion is to accurately model the PA inverse so that the cascaded

response of DPD and PA is linear. The basic idea is illustrated in the Figure 2.8 and the ideal power

transfer curve with DPD is demonstrated in Figure 2.9. DPD can perform channel equalization as well as

distortion compensation, correcting both linear and nonlinear PA behaviour, whereas an equalizer

corrects only the linear behaviour. Also, unlike DPD, some linearization strategies, such as particle

filtering, sit on the receiver end [13]. It should be noted that DPD linearization does not change the Psat

of the PA; it simply gives it a harder saturation characteristic.

General PA Model with Memory

LTI

LTI

Memoryless Nonlinearity

LTI


13

Figure 2.8: Cascade of DPD and PA [11]

Figure 2.9: Original PA Response and PA Response with Linearization [11]

Hence the objective of digital predistortion is now reduced to the challenge of determining the most

accurate inverse PA model, referred to as a predistortion model. Generally, the model chosen for the PA

can be used for the predistortion function as well [3]. The predistortion block can be implemented with

a look up table (LUT) or with basis waveforms. In the case of memory, the LUT would be multi-

dimensional and basis waveforms would have delay or advance terms. The pursuit of more accurate

predistortion models encourages the use of more basis waveforms. However, additional basis

waveforms require more hardware and hence would be more costly. Also, over specifying the DPD

model would cause the coefficient estimation to become ill conditioned, degrading predistortion

performance [14, 15]. This is discussed in detail in Section 2.6.

DPD using basis waveforms creates the desired predistorted signal (XDPD) from nonlinear transformations

of the input signal ( * ( )+):

∑ * ( )+

(2.10)

where Ƴp{k} are the nonlinear basis waveforms, P is the number of nonlinear basis waveforms and ap are

the DPD coefficients. These nonlinear basis waveforms can be divided into two general categories:

memoryless models, such as the memoryless polynomial, and models with memory effect, such as

Volterra series, memory polynomial, Hammerstein model/ Weiner model and neural networks [3].

These models are discussed in the following sections.

PADPD

XDPD(n)X(n) Y(t)

DACXDPD(t)

BA

Psat

Ideal linear

response

Response after

linearization

PA response

Input Power (dBm)

Ou

tpu

t P

ow

er

(dB

m)


14

2.3.2 Memory-less Polynomial

Given that a PA is memoryless, the input-output relation of the PA inverse may be modelled with a

memoryless polynomial:

( ) ∑ ( )

(2.11)

Where xDPD and x represent the predistorter output and input and ap are real coefficients. In this case,

the nonlinear basis function is a polynomial: Ƴp{k}=kp. The memoryless polynomial model is used in DPD

for low bandwidth, nonlinear signals [3]. In the case of a differential pair PA, only odd-order nonlinear

terms are included in the DPD model. Some studies claim that using second-order terms improve ACLR

performance [16]. When the memoryless polynomial model proves insufficient, the nonlinear basis set

must be expanded to include memory terms.

2.3.3 Volterra Series

The Volterra series expansion is the most comprehensive scheme that can describe any general

nonlinearity with memory [17]:

( ) ∑ ∑ ( ) ∏ ( )

(2.12)

The functions ap(τ1,...,τp) are pth order Volterra kernels. The drawback of the Volterra series is that the

large number of basis waveforms created limits practical implementation. The number of basis

waveforms, or model order, grows exponentially with nonlinearity order P [3]. These waveforms are also

highly correlated and in some cases duplicates of each other. Due to this huge disadvantage, pruning

techniques are applied to reduce the number of basis waveforms in practical applications [18, 19].

2.3.4 Memory Polynomial

A popular pruning method is to keep only the diagonal terms of the Volterra kernels, thus forming the

memory polynomial model:


15

( ) ∑ ∑ ( )

(2.13)

The basis waveforms in this case can be considered to be Ƴp{k}=(k-m)p . A memory polynomial

predistortion model may be implemented as P parallel branches which sum together, each with a

memoryless nonlinearity followed by an LTI Finite Impulse Response (FIR) filter. The structure is

presented in Figure 2.10. Each FIR filter can have a different number of filter taps with different

coefficients hence forming different frequency responses. The model order of the memory polynomial

basis set is P·(∑ ( ) ), which is significantly less than the model order of the Volterra series.

Figure 2.10: Block Diagram of Memory Polynomial

2.3.5 Hammerstein Model/Weiner Model

The Hammerstein model and the Weiner model are both examples of cascaded DPD structures

characterized by two blocks in series. In the Hammerstein model, the LTI filter follows the memoryless

nonlinearity whereas in the Weiner model the LTI precedes the memoryless nonlinearity. The block

diagram of the Hammerstein and Weiner model is given in Figure 2.11 and 2.12.

LTI1

LTI3

LTI2

X(n)

(.)2

(.)3

XDPD(n)

.

.

.


16

Figure 2.11: Block diagram of Hammerstein Model

Figure 2.12: Block Diagram of Weiner Model

The Hammerstein model differs from the memory polynomial because the same FIR filter is applied to

each nonlinearity [3]. In fact, the Hammerstein model can be considered a subset of the memory

polynomial. The input-output relationship of the Hammerstein model looks similar to the memory

polynomial except with a few key differences:

( ) ∑ ∑ ( ) ( )

(2.14)

Unlike the memory polynomial, the basis waveforms for the Hammerstein model are hard to define. In

the memory polynomial, each basis waveform has an associated coefficient. The Hammerstein model

has two sets of coefficients, one for the memoryless nonlinearity block and one for the LTI filter.

Decomposition of the cascaded response into two separate coefficient sets is non-trivial.

Similarly, the Weiner model has two sets of coefficients that need to be estimated independently:

( ) ∑

( ∑ ( ) ( )

)

(2.15)

Unlike the Hammerstein model, the Weiner model includes cross terms (e.g., x(n)·x(n-1) or x(n)·x(n-2)).

Hence, the Weiner model is not a subset of the memory polynomial but rather a subset of the general

Volterra series. Also, a Hammerstein model for the DPD model assumes that the PA can be best

described by a Weiner model and vice versa.

LTIMemoryless Nonlinearity

X(n) XDPD(n)LTI

Memoryless Nonlinearity

X(n) XDPD(n)


17

2.3.6 Artificial Neural Networks

Figure 2.13: ANN DPD model with Two Hidden Layers

More recently, artificial neural networks (ANN) have been used in DPD models to correct PA

nonlinearities and memory effects [20] [21]. Typically, ANNs have an input layer, one or more hidden

layers and an output layer. Figure 2.13 shows a sample ANN structure with two hidden layers; one for

linear behaviour (L) and one for nonlinear behaviour (NL) [20]. ANNs learn input-output mappings

through optimization using a training signal. Back propagation algorithms are commonly used to

approximate the nonlinear input-output relation to any degree of accuracy [20] [21]. However, ANNs

suffer from slow convergence speed and limited linearization performance [22].


18

2.4 Predistortion Architectures

In addition to a DPD model, a complete DPD system includes a learning scheme, coefficient estimation

algorithm and training scheme [3]. There are two types of learning schemes, direct and indirect learning,

which differ in DPD topology: the former uses original input signal as a reference and the latter uses the

predistorted signal as a reference [23]. Coefficient estimation algorithms, such as Least Mean Square

(LMS) or Recursive Least Square (RLS), direct how DPD coefficients are obtained [3]. The training scheme

defines when and how often DPD coefficients are updated. Some DPD architectures are adaptive,

iteratively adjusting coefficients during PA operation [3]. Alternatively, some DPD architectures rely on

offline coefficient estimation or factory calibration, called static or open-loop DPD systems [3]. These

various architectural facets are discussed below.

2.4.1 Learning Schemes

For DPD coefficient estimation there must be observation points in the main transmit path. The two

main DPD learning schemes, direct and indirect learning, differ in where the estimation branch connects

to the transmit branch [23]. Block diagrams of the direct learning scheme and the indirect learning

scheme are shown in Figures 2.14 and 2.15.

Figure 2.14: Direct Learning Scheme

Figure 2.15: Indirect Learning Scheme

In direct learning schemes, the coefficient estimator compares the PA feedback output to the original

input and adjusts DPD coefficients to minimize the error between them. A drawback of direct learning is

that the estimation loop includes the effect of the DPD block. Since the DPD block is inside the

coefficient estimation loop, coefficient estimation must be iterative, hence this scheme is best suited for

adaptive real-time DPD systems [23-25]. Hardware costs include an on-board observation loop with a

power hungry Analog to Digital Converter (ADC). A benefit of direct learning is that as the DPD

coefficients converge, the bandwidth of the PA feedback output approaches the bandwidth of the

LS

X(n) XDPD(n)PADPD DAC

ADC

Y(n)LS

X(n) XDPD(n)PADPD DAC

ADC

Y(n)


19

original signal input. As a result, the estimation process is more robust to subsampling of the PA

feedback output [3].

In indirect learning schemes, the coefficient estimator derives the PA inverse by comparing the

predistorted signal to the PA feedback output and adjusts the DPD coefficients to minimize the error

between them [23, 25]. The estimated PA inverse is called the post-distortion function and indirect

learning assumes that the post-distortion function is the ideal predistortion function [25]. A drawback of

this approach is that the signals used for estimation, xDPD(n) and y(n), have a much wider bandwidth

than the original input signal [3]. A benefit of indirect learning is that the coefficient estimation may be

done offline. Since the DPD block is outside of the estimation loop, the post-distortion function and the

DPD coefficients may be estimated from PA input-output measurements using Least Squares (LS) [23]. If

the DPD coefficients can linearize the PA sufficiently for all operating conditions, no iterative estimation

is needed and no additional feedback hardware is needed. Hence, the indirect learning scheme can be

used in both real-time adaptive systems and open-loop offline estimation systems.

2.4.2 Coefficient Estimation Algorithms

RLS, LMS or combinations of both are all derived from the more general Least Squares (LS) estimation.

LS is a standard approach in data fitting to approximate coefficients that minimize the sum of the

squared residuals (Jresidual). Residuals are the difference between the observed value and the

corresponding fitted value. For example, if the indirect learning architecture were used with LS and the

DPD model is comprised of P basis functions , LS will try to minimize:

∑| ( ) ∑ { ( )

}

|

(2.16)

We want a solution of the form:

(2.17)

Where , ( ) ( )-, [ ], 0 ( ) ( ) 1 and


20

( ) 0 . ( )

/ .

( )

/1

.

The LS estimate of the coefficients is:

( )

(2.18)

The estimation improves with a larger number of samples N. One critical issue with LS is stability, which

is dependent on the condition number of the estimation matrix [23]. The instability and condition

number increases with increasing complexity of the DPD model, e.g. higher-order polynomials or larger

memory order. Fortunately, some techniques exist to reduce the matrix condition number and increase

the stability of the DPD system. For example, orthogonalization techniques may be used to modify the

into an estimation matrix with a lower condition number [14, 15, 23]. Additional details on

orthogonalization techniques are discussed in section 2.6.5.

LMS and RLS are iterative estimation techniques that approximate LS. They both use gradient descent to

converge to a minimum but they differ in complexity and convergence behaviour. RLS converges faster

but is more unstable and requires more hardware to implement [26]. Some studies combine LMS and

RLS to reach a compromise between speed and stability [26].

2.4.3 Adaptive Digital Pre-distortion

Due to the limited number of DPD coefficients, adequate linearization results are obtained over a

narrow range of operating conditions. As the operating condition changes, e.g. temperature, the

nonlinear behaviour of the PA may change and the residual nonlinearities may grow. One method of

overcoming varying operating conditions is to make the DPD adaptive [3]. As the PA is transmitting, the

estimation loop iteratively estimates residual nonlinearities using adaptive algorithms such as LMS or

RLS.

Both indirect and direct learning schemes can be made adaptive. For example, the LS coefficient

estimation procedure presented in section 2.4.2 for indirect learning can be made iterative:


21

(2.19)

(2.20)

where = [ ( ) ( )], =[a1 ... aP] is the coefficient vector from the i-1 iteration,

0 ( ) ( ) 1 and ( ) 0 . ( )

/ .

( )

/1 .

The LMS estimate of the coefficient errors is:

( )

(2.21)

The DPD coefficients are updated every iteration:

(2.22)

In summary, adaptive DPD architectures can track slow changes in PA behaviour due to changes in

operating conditions. The primary drawback of adaptive systems is that the coefficient estimator block

and observation path are now necessary components in the transmitter. Hardware components in the

observation path, such as mixers and an ADC, add cost to the transmitter and consume power. On the

bright side, the DPD system is more robust to changes in operating conditions so it’s more stable as well.

This trade-off is acceptable in some base station applications where the hardware cost and power

consumption of the observation path is small compared to the PA [27-29].


22

2.4.4 Static Digital Predistortion

Static digital predistortion is a classic linearization method. This architecture uses offline measurements

to build a static LUT or DPD model. Though this architecture has significantly less power overhead than

adaptive systems, it is rarely used in practical applications since it cannot tolerate variations in

temperature and PA aging [3].

Several studies have made modifications to adaptive systems to reduce the power consumption of the

observation path. Waheed and Ba [30] propose a periodic online calibration scheme for cellular

handsets. Their approach facilitates tracking of PA behaviour variations. Deviations from expected

behaviour trigger a calibration of DPD coefficient while the PA is transmitting [30]. Other studies have

proposed schemes with periodic offline calibration: iteratively optimize DPD coefficients or LUT using

predefined test signals when the PA is not transmitting [31, 32]. In these cases, the power consumption

is reduced but the hardware implementation costs associated with the observation path remain. Some

studies have proposed schemes with offline calibration using Matlab, foregoing a fixed observation path

in the transmitter [18, 24]. However, these studies have not addressed temporal variations in PA

behaviour due to temperature or aging.

A compromise between DPD robustness and observation path implementation costs is proposed by

Hammi and Ghannouchi [33]. They suggest an open loop static architecture suitable for temperature

drift compensation in memoryless PAs. The DPD structure is two part; a memoryless LUT and a

temperature dependent adjustment function. First, the LUT is populated using offline PA measurements

at room temperature. Then, the LUT is characterized offline across temperature to devise an

adjustment function. The adjustment function takes temperature and LUT index as input parameters

and provides an adjustment factor to the LUT value. Figure 2.16 illustrates a block diagram of the

proposed DPD architecture.


23

Figure 2.16: Temperature Compensated DPD Scheme Proposed by Hammi and Ghannouchi [33]

In summary, a truly static DPD system has significantly lower implementation cost and power overhead.

However, the traditional static DPD cannot adapt to changes in temperature and PA aging. Some new

architectures address this trade-off by introducing a temperature compensated static DPD system.

These systems have shown linearization gains for memoryless PAs [33].

2.5 Real-world PA Example: The DOCSIS 3.1 Specification

2.5.1 Introduction

Data Over Cable Service Interface Specification (DOCSIS) is an international telecommunications

standard that enables high-speed data transfer over existing cable TV (CATV) infrastructure. With

DOCSIS, cable providers can also provide internet access over their Hybrid Fiber-Coaxial cables. This

infrastructure enables two-way communication between individual cable modems (CM) located on

customer premises and the Cable Modem Termination Systems (CMTS) located at the cable headend.

The upstream communication port from CM to CMTS is shared by a neighbourhood whereas the

downstream communication port from CMTS to CM is shared by several neighbourhoods.

Introduced by CableLabs in 1997, DOCSIS 1.0 specifications permitted speeds of 38 Mbps downstream

and 9 Mbps upstream [34]. Driven by the need to deliver greater speeds and service to more customers,

CableLabs introduced DOCSIS 3.1 in October 2013. The new DOCSIS 3.1 specifications does away with

DOCSIS 3.0 CDMA modulation and introduces OFDM modulation, increasing capacities from 160 Mbps

downstream and 120 Mbps upstream to 10 Gbps downstream and 1 Gbps upstream [35-37].

Each CM includes an upstream transmitter and a downstream receiver. The upstream transmit chain can

be divided into signal processing modules and RF modules. The signal processing modules include


24

encoders, scramblers, a symbol mapper and a modulator [36, 38]. The RF modules follow the signal

processing modules and include a Digital to Analog Converter (DAC) and the upstream PA, as shown in

Figure 2.17. The focus of this thesis is the upstream PA and specifications must be met at the PA output.

The following sections categorize DOCSIS 3.1 upstream specifications into frequency allocation

specifications, modulation requirements and emission specifications.

Figure 2.17: RF Modules in Upstream Transmit Chain of DOCSIS 3.1 Cable Modem

2.5.2 Frequency Allocation

Upstream transmissions can occupy the 5MHz to 204MHz frequency range and downstream

transmissions can occupy the 258MHz to 1218MHz [36]. The CM must not cause harmful interference to

any downstream signals. The frequency range between 204MHz and 258MHz is considered the

transition band. The upstream transmission from a single CM occurs in bursts of OFDM waveforms that

can occupy any frequency in the upstream transmission frequency range. The bandwidth of the OFDM

signal can be as low as 24MHz and as high as 96MHz and a CM can transmit up to two independently

configurable 96MHz wide OFDM signals for a total of 192MHz of active channels [36]. The CM must

support agile placement of the OFDM channels in the upstream frequency range [36].

2.5.3 Modulation Requirements

DOCSIS 3.1 uses OFDMA for upstream modulation. OFDMA is a multi-user version of OFDM where

subsets of OFDM subcarriers are assigned to individual CMs. The subcarrier spacing can be either 25kHz

or 50kHz. In the 25kHz subcarrier spacing mode, the Inverse Discrete Fourier Transform (IDFT) size is

4096 with a maximum of 3801 active subcarriers in a signal [36]. In the 50kHz subcarrier spacing mode,

the IDFT size is 2048 with a maximum of 1901 active subcarriers [36].

The modulation on each subcarrier can range from Binary Phase Shift Keying (BPSK) to 4096 Quadrature

Amplitude Modulation (QAM). The OFDM symbol duration is 20us in the 50kHz subcarrier mode and

40us in the 25kHz subcarrier mode. A raised-cosine pulse-shaping filter is used. After appending the

RF Modules in Cable Modem

DACProposed

DPDUpstream

PA


25

cyclic prefix, the OFDM frame is windowed with a Tukey raised cosine window. OFDM signals following

this modulation scheme can have a Peak-to-Average Power Ratio (PAPR) of 14dB.

2.5.4 Emission Specifications

The receiver in the CMTS is tasked with demodulating the transmitted signal with a certain level of

accuracy. This imposes restrictions on the amount of distortions that fall within the signal band. In the

case of DOCSIS 3.1, the MER of an upstream transmission must be less than -44dB [36]. The upstream

transmission band is shared amongst CMs in a neighbourhood. Naturally, in-band emission

specifications exist to ensure that the transmission from one CM does not interfere with the upstream

transmission of another CM. The in-band specification for DOCSIS 3.1 (5MHz-204MHz) is -44dBc [36]. On

the other hand, the downstream transmission band is shared amongst several neighbourhoods so

interference from a single CM in one neighbourhood can affect multiple neighbourhoods. Only a small

transition band separates the upstream and downstream transmission frequencies. Hence, stringent

out-of-band emission specifications are required to ensure that the upstream transmission is limited to

the allocated upstream frequency range. The out-of-band specification for DOCSIS 3.1 is -50dBc [36].

The transmit power requirements are a function of the number and occupied bandwidth of the OFDM

channel [36]. The minimum highest value of total CM output power is 65dBmV RMS [36]. Given that the

OFDM signal can have a PAPR of 14dB, the peak output power of the PA can be 79dBmV.

2.6 Challenges of Predistortion for DOCSIS 3.1

DOCSIS 3.1 specifications present challenges for traditional DPD systems. First, the high PAPR of OFDM

signals necessitate a complicated DPD model. Second, the signal bandwidths involved are almost double

the bandwidths encountered in previous DPD studies conducted by Huang-Jie et al and Chao et al [39,

40]. Third, predistortion would be performed on a digital passband signal as opposed to the digital

baseband or analog passband approaches seen in the literature. Fourth, the bandwidths and center

frequencies involved give rise to situations where IMD and HD may both be present in the signal band.

Furthermore, as a result of the high-order nature of DOCSIS 3.1 applications, the stability of the DPD

system is precarious. Finally, DPD for wideband signals demands models with large memory orders,

which in turn increases hardware costs.


26

2.6.1 High PAPR of OFDM Modulation Scheme

DOCSIS 3.1 is the first DOCSIS standard to employ OFDM modulation. Multicarrier modulation schemes,

such as OFDM, and higher-order QAM constellations, such as 4096 QAM, are attractive to

communication systems because of their high bandwidth efficiency and high data rates [41]. However,

OFDM signals have high PAPRs, which require sufficient power back-off in the PA in order to be

amplified linearly [42]. Signals with high PAPRs are difficult for DPD because they push the PA deeper

into saturation. This stimulates higher-order nonlinearities in the PA and increases the nonlinearity

order of the DPD model [3]. Fortunately, some studies have shown significant ACLR improvements using

a memory polynomial DPD model for OFDM signals with bandwidths up to 40MHz [16, 26, 43, 44].

Furthermore, DPD often increases the PAPR of the original input signal to compensate for gain

compression at peak amplitudes. Additional headroom is needed to remedy this; the RMS output power

level should be backed off from Psat by more than the original PAPR [3].

2.6.2 Large Bandwidth

The ideal DPD model for a system depends on both the PA characteristics and the input signal

characteristics. Specifically, wideband signals stimulate memory effects in PAs, increasing the DPD

model complexity. The DPD model requires larger memory order, thus adding more coefficients to

obtain the necessary correction [3]. Generally, few DPD systems are intended for signal bandwidths

larger than 20MHz [3]. More recently, DPD systems targeting 100MHz Long-Term Evolution Advanced

(LTE Advanced) applications have emerged [39, 40]. Both of these studies use complicated Volterra

based DPD models to achieve ACLR improvements of 29dB and 15dB for OFDM signals with PAPRs of

6.5dB and 9.8dB respectively [39, 40].

Figure 2.18: Training with Equalized Output Signal Proposed by Braithwaite [45]

To put things into perspective, DOCSIS 3.1 permits simultaneous upstream transmission bandwidths of

192MHz. Therefore, any proposed DPD system would have to linearize bandwidths that are almost twice


27

the bandwidths of current DPD systems. Since wider bandwidths usually equate to higher-order

memory, we would expect a large number of filter taps in the DPD model. However, this would increase

the power and implementation costs of the transmitter and render it unfeasible for DOCSIS CM

applications. Fortunately, if the wider bandwidth stimulates only linear memory effects in the PA, these

linear memory effects may be mitigated without complicating the DPD model. Linear equalization

techniques may be used to alleviate memory effect due to non-constant frequency response, thus

reducing the memory order of the DPDs fundamental response [45-47]. In fact, Braithwaite [45]

proposes an adaptive DPD system with an equalizer in the observation loop (refer to Figure 2.18). Power

and implementation costs may be further reduced if this scheme were static: the DPD coefficients are

trained during offline factory calibration with an equalizer but the CM transmitter implementation does

not include the observation path or equalizer. Assuming ideal DPD linearization with this technique, the

remaining error at the PA output would be due to linear memory, which will be compensated by the

equalizer in the CMTS upstream receiver.

2.6.3 Digital Pass-Band Input Signals

Digital predistortion is most commonly performed on digital baseband signals. The RF modules in the

DOCSIS 3.1 architecture do not have access to the input baseband signal. In fact, due to the low center

frequencies in use, the input signal to the RF modules is the digital passband signal. This case has not yet

been addressed in literature. Presently, in cases where the baseband signal is not available,

predistortion is performed on RF analog passband signals [28, 48-51]. These analog predistortion

architectures generally digitize the envelope of the incoming signal and use a LUT to determine the

appropriate analog gain and phase correction to apply to the analog signal [28, 48-51]. However, LUT

approaches are not well suited for PAs with memory. Fortunately, since the DOCSIS 3.1 RF module input

signal is digital, use of DPD basis functions with memory correction capabilities is still possible. The only

difference will be that these basis functions are in passband instead of baseband.

2.6.4 Correcting HD and IMD

Digital predistortion is ubiquitous in wireless applications centered at frequencies in the GigaHertz range

and bandwidths up to several MegaHertz. DOCSIS 3.1 upstream operations involve frequencies in the

5MHz to 204MHz range. The bandwidths are larger and the center frequencies are much smaller than

the bandwidths and center frequencies usually encountered in DPD systems. The difference in


28

frequency range poses a new problem currently unaddressed in the literature. The problem is that of

having both HD and IMD within the signal bandwidth.

Traditionally, DPD systems linearize IMD but do not consider HD as it falls far from the signal bandwidth

and is usually filtered away [3]. In DOCSIS 3.1 upstream, there are several wideband transmission cases

where HD will fall in the signal bandwidth. For example, in the case of two 96MHz wide OFDM signals

with center frequencies at 53MHz and 152MHz, the HD of the lower frequencies will fall into the upper

frequencies as illustrated in Figure 2.19. There are no studies investigating how this may impact DPD

performance.

Figure 2.19: Example of DOCSIS 3.1 Case Exhibiting Transmit signal, IMD and HD Spectral Overlap.

2.6.5 Stability

Stability is another challenge encountered in DPD systems for wideband, high PAPR applications. DPD

system stability depends on the condition number of the estimation matrix [23]. When higher-order

nonlinear terms are included in the DPD model, there is more correlation between DPD model terms

and consequently, the condition number of the estimation matrix increases. In fact, it can be shown that

the condition number increases exponentially with polynomial order [14, 15]. Higher condition numbers

mean the estimation procedure is more prone to numerical instability issues when the estimation matrix

is inverted [14, 15]. This introduces numerical errors and divergence to the coefficient estimation

process. Fortunately, there exist simple orthogonalization techniques to reduce the matrix condition

number [14, 15]. Given that the modulated signal is normally distributed, an orthogonal basis exists

which spans the same space as that spanned by , ( ) ( ) ( ) -

Pow

er/F

req

uen

cy

Frequency

OFDM1 OFDM2

IMD of OFDM1

IMD of OFDM2

HD3 of OFDM1

53MHz 152MHz


29

[14]. For a real Gaussian signal with unit variance, the first five orthogonal polynomials are simply the

first five Hermite polynomials:

[ ( ( ))

( ( ))

( ( ))

( ( )) ( ( ))

]

[

( )

√ ( ( ) )

√ ( ( ) ( ))

√ ( ( ) ( ) )

√ ( ( ) ( ) ( ))

]

(2.23)

Studies have shown that orthogonal polynomial DPD models can overcome instability issues [14, 15].

The condition number of the estimation matrix may also be reduced using QR decomposition [52].

2.6.6 Large Memory Order

Wideband signals stimulate large memory effects in PAs, requiring more coefficients to obtain the

necessary correction. Also, the DPD input signal must be oversampled by at least the highest DPD

nonlinearity order to prevent spectral regrowth aliasing. For a wideband signal, this means the input

signal is heavily oversampled. The result of both of these effects is a large number of filter taps where

consecutive samples are strongly correlated. To remedy this, a group of R samples can be assumed to

have the same value. Existing DPD models can be refined to have R-sample delay increments instead of

single-sample delay increments without loss of fidelity [53]. In fact, several studies have used this sparse

delay pruning technique to reduce the DPD model order [54-56]. The sparse delay version of the

memory polynomial would be:

( ) ∑ ∑ ( )

(2.24)

Every sample is processed but each output sample depends on every Rth input sample. The value of R

can be estimated from the ratio of the signal bandwidth to the sampling rate. The sparse delay pruning


30

method reduces the model order, reducing the condition number of the estimation matrix and

improving the model accuracy. Studies have shown better modelling performance using sparse delay

taps [53, 54]. Finally, reducing the model order also reduces hardware and power costs.

Simulation Model

31

3 Simulation Model

3.1 Introduction

In this section, the feasibility of a static DPD system for DOCSIS 3.1 upstream application is investigated

using a Cadence extracted model of the MxL235 upstream PA. First, transient simulations are used to

study the nonlinear behaviour of the PA, specifically, the low amplitude frequency response, AM-AM

and AM-PM response to gain insights into DPD model requirements. Next, a low-order static DPD model

is derived by testing the simulation model with OFDM signals generated in Matlab. Finally, the impact of

temperature, process and signal variations on DPD performance is investigated.

3.2 Power Amplifier Frequency Response

The PA’s gain and phase response varies over its frequency range when operating entirely in its linear

region. This is the fundamental/first-order frequency response of the PA. It was determined from

simulations that when the applied signal is operating at a back-off of 24dB from Psat, the distortion is

below 65dBc.

The Cadence model of the PA is tested with a wideband OFDM signal from 5MHz to 200MHz with a

PAPR of 14dB operating at 24dB back-off. The PA input and the sampled PA output are both normalized

to an RMS level of 1V and time-aligned. Time alignment is performed by upsampling by 25, computing

cross-correlation, delaying by index of maximum correlation and downsampling by 25. The Fast Fourier

Transform (FFT) of input and output is computed after trimming both input and output data sequences

to the same length. In 1MHz steps in the FFT, gain is measured as the ratio of output amplitude to input

amplitude and phase is the difference between output and input angle in radians. The resulting

frequency response of the PA Cadence model is given in Figure 3.1.

Simulation Model

32

Figure 3.1: Simulated PA Gain and Phase at 10dB backoff from required output RMS level

It is clear from the non-constant gain and phase response that the PA exhibits linear memory effects.

Hence, the PA model and the DPD model would need several taps for the first-order component.

The power spectral density (PSD) of the PA output under typical operating conditions overlaid with the

DOCSIS 3.1 mask is presented in Figure 3.2. The PA is tested with a wideband OFDM signal with 14dB

PAPR at 69dBmV RMS output. According to simulation results, the PA meets DOCSIS emission criteria

under typical conditions.

Figure 3.2: PSD of Simulated PA Output Under Typical Operating Conditions (80°C and TT process) with DOCSIS 3.1 Mask

3.3 AM-AM Effects

The AM-AM behaviour of the PA Cadence model is extracted by testing the PA with a wideband OFDM

signal with 195MHz bandwidth centered at 102.5MHz and a PAPR of 14dB. The input and output are

0 20 40 60 80 100 120 140 160 180 200-0.5

0

0.5

Simulated PA Gain and Phase

No

rmalized

Gain

(d

B)

0 20 40 60 80 100 120 140 160 180 200-0.02

0

0.02

Ph

ase (

rad

)

Frequency (MHz)

Phase

Gain

0 500 1000 1500-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

Simulated Wideband OFDM Output Spectrum

Po

wer/

Fre

qu

en

cy (

dB

m/H

z)

Frequency (MHz)

PA Output Spectrum

DOCSIS 3.1 Mask

Simulation Model

33

normalized to an RMS of 1V and time aligned. The magnitude of each output sample is plotted against

the input magnitude. The resulting AM-AM plot is presented in Figure 3.3.

Figure 3.3: AM-AM Behaviour of Simulated PA with Wideband (195MHz Bandwidth, 102.5MHz Center Frequency) OFDM Signal

Dispersion around the ideal AM-AM curve is indicative of memory effects. Also, gain compression is

observable at higher input signal magnitudes. However, the gain compression is not severe; it can be

modelled by a third or fifth order memoryless polynomial. In fact, the measured AM-AM data points

were fit to a fifth degree polynomial using Matlab’s Basic Fitting Tool which minimizes residuals and the

resulting curve is overlaid with the measured points. This implies that the PA is weakly non-linear; the

nonlinearity order is low.

3.4 AM-PM Effects

Figure 3.4: AM-PM Behaviour of Simulated PA with Wideband (195MHz Bandwidth, 102.5MHz Center Frequency) OFDM Signal

Simulation Model

34

The AM-PM behaviour of the PA Cadence model is extracted by testing the PA with a wideband OFDM

signal with 195MHz bandwidth centered at 102.5MHz and a PAPR of 14dB. The input and output are

normalized to an RMS of 1V, time-aligned and down-converted to baseband. The phase difference

between each output and input sample is plotted against the input magnitude. The resulting AM-PM

plot is presented in Figure 3.4.

Similar to the observed AM-AM effects, the fuzziness of the simulated AM to PM points is attributed to

memory effects. The phase difference appears larger at smaller input magnitudes because of noise. The

simulated AM-PM points do not deviate from the ideal AM-PM curve, hence the PA does not exhibit

significant AM-PM effects. Therefore, crossterms (e.g., x(n)·x(n-1)) may be excluded from the DPD

model.

3.5 Post-Distortion Test Procedure

Evaluating DPD models and assessing predistortion performance over various operating conditions

requires many time-consuming transient Cadence simulations. To reduce the number of simulations, the

post-distortion results are evaluated instead. According to Pth order inverse theory, the predistortion

results and post-distortion results of a PA with limited nonlinearity order are equivalent [57]. Therefore,

the suppression observed in the post-distortion signal is the amount of suppression that would be

achieved if the DPD model preceded the PA (predistortion). Figure 3.5 depicts the DPD architecture

(indirect learning scheme, LS coefficient estimation and static training) and post-distortion test

procedure used in sections 3.6 and 3.7. The test procedure can be divided into two stages: DPD training

and DPD testing. The two stages are described in sections 3.5.1 and 3.5.2.

Figure 3.5: Simulation Post-Distortion Test Set Up

Signal Generation

1/rms(Y)

LS

X(n)PA

Cadence

1/rms(X)

DPD

Matlab

Simulation Model

35

3.5.1 DPD Training

The reference training signal is generated in Matlab at 9GS/s and imported into Cadence as a text file.

Cadence uses a linear interpolator so the sampling rate of the input must be a several times larger than

the output sampling to avoid aliased images. After a transient simulation, the PA output is sampled in

Cadence at 3GS/s and exported to Matlab and the input is downsampled by 3. The input and output are

normalized to an RMS of 1V and time-aligned by upsampling by 25, computing cross-correlation,

delaying by the index of maximum cross-correlation and downsampling by 25. The LS block finds DPD

coefficients that best transform y(n) to x(n) using least squares estimation.

Mean Square Error (MSE) is a common metric used to evaluate the training procedure and determine a

suitable DPD model. Least squares estimation in the LS block attempts to minimize the mean square

error between the reference x(n) and predicted reference ∑ * ( )+ , called the residual error.

The MSE is simply the residual error normalized by the power of x(n) after time alignment:

(∑ | ( )|

∑ | ( ) ∑ * ( )+ |

) (3.1)

Where, =[a1 ... aP] are the coefficients from LS estimation and ( ( )) is the Pth basis function applied

to y(n). An MSE of 50dBc or higher implies DPD would suppress distortion to at least 50dBc. In addition,

the power spectral density of the residual error signal can indicate which frequency ranges degrade the

MSE the most.

3.5.2 Post-Distortion Testing

After a DPD model is determined, the measured Cadence output is applied to the DPD model in Matlab

to generate the post-distortion signal (xpostDPD(n)). The predistortion performance of the determined

coefficients and DPD model are evaluated using post-distortion results.

Worst in-band distortion and worst-out-of band distortion metrics verify whether post-distortion results

meet the DOCSIS 3.1 specification. Worst in-band distortion is measured as the ratio of the signal power

at center frequency to the largest distortion power in the 5MHz to 204MHz frequency range. The signal

power is measured in a 4MHz bandwidth centered at the signal center frequency and the largest in-band

distortion is measured in a 4MHz bandwidth centered at the largest distortion at least 2.5MHz away

Simulation Model

36

from the signal band edge. DOCSIS 3.1 specifications require in-band distortion levels to be above

45dBc. Similarly, worst out-of-band distortion is measured as the ratio of the signal power at the center

frequency to the largest distortion power in the 204MHz to 258MHz frequency range. The signal power

is measured in a 4MHz bandwidth centered at the signal center frequency and the largest out-of-band

distortion is measured in a 4MHz bandwidth centered at the largest distortion at least 2MHz away from

the 204MHz transition point. DOCSIS 3.1 specifications require out-of-band distortion levels to be above

50dBc. In-band suppression is the difference between the worst in-band distortion in the post-distortion

signal and the original output. Out-of-band suppression is the difference between worst out-of-band

distortion in the post-distortion signal and the original output.

3.6 DPD Model Selection

Simpler DPD models and architectures are preferred due to lower hardware and power costs. Thus, the

post-distortion performance of a memoryless 5th order polynomial DPD model is assessed first. The PA is

tested with a wideband OFDM signal at 69dBmV RMS output and with 14dB PAPR. Least squares

estimation and indirect learning architecture are employed to determine the DPD model coefficients

with an accuracy of 34dB MSE. Figure 3.6 depicts the power spectral density of the PA output and

resulting post-distortion signal with a 5th order memoryless polynomial DPD model. These results

suggest some out-of-band distortion suppression can be achieved using a weakly nonlinear memoryless

model. The residual error signal implies that the in-band error is the largest contributor to MSE

degradation.

Figure 3.6: Power Spectral Density of PA Output, Post-Distortion and Residual Error when Modelling with

Memoryless 5th

Order Polynomial Model

Figure 3.7: Power Spectral Density of PA Output, Post-Distortion and Residual Error when Modelling with

Memory Polynomial Model with 4 Taps for First, Third, Fifth and Seventh Order Nonlinearities

(Condition=1.3e11)

0 1 2 3 4 5

x 108

-120

-110

-100

-90

-80

-70

-60

Power Spectral Density

Po

wer/

Fre

qu

en

cy(d

Bm

/Hz)

Frequency (Hz)

Output

Post-Distortion

Error

MSE:34.3382dB

0 1 2 3 4 5 6

x 108

-120

-110

-100

-90

-80

-70

-60


Po

wer/

Fre

qu

en

cy(d

Bm

/Hz)

Frequency (Hz)

Output

Post-Distortion

Error

MSE:48.8086dB

Simulation Model

37

Next, the DPD model complexity is increased to that of a memory polynomial model with 4 taps for the

first, third, fifth and seventh order nonlinearities (Nonlinearity order P=7 and Memory Order M=4 with

N1=2, N3=2, N5=2 and N7=2). Least squares estimation and indirect learning architecture are employed to

determine the DPD model coefficients with an accuracy of 47.7dB MSE. Figure 3.7 depicts the power

spectral density of the PA output and resulting post-distortion signal with the memory polynomial DPD

model. These results suggest more out-of-band distortion suppression may be achieved using a memory

polynomial model. Furthermore, the residual error signal implies that the in-band error can be

significantly reduced by adding memory terms to the DPD model.

A memory polynomial with nonlinearity order of 7 and memory order of 4 generates a DPD model of

order 16. However, since the output is sampled at 4 times the Nyquist rate, these 16 DPD terms are

strongly correlated. The condition number of the coefficient estimation matrix is 1.3e11; the coefficient

estimation process likely has numerical errors and instability issues. To remedy this, the orthogonal

memory polynomial with sparse delay taps is used instead:

[ ( )

( )

]

[

]

[ ( ( ))

( )( ( ))

( ( ))

( )( ( ))

( ( ))

( ( ))

( ( ))

( ( ))

( ( ))

]

(3.2)

Where ( ( )) refers to the pth order orthogonal polynomial described in section 2.6.3 with a delay

of k samples. 2·Np is the total number of taps for the pth order polynomial. Every sample is processed but

x(n) depends on every Rth sample of y(n).

Simulation Model

38

Figure 3.8: Power Spectral Density of PA Output, Post-Distortion and Residual Error when Modelling with Orthogonal Memory Polynomial Model with 4 Taps for First, Third, Fifth and Seventh Order Nonlinearities and R=4

(Condition=131)

Figure 3.8 depicts the power spectral density of the PA output and resulting post-distortion signal with

the orthogonal memory polynomial DPD model with sparse delay taps. The nonlinearity order is 7,

memory order is 4 and the sparse delay tap factor is 4 (R=4). Using orthogonal polynomials and sparse

delay taps decreases the condition to 131 and improves MSE to 50dB. So, using orthogonal techniques

improves coefficient estimation by 2dB. These results suggest that our distortion suppression targets

can be achieved with the orthogonal memory polynomial model with sparse delay taps. The next step is

to determine the best reference and observation signals for training.

3.7 Post-distortion Simulation Results across Temperature and Process

The orthogonal memory polynomial shows promise as a DOCSIS 3.1 DPD model. However, a DPD block

in the DOCSIS 3.1 upstream block will be robust to variations in signal characteristics, temperature and

process. The implications are twofold. First, an appropriate training signal and training conditions for the

various operating conditions must be determined. Then, the post-distortion performance of the DPD

model should be evaluated against signal, temperature and process variations.

3.7.1 Post-distortion Training Signal Selection

The RF modules in the upstream transmit chain, which will house the DPD block, has no knowledge of

the incoming signal’s bandwidth or center frequency. The bandwidth can vary from 24MHz to 192MHz

and the center frequency can be placed anywhere in the upstream frequency range. Therefore, the DPD

0 5 10 15

x 108

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50


Po

wer/

Fre

qu

en

cy(d

Bm

/Hz)

Frequency (Hz)

Output

Post-Distortion

Error

MSE:50.0236dB

Simulation Model

39

model must be resilient to variations in signal bandwidth and center frequency. The DPD’s tolerance to

changes in signal characteristics is tested using four test signals: a narrowband OFDM signal at low

frequency (25MHz at 20MHz), a narrowband OFDM signal at mid frequency (25MHz at 100MHz), a

narrowband OFDM signal at high frequency (25MHz at 188MHz) and a wideband OFDM signal (5MHz to

200MHz).

Only static DPD systems may be considered for DOCSIS 3.1 upstream applications due to hardware and

power costs. However, static systems are sensitive to temperature variations. Unfortunately, as a result

of self-heating and other components in the upstream transmit chain, the junction temperature of the

upstream PA is predicted to vary from 0°C to 130°C. To determine whether a temperature compensated

static DPD scheme is required, the temperature tolerance of the DPD system is tested.

Similarly, training a universal DPD model using a sample board and applying those coefficients to all

boards is preferred to performing individual calibration. Thus, the resilience of the DPD model to

process variations is also analyzed. The typical (TT), fast (FF) and slow (SS) process corners are

considered.

Four signal corners, three temperature corners and three process corners are simulated. By training four

DPD coefficients for each of the four test signals and testing each DPD model with the four test signals, it

was determined that training with the wideband signal yields DPD coefficients that are most resilient to

signal variations. Similarly, by training nine DPD coefficients for each of the nine temperature and

process corners, it was determined that training a wideband signal at 130°C with the typical process

produces coefficients that are most tolerant to process and temperature variations. In summary, for a

static DOCSIS 3.1 DPD system with no temperature compensation or individual factory calibration,

training with a wideband OFDM signal at 130°C with the typical process results in the most robust DPD

model.

3.7.2 Post-Distortion Results with Temperature and Process Variations

The DPD model has been chosen to be the orthogonal memory polynomial with memory order 4 and

nonlinearity order 7 with sparse delay taps of factor 4 (R=4). The DPD coefficients are trained using LS

estimation and the indirect learning scheme. The training signal is a wideband OFDM signal at 130°C

Simulation Model

40

with the typical process. The post distortion performance of this DPD model and DPD coefficients is

evaluated against varying temperature, process and signal characteristics.

Figure 3.9: Worst In-Band Distortion and Worst Out-of-Band Distortion for 25MHz OFDM Signal at 20MHz Center Frequency Across Temperature and Process


Figure 3.9 depicts in-band and out-of-band distortion results for a narrowband low frequency signal

(25MHz OFDM signal at 20MHz) across temperature and process. Similarly, Figure 3.10 demonstrates in-

0 20 40 60 80 100 120 14045

50

55

60

65

70

75

80

85

90

95

Junction Temperature (deg C)

Avera

ge P

ow

er

(dB

c)

Worst In Band and Worst Out of Band for 25MHz at 20MHz

Worst In Band TT

Worst In Band FF

Worst In Band SS

Worst In Band TT-DPD

Worst In Band FF-DPD

Worst In Band SS-DPD

Worst Out of Band TT

Worst Out of Band FF

Worst Out of Band SS

Worst Out of Band TT-DPD

Worst Out of Band FF-DPD

Worst Out of Band SS-DPD

0 20 40 60 80 100 120 14055

60

65

70

75

80


Avera

ge P

ow

er

(dB

c)


Worst In Band TT

Worst In Band FF

Worst In Band SS










Simulation Model

41

band and out-of-band suppression results for a narrowband mid-frequency signal (25MHz OFDM signal

at 100MHz) across temperature and process. In some of these cases, the suppression is negative; the

distortion performance of the post-distortion signal is worse than the raw output signal. However, in

these cases, the distortion level is far above the required level of 50dBc. Hence, negative suppression is

acceptable in these cases if DPD aids distortion performance in more critical cases.

Figure 3.11 depicts in-band and out-of-band distortion results for a narrowband high frequency signal

(25MHz OFDM signal at 188MHz) across temperature and process. These results suggest DPD will

improve distortion for the high frequency OFDM signal for all temperatures and processes tested. In

addition, the distortion level in the high frequency case for the slow process is close to the minimum

required value of 50dBc, hence it is the limiting case.


Similarly, Figure 3.12 demonstrates in-band and out-of-band distortion results for a wideband OFDM

frequency signal (195MHz OFDM signal at 102.5MHz) across temperature and process. PAs with the

typical and slow process benefit significantly from DPD for the temperatures tested. At the lowest

temperature, the fast process sees distortion performance degradation with DPD. This performance

trade-off is acceptable since the slow process and higher temperatures are the more strenuous and

0 20 40 60 80 100 120 14050

55

60

65


Avera

ge P

ow

er

(dB

c)


Worst In Band TT

Worst In Band FF

Worst In Band SS










Simulation Model

42

critical cases. However, a performance trade-off may be avoided altogether by using a temperature

compensated DPD scheme.

Figure 3.12: Worst In-Band Distortion and Worst Out-of-Band Distortion for 195MHz OFDM Signal at 102.5MHz Center Frequency Across Temperature and Process

In summary, the PA’s distortion performance degrades with temperature, frequency and with the slow

process. Fortunately, DPD improves the PA’s performance at higher temperatures, frequencies and with

the slow process. However, DPD degrades PA performance when the PA already performs well, such as

in low frequency cases with the fast process. Therefore, this DPD performance trade-off is acceptable

since higher frequencies and temperatures are the performance limiting cases. Finally, DPD

performance is sensitive to PA temperature variations and thus may benefit from a temperature

compensated DPD scheme.

3.8 Summary

The nonlinear behaviour of the DOCSIS 3.1 upstream PA Cadence simulation model was analyzed and

used to construct a DPD model. The PAs low amplitude frequency response alludes to the presence of

linear memory effects. The measured AM-AM and AM-PM response suggests a weakly nonlinear DPD

model with memory should be sufficient. Using MSE as a metric, the orthogonal memory polynomial

model was chosen as the simplest DPD model that could model the PA inverse with an accuracy of -

50dBc MSE. A wideband OFDM signal at the higher temperature corner and typical process was chosen

as the training signal which produced DPD coefficients most resilient to temperature, process and signal

0 20 40 60 80 100 120 14050

52

54

56

58

60

62


Avera

ge P

ow

er

(dB

c)

Worst In Band and Worst Out of Band for Wideband Signal

Worst In Band TT

Worst In Band FF

Worst In Band SS










Simulation Model

43

variations. The post-distortion of the DPD model with one set of coefficients was tested at temperature,

process and signal corners. DPD suppresses distortion and improves PA linearity in the more demanding

cases (high temperature, slow process) at the cost of degrading PA performance when the linearity is

already exceptional. A temperature compensated DPD scheme would improve DPD performance across

temperature with only a slight increase in power consumption.

Pre-distortion Test Bed Implementation

44

4 Pre-distortion Test Bed Implementation

4.1 Introduction

Many challenges are encountered when trying to implement a DPD system. Implementing a DPD test

bed that meets the stringent requirements of the DOCSIS 3.1 specifications is particularly difficult. The

distortion specifications impose some linearity requirements, the signal bandwidth imposes speed

requirements and the signal specifications impose memory requirements. These requirements are

covered in section 4.2. The AD9625 ADC evaluation board and the AD9739A DAC evaluation board from

Analog Devices were chosen as the ADC and DAC in the DPD test bed. The performance of both of these

components is evaluated in sections 4.3 and 4.4. Particular implementation details pertaining to the

clock are considered in section 4.5 and FPGA implementation is described in section 4.6.

4.2 Requirements and Specifications

Regardless of whether the DPD system is adaptive or static, the DPD system requires two digital input

signals for training: the reference signal and the observation signal. The reference signal is the digital

signal at the input to the RF modules, before the DAC. The observation signal at the PA output must be

digitized with an Analog to Digital Converter (ADC). The linearity of both the DAC and ADC must be 10dB

better than the desired linearity of the system to avoid introducing distortion to the system [3]. So, if a

linearity of 50dBc is desired, the DAC and ADC should not produce any distortions, measured by IM3 or

Spurious Free Dynamic Range (SFDR), lower than 60dBc. Assuming a Signal to Noise and Distortion

(SINAD) of 60dBc, the distortion specification translates to an Effective Number of Bits (ENOB) of 9.6

bits.

The signal characteristics also impose some conditions on the DAC and ADC specifications. In general,

the observation signal and the predistorted signal have a wider bandwidth than the original input signal

because of the distortion component and distortion compensation signal. As a result, the sampling rate

of both the DAC and ADC need to be several times higher than the Nyquist rate of the original input


45

signal. Theoretically, a DAC and ADC sampling rate of at least 2GS/s is required to compensate up to the

fifth-order distortions of a DOCSIS 3.1 signal with a frequency range of 5MHz to 200MHz.

The OFDM modulation specifications and the ADC/DAC sampling rate determine the required memory

length for a single capture. Given that one OFDM frame can be 40us long and assuming 2GS/s sampling,

a memory of at least 80000 samples is required to capture one OFDM frame. Also, the least squares

estimation process has better convergence with larger number of samples. So, a solution with the

largest on-board memory as possible is preferred.

In summary, the DPD test bed should have an ENOB of at least 9.6 bits, a sampling rate of at least 2GS/s

and a data capture length of at least 80000 samples.

4.3 A/D Converter

The AD9625-2.5EBZ ADC evaluation board and HSC-ADC-EVALEZ FIFO board presented in Figure 4.1

from Analog Devices performs as a digitizer that meets the DOCSIS 3.1 DPD specifications. The AD9625 is

a 12 bit 2.5GS/s single-channel ADC with a Noise Spectral Density (NSD) of -149.5dBFS at 2.5GS/s [58].

The SINAD is 58dBc and the ENOB is 9.4 bits. The input signal voltage range of the AD9625 evaluation

board is 3.6V peak-to-peak. Due to a BAL0006SM single-to-differential balun [59] at the input, the input

signal frequency range must be above 0.5MHz. The board requires an external 2.5GHz clock source or it

may be modified to accommodate an on-board clock chip.

Figure 4.1: AD9625-2.5EBZ ADC evaluation board and HSC-ADC-EVALEZ FIFO board

AD9625 -2.5EBZHSC-ADC-EVALEZ

Clock

Input

Power Adapter

Power Adapter

USB


46

The HSC-ADC-EVALEZ data capture board connects to the AD9625 evaluation board via a High Pin Count

FPGA Mezzanine Card (HPC-FMC) connector and communicates using the JESD204B serial interface [60].

The data capture board and ADC are both programmable using a Serial Peripheral Interface (SPI) port.

Analog Devices also provides an Application Programming Interface (API) called HadBoardApi with

common interface functions in Matlab to program the capture board via a USB connection. A maximum

of 131000 12 bit samples can be captured at a time. Captured samples can be directly imported to

Matlab in real time.

The ADC was tested with single tones generated by an Agilent E4432B. The E4432B is a 14 bit RF

synthesizer in the 250kHz to 3GHz frequency range [61]. The SFDR of the synthesizer is larger than

65dBc [61]. Low pass filters were used to ensure that the distortion of the generator is less than the

distortion of the ADC. This limits the number of frequencies that can be tested. The SFDR is measured as

the ratio of the fundamental signal power to the largest spur. The measured SFDR as a function of ADC

input signal amplitude for 10MHz, 90MHz and 200MHz is given in Figure 4.2.The SFDR at higher input

amplitudes is around 75 dBc for all frequencies of interest. The SFDR degrades for higher frequencies at

lower input amplitudes due to spurs at higher frequencies.

Figure 4.2: Measured SFDR of AD9625 at 10MHz, 90MHz and 200MHz

Similarly, the ADC was tested with two tones generated by two Agilent E4432B generators and a splitter.

Low pass filters are placed at each E4432B output and the output power of the E4432B must be reduced

until the intermodulation distortion of the combined output is larger than 75dBc. The low pass filters

limit the number of frequencies that can be tested. The interaction between the two E4432B generators

-15 -10 -5 050

55

60

65

70

75

80

Input Amplitude (dBFS)

Am

plitu

de (

dB

c)

Measured SFDR

10MHz

90MHz

200MHz


47

limits the permitted output power. IM3 is measured as the ratio between the fundamental tone at the

lower frequency and the largest IM3 spur. The measured IM3, where one tone is fixed at 90MHz and the

other tone frequency varies, is given in Figure 4.3. The measured IM3, where one fixed at 150MHz and

the other tone frequency varies, is also given in Figure 4.3. The measured IM3 is always higher than

64dBc.

Figure 4.3: Measured IM3 for AD9625 ADC with Varying Tone Spacing Vs. Center Frequency

4.4 D/A Converter

The AD9739A-FMC-EBZ DAC evaluation board from Analog Devices and the ML605 FPGA evaluation kit

from Xilinx perform as an arbitrary waveform generator that meets the DOCSIS 3.1 DPD specifications.

Figure 4.4 presents the DAC-FPGA configuration. The AD9739A is a 14 bit 2.5GS/s single channel DAC

capable of synthesizing wideband signals of up to 1.25GHz of bandwidth [62]. The DAC has a Noise

Spectral Density (NSD) of -167dBm/Hz at 100MHz [62]. The output signal voltage range of the AD9739A

evaluation board is 450mV peak-to-peak. Due to a TC1-33-75G2+ differential-to-single-ended

transformer [63] at the output, the output signal frequency range must be above 5MHz. The evaluation

board also includes an on-board ADF4350 clock chip which can generate a 2.5GHz clock from a 25MHz

crystal [64]. An alternate clock path is available for driving the clock externally.

40 60 80 100 120 140 160 180 20064

66

68

70

72

74

76

Frequency (MHz)

Am

plitu

de (

dB

c)

Measured IM3

90MHz

150MHz


48

Figure 4.4: AD9739A-FMC-EBZ DAC evaluation board and ML605 FPGA

The AD9739A DAC evaluation board connects to the ML605 via a Low Pin Count (LPC) FMC connector.

The ML605 is connected to a PC using two USB cables to the JTAG and UART USB connectors on the

ML605. One connection is for programming the FPGA and the other is for reading from the FPGA. There

is also an Ethernet connection between the ML605 and the PC. This is for downloading waveforms from

Matlab to the ML605. The ML605 can store up to 180000 16 bit samples where the last two bits of each

16-bit sample are ignored by the 14-bit DAC.

The SFDR of the DAC was measured using an Agilent N9030 PXA Signal Analyzer [65], which has a

bandwidth up to 50GHz. The SFDR of the N9030 is about 77dBc nominal for signals within the analysis

bandwidth [65]. The SFDR of the DAC was measured by generating a tone and measuring the resulting

harmonics using the N9030. The Resolution Bandwidth of the N9030 was set to 500kHz and trace

averaging was enabled. The SFDR is measured as the ratio of the power in the fundamental tone to the

largest harmonic. The measured DAC SFDR as a function of signal frequency is given in Figure 4.5. It

should be noted that the SFDR is generally above 71dBc.

Input Clock

Output

Power Adapter

JTAG and UART


49

Figure 4.5: Measured SFDR of AD9739A DAC Evaluation Board vs. Frequency

Similarly, the DAC synthesized two tones with 1MHz frequency separation at various frequencies. The

Agilent N9030 PXA Signal Analyzer was used to measure the amplitudes of the resulting intermodulation

terms. IM3 is measured as the ratio between the fundamental tone at the lower frequency and the

largest IM3 spur. The measured IM3 as a function of frequency is given in Figure 4.6. It should be noted

that the IM3 is above 74dBc across the 5MHz to 200MHz DOCSIS 3.1 upstream frequency range.

Figure 4.6: Measured IM3 of AD9739A DAC Evaluation Board vs. Frequency

4.5 Clock Considerations

The ADC and DAC in the DPD test bed both require a 2.5GHz clock source. The AD9739A DAC evaluation

board has an on-board 2.5GHz clock and the AD9625 ADC evaluation board requires an external source.

Several clock source non-idealities must be addressed in order to ensure proper operation. Clock jitter

and clock drift are two such issues that are described in sections 4.5.1 and 4.5.2.

0 20 40 60 80 100 120 140 160 180 20071

72

73

74

75

76

77

Measured SFDR

Am

plitu

de (

dB

c)

Frequency (MHz)

0 20 40 60 80 100 120 140 160 180 20074

75

76

77

78

79

80

81

Measured IM3

Am

plitu

de (

dB

c)

Frequency (MHz)


50

4.5.1 Clock Jitter

Clock jitter is the deviation of the clock edge from its ideal location [66]. Thermal noise, power supply

noise, PLL circuitry, crosstalk and reflections are all possible sources of clock jitter [67]. An impact of

clock jitter is an increased noise floor and degradation in the device SNR. With a fixed amount of clock

jitter, SNR degradation depends on the input tone frequency and it degrades with increasing frequency

[67]. In fact, the SNR degradation due to clock jitter can be calculated as:

( ) (4.1)

Where fin is the input tone frequency and tjitter is the RMS clock jitter [67]. Given the quoted ADC SNR of

57dBc and input frequency of 200MHz, the RMS jitter of the external clock source should be below

500fs to achieve the quoted ADC performance [58].

The AD9625 ADC evaluation board requires an external 2.5GHz signal. An on-board clocking solution is

preferred over using a RF synthesizer as the clock source. The CVC055BE-2430-2585 Voltage Controlled

Oscillator (VCO) from Crystek Microwave [68] is a 2.5GHz frequency synthesizer with an RMS jitter of

120fs. With some board modifications, this VCO was used as an on-board clock source for the AD9625

ADC evaluation board.

4.5.2 Clock Drift

Clock sources require an oscillator; the oscillator can be electrical or a crystal. Electrical oscillators, such

as a Voltage Controlled Oscillators (VCO), exhibit frequency drift. Frequency drift is an undesired

progressive change in oscillator frequency with time. Reasons for frequency drift in VCOs include tuning

voltage drift, power supply drift and load changes [69]. Regardless of the reason, frequency drift can

severely impede DPD training.

Training DPD coefficients using LS involves a comparison between PA input and output to derive the

inverse relation. The PA input is the waveform generated by the DAC and stored on the FPGA. The PA

output is the waveform measured by the ADC. The AD9625 ADC evaluation board uses the 2.5GHz VCO

from Crystek and the AD9739A evaluation board uses the 2.5GHz ADF4350 VCO from Analog Devices

[70]. However, during waveform generation and capture, the frequencies of the two VCOs will drift

relative to one another. So, the DAC may be generating a waveform at 2.500GS/s but the ADC may be


51

sampling it at 2.495GS/s. When plotting both input and output waveforms in the time domain assuming

2.5GS/s sampling, relative frequency drift manifests itself as time expansion; the output waveform may

lead the input waveform at an early point in time and then lag the input waveform at a later point.

Figure 4.7 illustrates the effects of relative frequency drift in the time domain.

Figure 4.7: Time Domain Effects of Relative Frequency Drift Between ADC and DAC

Figure 4.8: DPD Test Bed with ADC and DAC Locked to the Same Clock

Relative frequency drift between DAC and ADC can be remedied by using one oscillator for both. The

solution is further simplified because both ADC and DAC require a 2.5GHz clock source. The AD9625 ADC

board was modified to provide an additional output route from the on-board Crystek VCO to an SMA

output. The AD9739A DAC board was modified to receive an external clock source from an SMA input.

Therefore, the Crystek VCO on the ADC board is the clock source for both the ADC and the DAC. The

arrangement is given in Figure 4.8 and the required board modifications are described in Appendix C.

With this test bed configuration, frequency drift does not impair DPD model training.

Time

Input Signal

ClockTo PA

From PA


52

4.6 FPGA Implementation Details

The ML605 FPGA Development Kit from Xilinx connects the AD9739A DAC evaluation board to the PC.

Pass-band OFDM waveforms generated in Matlab can be downloaded to the off-chip DDR Memory on

the FPGA development kit using Telnet. A Telnet server is started on the FPGA board and a Telnet

connection can be initiated using Matlab. A Matlab script (provided in Appendix A) is used to transfer

the generated OFDM waveform as 16-bit samples to the FPGA using a network cable. Once downloaded,

the FPGA transfers the samples from DDR Memory to the AD9739 DAC evaluation board. The overall

FPGA system architecture is shown in Figure 4.9 and relevant modules are described in sections 4.6.1 to

4.6.4.

Figure 4.9: FPGA System Architecture

4.6.1 AD9739A DAC Evaluation Board

The AD9739A DAC evaluation board RF output is a single-channel output at 2.5GS/s. It has two input

data ports and expects two 14 bit samples at 1.25GS/s. This can be accomplished with a 625MHz clock

running at double data rate. So, the input DAC clock of 2.5GHz is converted to a 625MHz clock and sent

to the FPGA to use for data transmission timing. The FMC connector permits Serial Peripheral Interface

(SPI) and Low Voltage Differential Signalling (LVDS) for communication between the DAC evaluation

board and the SPI and DAC Interface modules on the FPGA.


53

4.6.2 Serial Peripheral Interface Module

The SPI module is an instantiation of the SPI IP Core from Xilinx. This core provides a serial interface to

SPI devices such as the AD9739A DAC evaluation board, enabling configuring of the DAC registers. It is

designed to interface with the AXI Lite bus as a 32 bit slave [71].

4.6.3 DAC Interface Module

The DAC Interface module provides the DAC evaluation board with two 14-bit samples at 1.25GS/s from

a 625MHz double data rate clock. It includes a 3Mbit FIFO capable of storing 196608 16-bit samples and

an LVDS interface. It reads 12 16-bit samples at 208MHz and converts it to two 14-bit samples at

1.25GHz using 3:1 SERDES and double data rate. The 3Mbit FIFO is populated by the Video Direct

Memory Access (VDMA) module.

4.6.4 Video Direct Memory Access Module

The VDMA module is an instantiation of the VDMA IP core from Xilinx [72]. It provides high bandwidth

direct memory access between off-chip DDR memory and a target peripheral, in this case the DAC

interface. Data is streamed via the AXI bus using the AXI4-Stream Video Protocol [72]. VDMA

initialization and management registers are accessed using the AXI Lite bus as a slave interface [72]. A

configurable asynchronous line buffer circumvents frequency differences on the memory and streaming

side interfaces.

4.7 Summary

In summary, the AD9625 ADC evaluation board and the AD9739A DAC evaluation board from Analog

Devices are chosen as the ADC and DAC in the DPD test bed. The performance of both is evaluated and

found to meet DPD specifications. Due to clock jitter requirements and clock drift, both ADC and DAC

use the same 2.5GHz VCO from Crystek as the clock source. The FPGA implementation of the DAC

interface enables its use as an arbitrary waveform generator capable of generating 14 bit 196608

sample long waveforms at 2.5GS/s.

A High-performance PA Case Study: Measured Results

54

5 A High-performance PA Case Study: Measured

Results

5.1 Introduction

MxL235 is a class AB biased upstream PA designed by Maxlinear for use in DOCSIS 3.1 gateways [73].

The PA supports upstream frequencies up to 204MHz and can deliver up to 69dBmV of combined output

power to a 75Ω load across any combination of OFDM upstream channels using a single 3.3V supply

[73].

The driver software on the PA evaluation board has been modified to support three bias settings where

higher bias settings consume more power but have better linearity performance. At the highest biasest

setting (Bias 2), the PA draws approximately 1A of current, consuming 3.3W. At the lowest Bias setting

(Bias 0), the PA draws about 700mA, consuming 2.3W. Hence, this 1W difference is the maximum

allowed power a proposed DPD system can consume. The objective of this chapter is to design a DPD

system for the PA at Bias 0 that consumes less than 1W of power but matches the performance of the

PA at Bias 2. So, the tandem connection of the DPD system and the PA operating at Bias 0 should

consume less power than and perform similarly to the PA operating at Bias 2.

The PA’s nonlinear behaviour is introduced and analyzed in sections 5.2 and 5.3. In section 5.4, a DPD

model, architecture and training scheme is proposed for DOCSIS 3.1 upstream applications. Section 5.5

presents measured predistortion results using the proposed scheme under various temperature, process

and signal conditions. The power and area costs of the proposed DPD scheme is estimated in section

5.6.


55

5.2 Power Amplifier Characterization

5.2.1 Fundamental Frequency Response

A PA’s gain and phase variations while operating in its linear region is referred to as the PA’s

fundamental response. To measure the fundamental response of MxL235 at Bias 0, the PA was tested

with a wideband OFDM signal (5MHz to 200MHz) with 12dB PAPR) at a backoff of 24dB from Psat. The

test signal was generated with the AD9739A 14-bit 2.5GS/s DAC described in section 4.4. The PA output

was measured using the AD9625 12-bit 2.5GS/s ADC described in section 4.3.

The gain and phase variation of MxL235 across the frequency range of interest is larger than the

variations observed in simulation; the measured gain and phase varies more than 1dB and 0.2 radians,

respectively. This non-constant fundamental response is indicative of linear memory in the PA.

5.2.2 Harmonics

The harmonics generated by a PA under single-tone tests offers insight into the nonlinearity order of the

PA. The MxL235 PA at Bias 0 is tested with single tones at 69dBmV output RMS in the 5MHz to 200MHz

region. Tones are generated with an HP 8648C 9kHz-to-3200kHz RF synthesizer with an SFDR above

30dBc [74]. Low pass filters are used to ensure that the harmonics of the signal generator are above

60dBc. Harmonics generated by the PA are measured with an HP 8561E 6.5GHz Spectrum Analyzer,

which has an SFDR and IM3 above 82dBc [75]. The presence of HD2 in the measured results implies that

both even and odd order terms should be included in the DPD model in order to meet DOCSIS 3.1

specifications and match the performance of the PA at Bias 2.

Two tone tests are ubiquitous in DPD studies concerning PA memory. Two HP 8648C 9kHz-3200kHz

signal generators and a ZFSC-2-1W+ combiner from Mini-Circuits [76] are used to generate two tone

signals in the 5MHz to 200MHz frequency range at 69dBmV output RMS [74]. Low pass filters at the

signal generator output are used to ensure that the intermodulation products of the generators are

above 60dBc. IMD products generated by the PA are measured with an HP 8561 6.5GHz Spectrum

Analyzer [75].

Measured IM2 as a function of center frequency with varying tone spacing is presented in Figure 5.1.

Measured points are labelled with the frequencies of the two tones used. Similarly, measured IM3 as a


56

function of center frequency with varying tone spacing is given is presented in Figure 5.2. Points are

labelled with two tone frequencies. All reported IM2 and IM3 are given relative to the measured left IM2

and IM3 sideband at the lowest center frequency.

Figure 5.1: Measured IM2 vs. Center Frequency of MxL235 at Bias 0 with Varying Tone Spacing and at

69dBmV output RMS

Figure 5.2: Measured IM3 vs. Center Frequency of MxL235 at Bias 0 with Varying Tone Spacing and at

69dBmV output RMS

Measured IM2 and IM3 demonstrate dependence on two-tone frequency separation. In addition,

asymmetry is observed in the upper and lower sideband distortion products for both second-order and

third-order intermodulation products. Both of these effects are attributed to nonlinear memory effects

in the PA. Furthermore, this nonlinear memory must be captured and corrected by the DPD model in

order to meet DOCSIS 3.1 specifications. Therefore, the DPD model must have a memory order larger

than 1 for the second-order and third-order nonlinearities.

5.2.3 P1dB and Psat

Figure 5.3 presents the P1dB and Psat of the MxL235 PA at Bias 0 at various frequencies in the DOCSIS 3.1

upstream range. An HP8648C signal generator is used to synthesize tones in the 5MHz to 200MHz region

at increasing power levels [74]. The output power of the PA is measured with an HP 8561E spectrum

analyzer [75]. Psat is defined as the output power at which the PA gain is 3dB below nominal gain.

10 20 30 40 50 60 70 80 90 100 110-5

0

5

10

15

20

25

(10, 16)

(10, 42)

(10, 68)

(10, 94)

(10,120)

(10,146)

(10,172)

(10,198)

(10, 16)

(10, 42)

(10, 68)

(10, 94)

(10,120)

(10,146)

(10,172)

(10,198)

Measured IM2

Rela

tive IM

2(d

Bc)

Frequency (MHz)

f2-f1

f2+f1

105 110 115 120 125 130 135 140 145 150-20

-15

-10

-5

0

5

10

(101,117)

(101,133)

(101,149)

(101,165)

(101,181)

(101,197)

(101,117)

(101,133)

(101,149) (101,165) (101,181)

(101,197)

Measured IM3

Rela

tive IM

3(d

Bc)

Frequency (MHz)

2f1-f2

2f2-f1


57

Figure 5.3: P1dB and Psat relative to P1dB and Psat at 5MHz of MxL235 at Bias 0 Vs. Frequency

Both P1dB and Psat decrease by 4dB over the DOCSIS 3.1 upstream transmit frequency range. This explains

the observed increase in IM3 with center frequency in Figure 5.2. At the same input power level, signals

at high frequencies are operating more in the compression region than signals at lower frequencies.

Therefore, signals with high frequency content induce more nonlinearities in the PA output spectrum.

5.3 AM-AM and AM-PM Effects

DOCSIS 3.1 upstream frequency range is 5MHz to 204MHz and the output power specification is

65dBmV. However, MxL235 is rated to deliver up to 69dBmV of output power. To identify the individual

contributions from high power and large bandwidth to the DPD strategy, the bandwidth and output

power capabilities of the PA cannot be exercised simultaneously. Therefore, two distinct test sets are

explored to evaluate predistortion performance:

Test Set #1: Limited bandwidth (5MHz to 105MHz), maximum output power (69dBmV RMS

output)

Test Set #2: Full bandwidth (5MHz to 200MHz), limited output power (65dBmV RMS output)

Test Set #1 is investigated in sections 5.3.1 and 5.5.2. Test Set #2 is investigated in sections 5.3.2 and

5.5.3.

5.3.1 AM-AM, AM-PM and MER for 100MHz Bandwidth and 69dBmV Power

The AM-AM behaviour of the MxL235 PA at maximum output power (69dBmV) and Bias 0 is extracted

by testing the PA with a 100MHz wide OFDM signal with a PAPR of 13dB centered at 55MHz. The

0 20 40 60 80 100 120 140 160 180 200-4.5

-4

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

0

P1dB and Psat

Ou

tpu

t P

ow

er(

dB

c)

Frequency (MHz)

P1dB

Psat


58

AD9739A DAC described in section 4.4 is used for OFDM signal generation. The AD9625 ADC described

in section 4.3 is used to measure the PA output.

Similar to the AM-AM behaviour of the simulated PA given in Figure 3.3, slight gain compression is

evident at high input amplitudes implying a weakly nonlinear PA. The MxL235 PA exhibits more AM-AM

dispersion than the simulated PA. Similar to the simulated PA, MxL235 does not exhibit significant AM-

PM effects.

Figure 5.4 depicts the output constellation after demodulation of the 100MHz wide OFDM signal at

69dBmV output RMS with 100 subcarriers, each subcarrier with 16 QAM modulations. MER is calculated

as:

[∑| |

| |

] (5.1)

Where Yi is the ith output constellation point and Xi is the ith input constellation point. The MER of the

MxL235 PA at Bias 0 under the given signal conditions is calculated to be -38.6dB. DOCSIS 3.1

specifications require the MER to be -44dB.

Figure 5.4: Output Constellation of MxL235 with 100MHz Bandwidth, 55MHz Center

Frequency OFDM Signal at 69dBmV output RMS

-3.03 -3.02 -3.01 -3 -2.99 -2.98 -2.97 -2.96 -2.952.92

2.94

2.96

2.98

3

3.02

3.04

3.06

3.08

Input and Output Constellation

Imag

inary

Real

Output

Input

-4 -3 -2 -1 0 1 2 3 4-4

-3

-2

-1

0

1

2

3

4


Imag

inary

Real

MER = -38.5648dB

Output

Input


59

5.3.2 AM-AM, AM-PM and MER for 195MHz Bandwidth and 65dBmV Output

Power

The AM-AM behaviour of the MxL235 PA at Bias 0 with full bandwidth (200MHz) and limited output

power (65dBmV) is extracted by testing the PA with a 195MHz wide OFDM signal with a PAPR of 13dB

centered at 102.5MHz. The AD9739A DAC described in section 4.4 is used for OFDM signal generation.

The AD9625 ADC described in section 4.3 is used to measure PA output. Gain compression is not

noticeable since the PA is essentially operating at a 4dB backoff compared to the 69dBmV output power

case. However, dispersion of the AM-AM points is more significant, implying that a wider bandwidth

begets more significant memory effects. Similar to the simulated PA, MxL235 does not exhibit significant

AM-PM effects.

After downconversion, the MER of the OFDM signal is calculated to be -33.5dB, which is 3dB lower than

the MER for the 100MHz bandwith case, as shown in Figure 5.5. Therefore, a wider bandwidth produces

more memory effect which hinders demodulation.

Figure 5.5: Output Constellation of MxL235 with 195MHz Bandwidth, 102.5MHz Center Frequency OFDM Signal at

65dBmV output RMS

5.4 DPD Model Selection

The DPD test bed set up is presented in Figure 5.6. It should be noted that the balun at the output of the

MxL235 PA severely attenuates frequencies above 250MHz.

-4 -3 -2 -1 0 1 2 3 4-4

-3

-2

-1

0

1

2

3

4


Imag

inary

Real

MER = -33.5248dB

Output

Input


60

Figure 5.6: DPD Test Bed Set Up

5.4.1 DPD Model Constraint and Considerations

A power budget of 1W limits both the DPD model selection and DPD architecture choices. Simpler DPD

models provide more significant power savings because of fewer hardware requirements. Models with

minimal linearity order and minimal memory order give way to a minimal number of coefficients. A

Lower number of coefficients translates to fewer multiplications and additions required per sample.

Similarly, static DPD systems are power savvy by omitting the observation path with the power hungry

ADC altogether. However, static DPD systems assume little temperature and board-to-board variations.

Static DPD systems are generally not tolerant to process or temperature variations. These limitations are

overcome by using factory calibration and temperature compensated DPD schemes. Factory calibration

refers to the offline training of DPD coefficients for each board produced. So, each board has the same

DPD model structure but different coefficients customized for its operation. Similarily, temperature

compensated DPD schemes can improve the DPD systems resilience to temperature fluctuations

without incurring significant power costs. In fact, simulation results suggest that a temperature

compensated static DPD system would be better suited for the predicted temperature variations in the

upstream chain (0°C to 130°C).


61

The proposed temperature compensated static DPD scheme employs a DPD model and a bank of DPD

coefficients indexed by temperature. The system monitors the ambient temperature and when a change

is detected, the coefficients trained at that temperature are swapped in. Fortunately, the upstream

chain already houses a temperature sensor accurate to ±5°C. Therefore, a simple temperature

compensated static DPD scheme is feasible given that the DPD coefficients are not sensitive to

temperature measurement errors of 10°C. Furthermore, the number of temperature coefficient sets

should be minimized to reduce hardware costs.

In summary, a DPD model for the MxL235 PA is subjected to the following constraints and

considerations:

1. The power consumption of the DPD system must be less than 1W.

2. DPD model complexity should be minimized.

3. The DPD scheme must be static.

4. DPD coefficients must not be sensitive to temperature measurement errors of 10°C.

5. The number of temperature coefficient sets should be minimized.

5.4.2 Impact of Severe Linear Memory Effect

Following a similar procedure to that outlined in section 3.6, the orthogonal memory polynomial model

with sparse delay taps of order 5 (R=5) is chosen as the DPD model. However, the linear memory effect

of the PA requires a large number of first-order taps to correct, rendering the orthogonal memory

polynomial unfeasible. For example, the post-distortion and residual error signals when modelling the

MxL235 with an orthogonal memory polynomial with N1=1, N2=2, N3=3, N5=1 (total of 14 coefficients) is

given in Figure 5.7. The results are dismal; the post-distortion signal does not predict any distortion

suppression. In fact, the MSE of the model is 22.7dB and the in-band error is the largest contributor to

MSE degradation. As shown in Figure 5.8, the in-band error and MSE improves to 44dB by increasing N1

to 42 taps for a total of 96 coefficients. This implies that the first-order response of the PA or the linear

memory effect of the PA disrupts the LS coefficient estimation process.


62

Figure 5.7: Power Spectral Density of PA Output, Post-Distortion and Residual Error when Modelling with Orthogonal Memory Polynomial with N1=1, N2=2,

N3=3, N5=1 and R=5 (MSE = 22.7dB)

Figure 5.8: Power Spectral Density of PA Output, Post-Distortion and Residual Error when Modelling with Orthogonal Memory Polynomial with N1=42, N2=2,

N3=3, N5=1 and R= 5 (MSE = 44.5dB)

The presence of severe linear memory effect is evident from the fundamental gain and phase response

which is discussed in Section 5.2.1. In deriving the fundamental gain and phase response, it in inherently

assumed that the nonlinear behaviour of the PA is bypassed by operating at a large backoff from P1dB.

Therefore, the measured fundamental response is the first order response of the PA in linear operation

and can be described by an LTI filter. From Figures 5.7 and 5.8, it is clear that this fundamental response

is present even when the PA is in nonlinear operation. A fundamental response which varies significantly

over the bandwidth of operation is more common for larger bandwidths and requires a large number of

filter taps to model.

Traditionally, large linear memory effects require a large number of fundamental coefficients to achieve

distortion suppression. Unfortunately, a DPD model with 96 coefficients is simply unreasonable for the

given power constraints. Furthermore, correcting the fundamental channel response of the PA is not the

job of a DPD system; it is the job of the receiver in the CMTS. In fact, linear memory effects do not

produce distortion per se, they simply impair DPD coefficient estimation.

5.4.3 Modified DPD Training Scheme

Figure 5.9 presents a PA model consistent with the observed linear memory effects: a memory

polynomial followed by an LTI filter. The effects of the LTI filter must be removed from the coefficient

estimation process in order to reduce the number of fundamental coefficients. Similar to training

schemes proposed by Braithwaite, Bondar and Budimar [45-47], a pseudo-inverse of the LTI filter, called

an equalization filter, may be used to remove the effects of the LTI filter from the coefficient estimation

process. The proposed DPD training scheme is presented in Figure 5.10. The equalization filter is

0 0.5 1 1.5 2

x 108

-110

-100

-90

-80

-70

-60

Power Spectral DensityP

ow

er/

Fre

qu

en

cy(d

Bm

/Hz)

Frequency (Hz)

Output

Post-Distortion

Error

MSE:22.7109dB

0 0.5 1 1.5 2

x 108

-120

-110

-100

-90

-80

-70

-60


Po

wer/

Fre

qu

en

cy(d

Bm

/Hz)

Frequency (Hz)

Output

Post-Distortion

Error

MSE:44.5031dB


63

implemented in Matlab and only utilized during offline coefficient training, implying that filter

coefficients are floating point with no dynamic range issues and no hardware implications. The

equalization filter is not present in the upstream transmit chain; hence the proposed DPD training

scheme incurs no additional hardware costs.

Figure 5.9: Proposed PA Model

Figure 5.10: Proposed DPD Training Scheme

5.4.4 Designing Equalization Filter

An equalization filter is derived from the assumption that the contributions of the memory polynomial

in the PA model are negligible under low amplitude signal conditions. The MxL235 PA is tested with a

low amplitude OFDM (19dB backoff from Psat) and occupying the observation frequency range from

5MHz to 230MHz. The measured output is digitally low pass filtered with an equal ripple filter with

0.0001dB ripple in the pass band (from 5MHz to 230MHz) and 100dB attenuation in the stop band

(>250MHz). Input and output are normalized to 1Vrms and time aligned. LS is employed to solve for the

linear coefficients:

*

+

[ ]

[

( ) ( )

( ) ( )

]

(5.2)

( ) (5.3)

Memory Polynomial

LTI

PA

Memory Polynomial

LTI

PA

Equalizer:LTI-1

LS

DPD:Memory

Polynomial


64

The resulting 120 tap FIR filter is the linear equalizing filter for the PA. The frequency response of this

equalizing filter is shown in Figure 5.11. The gain and phase response of the equalizing filter is the

opposite of the gain and phase of the PA measured in section 5.2.1.

Figure 5.11: Frequency Response of the Equalizing Filter for MxL235 at 19dB backoff from Psat

Figure 5.12: Frequency Response of PA and Equalizing Filter for MxL235 at 19dB backoff from Psat

The frequency response of the PA and equalizing filter cascade for a low amplitude OFDM signal is

presented in Figure 5.12. In comparison to the measured PA response given in section 5.2.1, the

response of the PA and equalizing filter cascade shows far less gain and phase variation over the DOCSIS

3.1 upstream transmit frequencies. The gain and phase of the cascade fluctuates by 0.04dB and 0.06

radians, respectively. Without the equalizing filter, the gain and phase of the PA fluctuated by 1.5dB and

0.3 radians, respectively.

5.4.5 Results with Proposed DPD Training Scheme

Figure 5.13: Power Spectral Density of PA Output, and Residual Error when Modelling with Orthogonal Memory Polynomial with N1=(1,5,10,20), N2=2, N3=3, N5=1, and R= 5 (MSE = 44.1dB, 46dB, 48dB and 49dB) and Training

with Proposed Equalization Training Scheme

0 20 40 60 80 100 120 140 160 180 200-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8Equalizer Gain and Phase

No

rmalized

Gain

(d

B)

0 20 40 60 80 100 120 140 160 180 200-0.35

-0.3

-0.25

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

Ph

ase (

rad

)

Frequency (MHz)

Phase

Gain

0 20 40 60 80 100 120 140 160 180 200-0.02

-0.015

-0.01

-0.005

0

0.005

0.01

0.015

0.02Cascaded PA and Equalizer Gain and Phase

No

rmalized

Gain

(d

B)

0 20 40 60 80 100 120 140 160 180 200-5

0

5x 10

-4

Ph

ase (

rad

)

Frequency (MHz)

Phase

Gain

0.5 1 1.5 2

x 108

-120

-110

-100

-90

-80

-70

-60


Po

wer/

Fre

qu

en

cy(d

Bm

/Hz)

Frequency (Hz)

Output

Error: N1=1 (MSE=44dB)





65

Figure 5.13 illustrates the post-distortion and residual error signal when modelling with the same DPD

model structure and signal attempted in Figure 5.7 (Orthogonal Memory Polynomial with N1=1, N2=2,

N3=3, N5=1, sparse delay taps of order 5 (R=5), OFDM signal with 100MHz bandwidth and 69dBmV

output power) but using the proposed DPD training scheme. Keeping signal conditions and DPD model

structure the same, the MSE is improved from 22.7dB to 44.1dB simply by training the DPD model with

an equalized output signal as the observation signal. The number of fundamental coefficients is reduced

from 84 to 2 while maintaining DPD performance and incurring no additional power costs. Figure 5.13

also demonstrates how the MSE may be improved further by increasing the number of taps at the

expense of DPD complexity. The maximum attainable MSE is limited by the SINAD of the system.

Figure 5.14 depicts the output constellation of the signal presented in Figure 5.4 after equalization. With

equalization, the computed MER improves by 5dB to -43dB. This confirms that the fundamental channel

response of the PA is the largest contributor to residual error.


66

Figure 5.14: Output Constellation of MxL235 with 100MHz Bandwidth, 55MHz

Center Frequency OFDM Signal at 69dBmV output RMS after Equalization (MER=-43.1dB)

5.5 Measured Predistortion Results

5.5.1 Test Procedure

The predistortion test procedure assumes an equalization filter has already been determined. The test

procedure is subdivided into two phases: the DPD training phase and the predistortion test phase.

5.5.1.1 Training Phase

Figure 5.15 illustrates the training phase of the DPD system. An OFDM signal is generated in Matlab and

2.5GS/s and downloaded to the AD9739A waveform generator described in section 4.4. The OFDM

signal (X(n)) is applied to the MxL235 PA at 69dBmV output RMS in Test Set #1 and 65dBmV output RMS

in Test Set #2. The PA output (Y(n)) is measured using the 2.5GS/s AD9625 digitizer described in section

4.3, then digitally low-pass filtered with an equal-ripple filter with 0.0001dB ripple in the 230MHz pass

band and 100dB attenuation in the stop band (>250MHz). Finally, the equalizing filter derived in section

5.4.3 is applied to the processed output. Both input X(n) and equalized output Yeq(n) are normalized to

an RMS of 1 and time aligned. The orthogonal memory polynomial with sparse delay taps of order 5

(R=5) is used as the DPD model. DPD coefficients are solved using a LS fit and quantized to 12 bits.

-3.06 -3.05 -3.04 -3.03 -3.02 -3.01 -3 -2.99 -2.98 -2.972.92

2.94

2.96

2.98

3

3.02

3.04

3.06

3.08


Imag

inary

Real

Output

Input

-4 -3 -2 -1 0 1 2 3 4-4

-3

-2

-1

0

1

2

3

4


Imag

inary

Real

MER = -43.1899dB

Output

Input


67

Figure 5.15: Training Phase of DPD Test Procedure

Figure 5.16: Test Phase of DPD Test Procedure

5.5.1.2 Test Phase

Figure 5.16 illustrates the test phase of the DPD test procedure. After the DPD model and coefficients

are fixed, the DPD model is applied to new OFDM signals x(n) to produce a predistorted input signal

(XDPD(n)) in Matlab. The predistorted input signal is downloaded to the AD9739A waveform generator

and applied to the MxL235 PA. The resulting predistorted output signal (YDPD(n)) is measured using the

AD9625 digitizer.

Worst in-band distortion, worst out-of-band distortion and notch ACLR metrics verify whether

predistortion results meet the DOCSIS 3.1 specification. Worst in-band distortion is measured as the

ratio of the signal power at center frequency to the largest distortion power in the 5MHz to 204MHz

frequency range. The signal power is measured in a 4MHz bandwidth centered at the signal center

frequency and the largest in-band distortion is measured in a 4MHz bandwidth (BW) centered at the

largest distortion at least 2.25MHz away from the signal band edge. DOCSIS 3.1 specifications require in-

band distortion levels to be above 45dBc. Similarly, worst out-of-band distortion is measured as the

ratio of the signal power at center frequency to the largest distortion power in the 204MHz to 258MHz

frequency range. The signal power is measured in a 4MHz bandwidth centered at the signal center

frequency and the largest out-of-band distortion is measured in a 4MHz bandwidth centered at the

largest distortion region outside of the 204MHz transition point. DOCSIS 3.1 specifications require out-

of-band distortion levels to be above 50dBc. If applicable, notch ACLR is the ratio of the signal power to

the distortion measured in a 2MHz bandwidth at the center of the frequency notch. In-band suppression

is the difference between the worst in-band distortion in the predistortion signal and the original output

at Bias 0. Out-of-band suppression is the difference between worst out-of-band distortion in the

predistortion signal and the original output at Bias 0.

1/rms(Yeq(n))

PAEqualizer:

LTI-1

Y(n)

LS

1/rms(X(n))PA

YDPD(n)DPD: Memory Polynomial


68

5.5.2 Predistortion Results for 100MHz Bandwidth 69dBmV Test Set

This section evaluates predistortion performance for Test Set #1 under varying signal conditions,

temperatures and boards. Test signals are restricted to the 5MHz to 105MHz frequencies and 69dBmV

output RMS. For this test set, the orthogonal memory polynomial model with N1=1, N2=2, N3=5 and N5=1

is chosen as the DPD model. The training signal is an OFDM signal with a bandwidth of 100MHz, center

frequency of 55MHz, PAPR of 13dB and at 69dBmV output RMS.

5.5.2.1 Results for Various Center Frequencies and Bandwidths

Table 5.1 presents measured PA output for the MxL235 PA at Bias 2, Bias 0 and Bias 0 with predistortion

at room temperature. Test signals vary in bandwidth (BW) and center frequency (Fc). The PAPR of the

test signal range from 12dB to 14dB and Ibias refers to the current consumed by the PA. The MxL235 PA

at Bias 2 consumes about 300mA more current, which translates to 1W, than the PA at Bias 0. However,

with predistortion, the PA at Bias 0 saves 1W of power but still meets both the DOCSIS 3.1 mask and the

performance of the PA at Bias 2.

Table 5.1: Measured Results for MxL235 PA at Bias 2, Bias 0 and Bias 0 with Predistortion at Room Temperature

Signal Type Bias 2 Bias 0 Bias 0 + Predistortion

BW

(MHz)

Fc

(MHz)

Worst

In-

Band

(dBc)

Worst

In-

Band

Freq.

(MHz)

Worst

Out-Of-

Band

(dBc)

Worst

Out-Of-

Band

Freq.

(MHz)

Worst

In-

Band

(dBc)

Worst

In-

Band

Freq.

(MHz)

Worst

Out-Of-

Band

(dBc)

Worst

Out-Of-

Band

Freq.

(MHz)

Worst

In-

Band

(dBc)

Worst

In-

Band

Freq.

Worst

Out-Of-

Band

(dBc)

Worst

Out-Of-

Band

Freq.

(MHz)

24

17 54.7 37 68.1 207 51.7 36 67.2 205 57.2 49 69.6 208

55 50.8 162 64.3 206 44.8 159 66.4 207 50.1 157 65.8 205

93 54.9 112 62.0 205 48 111 57.5 204 51.7 115 65 205

100 55 48.5 155 52.5 205 41.6 162 49 205 48.6 132 57 205

48 29 & 81

49.2 157

53.7 206

41.6 153

49.5 206

49 110

56 205 Notch

ACLR=51

Notch

ACLR=47.4

Notch

ACLR=51.1

5.5.2.2 MER with DPD

Figure 5.17 depicts the output constellation of the signal presented in Figure 5.4 with DPD and

equalization. With DPD, the computed MER improves by an additional 2dB to -45dB, which meets

DOCSIS 3.1 specifications. Hence, equalization improves MER by 5dB and DPD improves MER by 2dB.

This is expected because out-of-band errors are filtered in the demodulation process, so MER only


69

accounts for in-band errors. Therefore, the largest in-band errors are a result of the PAs fundamental

response.

Figure 5.17: Output Constellation of MxL235 with 100MHz Bandwidth, 55MHz Center Frequency OFDM Signal with DPD at 69dBmV output RMS after Equalization (MER=-45.3dB)

5.5.2.3 Predistortion Results with Temperature Variations

The resilience of the MxL235 DPD system to temperature variations is tested using a TestEquity 115A-F

temperature chamber [77]. The chamber has a temperature range of -73°C to 175°C with a control

tolerance of ±0.2°C [77]. The MxL235 PA is placed inside the temperature chamber and connected to the

AD9739A DAC and AD9625 ADC outside of the chamber. The training signal is applied to the PA at five

ambient temperature points: -18°C, 2°C, 27°C, 52°C and 72°C. Table 5.2 presents the PAs junction

temperature at Bias 2 and Bias 0 for the five ambient temperature points. It should be noted that given

an ambient temperature, the PA at Bias 2 has a junction temperature that is 15°C higher than the

junction temperature for the PA at Bias 0. This is an added benefit of the lower bias setting.

Table 5.2: MxL235 Junction Temperature at Bias 2 and Bias 0 for 5 Ambient Temperature Points

Ambient

Temperature

-18°C 2°C 27°C 52°C 72°C

Bias 2 Junction

Temperature

28°C 49°C 73°C 99°C 119°C

Bias 0 Junction

Temperature

12.4°C 34.4°C 57°C 86°C 105°C

-3.06 -3.05 -3.04 -3.03 -3.02 -3.01 -3 -2.99 -2.982.92

2.94

2.96

2.98

3

3.02

3.04

3.06

3.08


Imag

inary

Real

Output

Input

-4 -3 -2 -1 0 1 2 3 4-4

-3

-2

-1

0

1

2

3

4


Imag

inary

Real

MER = -45.3389dB

Output

Input


70

A new set of coefficients are trained at each temperature point. Then, each set of coefficients is applied

test signals at various temperatures to generate post-distortion results. The post-distortion results are

used to determine the number of entries in the bank of coefficient sets. For the MxL235 PA under Test

Set #1 conditions a total of three coefficient sets were determined:

Use coefficients trained at 2°C when the ambient temperature is less than 10°C

Use coefficients trained at 52°C when the ambient temperature is greater than 10°C and less

than 37°C

Use coefficients trained at 72°C when the ambient temperature is greater than 37°C

The MxL235 PA at Bias 0 is tested with various signal bandwidth and center frequencies at ambient

temperatures ranging from -18°C to 72°C. Table 5.3 presents a summary of the largest and smallest

suppression achieved across temperature with the temperature compensated predistortion scheme

described above for Test Set #1.

Table 5.3: Summary of Suppression Achieved Across Temperature with MxL235 at Bias 0 with the Temperature

Compensated Predistortion Scheme for Test Set #1

Signal Type Largest In band Suppression

(dB)

Smallest In band Suppression

(dB)

Largest Out of Band

Suppression (dB)

Smallest Out of Band

Suppression (dB)

BW=24, Fc=17 6.3 4.2 2.3 -1.2*

BW=24, Fc=55 5.3 3 1.2 -0.6*

BW=24, Fc=93 4.8 1.7 7.5 3.8

BW=100, Fc=55 7 4.9 8.2 4.2

BW=48, Fc=29, 81

7 5.9 9.1 5.7

Results indicate that the amount of in-band suppression achieved with the temperature compensated

DPD scheme for Test Set #1 varies from 1.7dB to 7dB. Similarly, the out-of-band suppression can range

from 1.2dB to 9.1dB. The cases marked with an asterisk are ignored because the distortion level is below

-65dBc, hence it is lower than the measurement accuracy of the AD9625 digitizer. Therefore, it can be

summarized that predistortion improves the distortion performance of the MxL235 PA at Bias 0.


71

Figure 5.18: Worst In-Band and Worst Out-Of-Band Distortion for 24MHz OFDM Signal at 93MHz Fc Across Temperature with MxL235 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test

Set #1

Figure 5.19: Worst In-Band, Worst Out-Of-Band and Notch ACLR for 48MHz OFDM Signal at Fc=29MHz and 81MHz Across Temperature with MxL235 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for

Test Set #1

Figure 5.18 depicts distortion results for a 24MHz OFDM signal at 93MHz with the temperature

compensated predistortion scheme for Test Set #1. Worst in-band and worst out-of-band distortion for

the MxL235 PA at Bias 2, Bias 0 and Bias 0 with predistortion is presented. Worst in-band distortion is

labelled with the center frequency of the worst in-band distortion region. Similarly Figure 5.19 presents

the worst in-band distortion, out-of-band distortion and notch ACLR measurements for a 96MHz OFDM

signal with a 4MHz notch at 55MHz. Additional measurement results under three other signal conditions

are given in Appendix B.1.

-20 -10 0 10 20 30 40 50 60 70 8045

50

55

60

65

70

75

9MHz 11MHz

11MHz

111MHz

78MHz

107MHz110MHz

111MHz 107MHz111MHz

108MHz109MHz 115MHz

109MHz 109MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)


Worst In Band bias2

Worst In Band bias0

Worst In Band predistorted

Worst Out of Band bias2


Worst Out of Band predistorted

-20 0 20 40 60 80 10040

42

44

46

48

50

52

54

56

58

60

117MHz

169MHz

157MHz

170MHz

109MHz

150MHz

153MHz

153MHz170MHz

153MHz

110MHz

109MHz

110MHz

159MHz147MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)

Worst In Band, Worst Out of Band and Notch for 48MHz at 29MHz and 81MHz

Worst In Band bias2

Worst In Band bias0





Notch bias2

Notch bias0

Notch predistorted


72

The performance of MxL235 at Bias 0 with the temperature compensated predistortion scheme is

similar to the performance at Bias 2; both meet DOCSIS 3.1 specifications. The PA at Bias 0 without

predistortion generally fails to meet DOCSIS 3.1 standards. Furthermore, the PA at Bias 0 with

predistortion is more resilient to temperature fluctuations than the PA at Bias 2. In summary, the PA at

Bias 0 with the temperature compensated predistortion scheme for Test Set #1 consumes less power

than the PA at Bias 2 while matching the performance of the PA at Bias 2.

5.5.2.4 Results with Process and Board Variations

The tolerance of the MxL235 temperature compensated DPD system for Test Set #1 to process

variations is tested using another MxL235 board. This board with be referred to as an MxL235-2.

Measurements of the MxL235-2 PA reveal that this part consumes approximately 40mA to 50mA less

current that the original MxL235 part for all biases and test signals. As a result, the MxL235-2 PA

generally has higher distortion levels than the MxL235 part for all bias settings.

Table 5.4: Measured Results for MxL235-2 PA at Bias 2, Bias 0 and Bias 0 with Predistortion Trained with MxL235 and MxL235-2 at Room Temperature

Signal Type

Bias 2 Bias 0

Bias 0 + Pre-distortion

Training with MxL235

Training with MxL235-2

BW Fc Worst In-

Band (dBc)

Worst Out-Band (dBc)

Worst In-Band (dBc)


Worst In-Band (dBc)


Worst In-Band (dBc)

Worst Out-Band

(dBc)

24

17 56.5 66.4 48.9 67.2 55 67.2 54.6 67.8

55 44.4 66.9 42.4** 63.6 46 66.5 47.6 66.1

93 42.6** 63.3 51.8 61.1 50.9 61.8 50.2 66.2

100 55 42.8** 49** 38.8** 46.2** 45 53.1 47.8 55.2

48 29 & 81

44 48.9** 39.2** 45.6** 44.3 53.5 47.9 56.4

Notch =46.6 Notch =44.5 Notch = 49.4 Notch = 51.8

Table 5.4 presents measured distortion results for the MxL235-2 PA at Bias 2, Bias 0 and Bias 0 with

predistortion at room temperature. The Bias 0 with predistortion case is further subdivided into two

cases: one where the DPD coefficients are trained using the original MxL235 part and one where the

coefficients are trained using the new MxL235-2 part. Test cases that fail to meet DOCSIS 3.1 standards

are marked with two asterisks.


73

Similar to the original MxL235, the MxL235-2 part at Bias 0 consumes approximately 300mA less current

than the PA at Bias 2 for a power saving of 1W. However, the MxL235-2 PA at Bias 2 and Bias 0 does not

meet DOCSIS 3.1 standards for all test cases whereas the PA with predistortion does meet specifications.

Regardless of whether the coefficients were trained with the original MxL235 part or the new MxL235-2

part, the performance of the MxL235-2 PA at Bias 0 with predistortion is superior to the performance of

the PA at Bias 2 and Bias 0. It should also be noted that training and testing the DPD model on the same

board results in better DPD performance than applying a DPD model derived from another part.

Therefore, DPD coefficients should be calibrated for each part for the best DPD performance.

Figure 5.20: Worst In-Band and Worst Out-Of-Band Distortion for 100MHz OFDM Signal at 55MHz Fc Across Temperature with MxL235-2 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test

Set #1 (Training with Original MxL235)

The tolerance of the MxL235 temperature compensated DPD system for Test Set #1 to process and

temperature variation is tested using the MxL235-2 part. First, the distortion levels of the MxL235-2 PA

at Bias 0 and Bias 2 is measured across temperature. Then, the MxL235-2 PA at Bias 0 is tested with the

temperature compensated DPD scheme derived in section 5.5.2.3 using the original MxL235 PA. Results

for a 100MHz OFDM signal at 55MHz center frequency is given in Figure 5.20. Measurements for

additional signal conditions are given in Appendix section B.2.

The MxL235-2 PA with the temperature compensated DPD scheme derived from MxL235 meets DOCSIS

3.1 standards. In fact, it generally performs better than the MxL235-2 PA at Bias 2. In summary,

temperature compensated DPD schemes may be used across different boards, although DPD coefficient

training for each board is preferred.

-20 -10 0 10 20 30 40 50 60 70 8038

40

42

44

46

48

50

52

54

56

58

60

168MHz162MHz 169MHz

157MHz

162MHz

160MHz 158MHz

154MHz158MHz

135MHz

160MHz152MHz 157MHz

157MHz 157MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)


Worst In Band bias2

Worst In Band bias0






74

5.5.3 Predistortion Results for 195MHz Bandwidth 65dBmV Test Set

This section evaluates predistortion performance for Test Set #2 under varying signal conditions,

temperatures and boards. Test signals are restricted to the 5MHz to 200MHz frequencies and 65dBmV

output RMS. For this test set, the orthogonal memory polynomial model with N1=1, N2=2, N3=7 and N5=1

is chosen as the DPD model. The training signal is an OFDM signal with a bandwidth of 195MHz, center

frequency of 102.5MHz, PAPR of 13dB and at 68dBmV output RMS.

5.5.3.1 Results for Various Center Frequencies and Bandwidths

Table 5.1 presents measured PA output for the MxL235 PA at Bias 2, Bias 0 and Bias 0 with predistortion

at room temperature. Test signals vary in bandwidth (BW) and center frequency (Fc). The PAPR of the

test signal range from 12dB to 14dB. The MxL235 PA at Bias 2 consumes about 300mA more current,

which translates to 1W, than the PA at Bias 0. However, with predistortion, the PA at Bias 0 saves 1W of

power but still meets both the DOCSIS 3.1 mask and the performance of the PA at Bias 2.

Table 5.5: Measured Results for MxL235 PA at Bias 2, Bias 0 and Bias 0 with Predistortion at Room Temperature

Signal

Type Bias 2 Bias 0 Bias 0 + Predistortion

BW

(MHz)

Fc

(MHz)

Worst

In-

Band

(dBc)

Worst

In-

Band

Freq.

(MHz)

Worst

Out-Of-

Band

(dBc)

Worst

Out-Of-

Band

Freq.

(MHz)

Worst

In-

Band

(dBc)

Worst

In-Band

Freq.

(MHz)

Worst

Out-Of-

Band

(dBc)

Worst

Out-Of-

Band

Freq.

(MHz)

Worst

In-Band

(dBc)

Worst

In-Band

Freq.

Worst

Out-Of-

Band

(dBc)

Worst

Out-

Of-

Band

Freq.

(MHz)

24

17 54.7 34 67 210 51.5 57 66.8 207 52.9 33 67 205

93 55.8 109 65.3 206 49.5 108 61.1 205 53.4 6.7 64.6 205

188 53.8 7.5 56 204 42.8 204 42.8 204 51.4 170 54.4 209

195 102.5 51.2 203 51.9 204 42.2 202 43.5 206 50.4 202 51.2 209

96

53

&

152

51.8 204

52.5 205

44.4 203

44.2 208

51 203

51.3 204 Notch

ACLR=51.2 Notch ACLR=46.8 Notch ACLR=51.4

5.5.3.2 Predistortion Results with Temperature Variations

The resilience of the MxL235 DPD system to temperature variations is tested using a TestEquity 115A-F

temperature chamber [77]. Similar to the procedure described in section 5.5.2.3, the training signal is

applied to the PA at five ambient temperature points: -18°C, 2°C, 27°C, 52°C and 72°C. A new set of


75

coefficients are trained at each temperature point. Then, each set of coefficients is applied to test

signals at various temperatures to generate post-distortion results. The post-distortion results are used

to determine the number of entries in the bank of coefficient sets. For the MxL235 PA under Test Set #2

conditions a total of two coefficient sets were determined:

Use coefficients trained at 2°C when the ambient temperature is less than 2°C

Use coefficients trained at 27°C when the ambient temperature is greater than 2°C

The MxL235 PA at Bias 0 is tested with various signal bandwidth and center frequencies at ambient

temperatures ranging from -18°C to 72°C. Table 5.6 presents a summary of the largest and smallest

suppression achieved across temperature with the temperature compensated predistortion scheme

described above for Test Set #2.

Table 5.6: Summary of Suppression Achieved Across Temperature with MxL235 at Bias 0 with the Temperature

Compensated Predistortion Scheme for Test Set #1

Signal Type Largest In-band Suppression

(dB)

Smallest In-band

Suppression (dB)

Largest Out-of-Band

Suppression (dB)

Smallest Out-of-Band

Suppression (dB)

BW=24, Fc=17 1.4 -0.4** 1.4 -1.9*

BW=24, Fc=93 5.7 1 6.2 2.9

BW=24, Fc=188 8.6 4.4 11.7 7.4

BW=195, Fc=102.5 8.3 5.7 7.7 5.3

BW=96, Fc=53, 152

7.7 5.6 7.5 5.7

Results indicate that the amount of in-band suppression achieved with the temperature compensated

DPD scheme for Test Set #2 varies from -0.4dB to 8.6dB. Similarly, the out-of-band suppression can

range from 1.4dB to 11.7dB. The case marked with a single asterisk is ignored because the distortion

level is below -65dBc, hence it is lower than the measurement accuracy of the AD9625 digitizer.

The case marked with two asterisks occurs when the test signal is a narrow-band low-frequency OFDM

signal. Similar to post-distortion results observed in simulation (section 3.6.2), DPD suppresses distortion

and improves PA linearity in the more demanding cases (high frequency and large bandwidth) at the

cost of slightly degrading PA performance when the linearity is already exceptional (narrow-band, low-


76

frequency). For example, Figure 5.21 depicts distortion results for a 24MHz OFDM signal at 17MHz with

the temperature compensated predistortion scheme for Test Set #2. Figure 5.22 depicts distortion

results for the more demanding 195MHz OFDM signal at 102.5MHz center frequency case.

Measurements for additional signal conditions are given in Appendix section B.3. For the narrow-band

low-frequency signal condition, the performance of the PA without predistortion is better than the

performance with predistortion at some temperatures. However, the measured distortion results

exceed the DOCSIS 3.1 standard (in-band distortion >44dBc, out-of-band distortion>50dBc) and this

performance trade-off is acceptable.

A possible explanation for the performance trade-off is given in section 5.2.2 and 5.2.3. IM3 and Psat

measurements suggest signals with high frequency content induce more nonlinearities in the PA output

spectrum. This means that the residual error is larger at the higher frequencies when training with a

wideband OFDM signal. The LS estimation will attempt to correct for the higher frequencies more than

the lower frequencies. Since higher frequencies and larger bandwidths are the more demanding cases,

the amount of suppression achieved at lower frequencies can be sacrificed.

In summary, predistortion improves the linearity performance of the MxL235 PA where it is most

needed: at higher frequencies. The PA at Bias 0 with the temperature compensated DPD scheme for

Test Set #2 performs comparably to the PA at Bias 2. Therefore, a temperature compensated DPD

scheme may be used to improve PA performance to DOCSIS 3.1 standards while consuming less power.


77

Figure 5.21: Worst In-Band and Worst Out-Of-Band Distortion for 24MHz OFDM Signal at 17MHz Fc Across Temperature with MxL235 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test

Set #2

Figure 5.22: Worst In-Band and Worst Out-Of-Band Distortion for 195MHz OFDM Signal at 102.5MHz Fc Across Temperature with MxL235 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test

Set #2

-20 -10 0 10 20 30 40 50 60 70 8050

52

54

56

58

60

62

64

66

68

70

35MHz 37MHz34MHz

37MHz

37MHz

57MHz 58MHz

57MHz 45MHz

56MHz

33MHz

34MHz

33MHz

34MHz32MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)


Worst In Band bias2

Worst In Band bias0





-20 -10 0 10 20 30 40 50 60 70 8042

43

44

45

46

47

48

49

50

51

52

203MHz

204MHz

203MHz

203MHz

203MHz

202MHz203MHz

202MHz203MHz

202MHz

204MHz

202MHz202MHz

203MHz

202MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)

Worst In Band and Worst Out of Band for 195MHz at 102.5MHz

Worst In Band bias2

Worst In Band bias0






78

5.6 Power and Area Estimates

Both test sets employ the orthogonal memory polynomial DPD structure shown in Figure 5.23. The

hardware implementation of the DPD model entails some adders and multipliers. The measured power

and area consumption for 12 bit arithmetic logic units (ALUs) per Gop/s in 28nm CMOS and 1V supply is

given in Table 5.7. However, since the memory order of the LTI filters is different for the two test sets,

the power and area consumption of the DPD model is different for each test set. The power and area

cost of the DPD scheme employed in Test Set #1 is presented in section 5.6.1. The power and are cost of

the DPD scheme employed in Test Set #2 is presented in section 5.6.2.

Figure 5.23: Implementation of Orthogonal Memory Polynomial DPD Model

Table 5.7: Power and Area Cost of Common Arithmetic Logic Units in 28nm

Power

mW/(Gop/s) Area

mm2/(Gop/s)

Adder(12 bits) 0.378 0.001

Const Multiplier (12 bits) 0.936 0.006

Full Multiplier(12 bits) 2.028 0.01

Output Stage

FiltersOrthogonalPower of P

H1(n)

H2(n)

H3(n)

H5(n)

(.)2

XDPD(n)

-3

15-10

-1

X(n)


79

5.6.1 Power and Area Estimates for 100MHz Bandwidth 69dBmV Case

The DPD model for Test Set #1 utilizes a total of 18 coefficients (N1=1, N2=2, N3=5 and N5=1). A

breakdown of the power and area cost contributions is presented in Table 5.8. The power and area cost

of the DPD model for Test Set#1 is estimated to be 83.3mW and 0.44mm2.

Table 5.8: Power and Area Cost Estimates of DPD model for Test Set#1 in 28nm

Full Multipliers Constant Multipliers Adder s Total

Power of P 3 0 0

Orthogonal 0 3 3

Filters 0 2+4+10+2 1+3+9+1

Output stage 0 0 3

Total 3 21 20

Power (mW) 15.21 49.14 18.9 83.25

Area (mm2) 0.075 0.315 0.05 0.44

5.6.2 Power and Area Estimates for 195MHz Bandwidth 65dBmV Case

The DPD model for Test Set #2 utilizes a total of 18 coefficients (N1=1, N2=2, N3=7 and N5=1). A

breakdown of the power and area cost contributions is presented in Table 5.8. The power and area cost

of the DPD model for Test Set#2 is estimated to be 83.3mW and 0.44mm2.

Table 5.9: Power and Area Cost Estimates of DPD model for Test Set#2 in 28nm

Full Multipliers Constant Multipliers Adder s Total

Power of P 3 0 0

Orthogonal 0 3 3

Filters 0 2+4+14+2 1+3+13+1

Output stage 0 0 3

Total 3 25 24

Power (mW) 15.21 58.5 22.68 96.4

Area (mm2) 0.075 0.375 0.06 0.51


80

5.7 Summary

The MxL235 PA is designed for DOCSIS 3.2 upstream gateways. At its designated bias setting (Bias 2), the

PA consumes 3.3W of power. The MxL235 board is modified to operate at a lower bias setting (Bias 0),

consuming 2.3W of power. However, the linearity performance of the PA is degraded at the lower bias.

The aim of the proposed DPD model, architecture and training scheme is to restore the linearity

performance of the PA without incurring significant power costs. The goal of this study is to reduce

power consumption while maintaining performance.

Measured predistortion results are compared against the DOCSIS 3.1 standards and the MxL235 PA at its

original bias setting. Table 5.10 provides a comparison of performance and power consumption of the

PA at Bias 2, Bias 0 and Bias 0 with DPD. Results indicate that the PA at Bias 0 with DPD performs

comparably to the PA at Bias 2 and meets DOCSIS 3.1 standards. Furthermore, the resilience of the

proposed DPD system to temperature and board variations is verified. Results suggest that a

temperature compensated DPD scheme with offline factory calibration for each board results in the

most linearity gains. Finally, power and area cost estimates of the proposed DPD system are well within

the 1W power budget. In summary, the proposed DPD system would reduce power consumption by 25%

while maintaining PA performance.

Table 5.10: Summary of MxL235 Power Consumption, Efficiency and Linearity Performance at Bias 2, Bias 0 and

Bias 0 with DPD

PA Power

Consumption (W)

DPD Power Consumption

(W)

PA Efficiency (%)

Meets DOCSIS 3.1 Upstream

Specifications?

Bias 2 3.3 0 4.8

Bias 0 2.2 0 7.2

Bias 0 + DPD 2.2 0.1 7.2

Conclusion

81

6 Conclusion

6.1 Summary of Contributions

A digital linearization strategy is proposed for DOCSIS 3.1 upstream applications. The proposed digital

predistortion scheme saves power and reduces heat mitigation costs by enabling low power operation

of the upstream amplifier without linearity degradation across a bandwidth that is almost double the

largest bandwidth encountered in DPD literature. Furthermore, the digital predistortion scheme

accounts for temperature and board variations by virtue of temperature compensation techniques and

per-board DPD calibration. Finally, the DPD scheme overcomes novel challenges specific to DOCSIS 3.1

upstream applications: digital passband input signals and spectral overlapping of intermodulation and

harmonic distortion products.

The linearization strategy was investigated on a recently announced DOCSIS 3.1 upstream power

amplifier supporting 204MHz of simultaneous bandwidth and output power capabilities of 69dBmV. The

hardware drivers on the power amplifier evaluation board were modified to support lower bias settings

and more power savvy power amplifier operation for a power saving of 1W. The impact of this

modification on PA linearity was evaluated against the default PA linearity performance as measured by

in-band and out-of-band distortion levels. An in-band and out-of-band linearity degradation of 9dB and

8.4dB, respectively, was observed for an OFDM signal with a bandwidth of 195MHz, center frequency of

102.5MHz and PAPR of 13dB at an ambient temperature of 25°C. The proposed linearization strategy

introduces an area and power overhead of 0.51mm2 and 100mW in 28nm for a net power savings of

900mW. The DPD system is located before the DAC in the upstream transmit chain and is initialized after

board assembly with board specific coefficients indexed by temperature. As a result, it has a higher

degree of tolerance for temperature and process variations. Thus, the power amplifier may be operated

more efficiently and the total power consumption of the transmitter can be reduced with temperature

compensated static digital linearization techniques, thereby decreasing heat mitigation costs.

Conclusion

82

To improve DPD system estimation in the presence of low-power PA operation under large bandwidth

and high PAPR signal conditions, a memory polynomial digital predistortion model with increased

stability through orthogonalization techniques is proposed. The proposed orthogonal memory

polynomial model with sparse delay taps enhances coefficient estimation by reducing correlation

between DPD model terms and thereby reducing numerical instability issues usually associated with

DPD models for large bandwidth, high PAPR applications. The benefits are two-fold: fewer terms are

required to capture memory effects in the PA, reducing DPD complexity and the coefficient estimation

process is less prone to errors.

Similarly, a new DPD model training scheme is proposed in order to focus the DPD’s hardware and

power efforts on distortion mitigation rather than channel equalization for the 200MHz bandwidth. The

proposed training scheme uses the PA input and equalized PA output for training, reducing errors

between the reference signal and a channel compensated observation signal. These residual errors are

largely the result of nonlinearities in the PA whereas a non-constant channel response contributes to

residual errors between PA input and measured raw PA output. Therefore, the proposed DPD training

scheme reduces the number of first-order memory terms, thereby minimizing DPD complexity without

incurring additional hardware or power costs.

A predistortion test bed exceeding the desired linearity of the overall DOCSIS 3.1 DPD system is designed

using commercially available ADC and DAC components and a Virtex 6 ML605 FPGA. The tandem

operation of the power-efficient PA and the proposed DPD system with a temperature-compensated

static architecture, orthogonal model and equalized training scheme is compared against DOCSIS 3.1

standards and the PA at its original power setting using in-band and out-of-band distortion metrics.

Furthermore, the performance of the DPD system is tested under temperature variations, board

variations and varying test signal characteristics to emulate the predicted conditions of the DOCSIS 3.1

upstream chain. In the case of 195MHz operation with 65dBmV output power, the proposed DPD

system suppresses distortion by 11.7dB in the best case (narrowband 24MHz OFDM signal at high center

frequency of 188MHz at room temperature) and -0.4dB in the worst case (narrowband 24MHz OFDM

signal at low center frequency of 17MHz and -18°C ambient). The DPD system suppresses distortion and

improves PA linearity in the more demanding high frequency cases at the cost of slightly degrading PA

performance in low frequency cases where the linearity is already exceptional. This frequency

dependent performance trade-off is acceptable considering that the proposed DPD system improves the

Conclusion

83

linearity of low power PA operation to DOCSIS 3.1 standards. Furthermore, the linearity performance of

the power efficient PA with DPD is comparable to that of the PA at its original power settings, thus

delivering net power savings. In summary, the proposed DPD system would reduce power consumption

by 25% while maintaining PA performance.

6.2 Future Directions

Testing Linearization Strategy with Other DOCSIS 3.1 Power Amplifiers

Broadcom recently announced a DOCSIS 3.1 compliant cable modem system-on-a-chip at the 2015

Consumer Electronics Show [78]. Though power specifications are not yet available, the solution should

house a DOCSIS 3.1 upstream PA capable of supporting bandwidths up to 204MHz. A similar power

reduction modification can be attempted on this PA to verify if predistortion techniques can restore

linearity performance without incurring significant hardware or power costs. Depending on the design of

the PA, the suppressions gains may be more than what was achieved in this thesis.

Test for Supply Voltage Variations

The proposed DPD system proved reasonably resilient to process, temperature and signal variations.

However, the tolerance of the DPD system to supply voltage variations in the PA has not been studied.

The DPD system would be impractical if it proves sensitive to PA supply variations.

Compensation for Power Amplifier Aging

Static open-loop DPD architectures, such as the one proposed in this thesis, generally cannot tolerate PA

aging. Adaptive DPD architectures account for PA aging by continuously updating DPD coefficients using

a hardware and power intensive observation feedback loop. However, such an approach does not

provide enough power savings to be feasible. Thus, there exists a need for a DPD architecture that

monitors long-term changes in PA behaviour and adjusts the DPD model accordingly.

ASIC Implementation of DPD

The power consumption of the proposed DPD scheme in 28nm is estimated to be a mere 10% of the

power saved by operating the PA at a lower power setting. These estimated values should be verified

through ASIC implementation of the proposed DPD model.

Appendix A: Matlab

84

Appendix A: Matlab

A.1 Matlab Code for Solving and Applying Equalization Filter

%%Code for solving equalization coefficients where the second and fourth column of in_out

%%contains time-aligned input and output samples respectively

ntaps_list=[60]; %number of delay taps

ntaps_listff=[60]; %number of advance taps

skip=5; %sparse delay taps of order 5

skipf=5;

%%solving for best fit coefficient using least squares

output_matrix=zeros(1, (size(in_out,1)-max(ntaps_list)*skip-max(ntaps_listff)*skip));

input_matrix=zeros(sum(ntaps_list)+sum(ntaps_listff), (size(in_out,1)-max(ntaps_list)*skip-

max(ntaps_listff)*skip));

for r=1:1:(size(in_out,1)-max(ntaps_list)*skip-max(ntaps_listff)*skip)

k=r+max(ntaps_listff)*skip;

input_matrix(:, r)=[ (in_out(k-ntaps_listff(1)*skip:skip:k+(ntaps_list(1)-1)*skip, 4))];

output_matrix(1,r)=(in_out(k, 2));

end

equalizer_coeff= (input_matrix*input_matrix')^-1*input_matrix*output_matrix';

%%Code for applying equalization coefficients to a signal

function [yy input]= equalize_output_ds(aaLP_inver, txos_pre,input)

[inout]=timealign(input,txos_pre);

txos_pre=inout(:,2);

ntaps=length(aaLP_inver)/2;

skip=5;

input_matrix=zeros(ntaps*2, (size(txos_pre,1)-ntaps*2*skip));

for r=1:1:(size(txos_pre,1)-ntaps*2*skip),

k=r+ntaps*skip;

input_matrix(:, r)=[ (txos_pre(k-ntaps*skip:skip:k+(ntaps-1)*skip))];

end

yy=(aaLP_inver'*input_matrix)';

input=inout(ntaps*skip+1:end-ntaps*skip,1);

Appendix A: Matlab

85

A.2 Matlab Code for Solving and Applying DPD Coefficients

%%Code for solving DPD coefficients with orthogonal memory polynomial where the second and fourth

%%column of in_out contains time-aligned input and output samples respectively

ntaps_listff=[1;2;5;0;1;0;0];

ntaps_list= [1;2;5;0;1;0;0];

skip=5;

skipf=5;

output_matrix=zeros(1, (size(in_out,1)-max(ntaps_list)*skip-max(ntaps_listff)*skip));

input_matrix=zeros(sum(ntaps_list)+sum(ntaps_listff), (size(in_out,1)-max(ntaps_list)*skip-


%%forming estimation matrix

for r=1:1:(size(in_out,1)-max(ntaps_list)*skip-max(ntaps_listff)*skip),


input_matrix(:, r)=[ (in_out(k-ntaps_listff(1)*skip:skip:k+(ntaps_list(1)-1)*skip, 4)/K);...

(1/sqrt(2))*((in_out(k-(ntaps_listff(2))*skip:skip:k+(ntaps_list(2)-1)*skip, 4)/K).^2-1);...

(1/sqrt(6))*((in_out(k-ntaps_listff(3)*skipf:skipf:k+(ntaps_list(3)-1)*skipf, 4)/K).^3 -

3*(in_out(k-ntaps_listff(3)*skip:skip:k+(ntaps_list(3)-1)*skip, 4)/K));...

(1/sqrt(24))*((in_out(k-(ntaps_listff(4))*skip:skip:k+(ntaps_list(4)-1)*skip, 4)/K).^4-

6*(in_out(k-(ntaps_listff(4))*skip:skip:k+(ntaps_list(4)-1)*skip, 4)/K).^2 +3);...

(1/sqrt(120))*((in_out(k-ntaps_listff(5)*skipf:skipf:k+(ntaps_list(5)-1)*skipf, 4)/K).^5 -

10*(in_out(k-ntaps_listff(5)*skipf:skipf:k+(ntaps_list(5)-1)*skipf, 4)/K).^3 + 15*(in_out(k-

ntaps_listff(5)*skip:skip:k+(ntaps_list(5)-1)*skip, 4)/K));...

output_matrix(1,r)=(in_out(k, 2));

end

%% LS estimation

aa2= (input_matrix*input_matrix')^-1*input_matrix*output_matrix';

%%Code for applying DPD coefficients to a signal txos_pre

ntaps_listff=[1;2;5;0;1;0;0];

ntaps_list= [1;2;5;0;1;0;0];

skip=5;

skipf=5;

input_matrix=zeros(sum(ntaps_list)+sum(ntaps_listff), (size(txos_pre,1)-max(ntaps_list)*skip-


for r=1:1:(size(txos_pre,1)-max(ntaps_list)*skip-max(ntaps_listff)*skip),

Appendix A: Matlab

86


input_matrix(:, r)=[ (txos_pre(k-ntaps_listff(1)*skip:skip:k+(ntaps_list(1)-1)*skip));...

(1/sqrt(2))*((txos_pre(k-(ntaps_listff(2))*skip:skip:k+(ntaps_list(2)-1)*skip)).^2-1);...

(1/sqrt(6))*((txos_pre(k-ntaps_listff(3)*skipf:skipf:k+(ntaps_list(3)-1)*skipf)).^3 -

3*(txos_pre(k-ntaps_listff(3)*skip:skip:k+(ntaps_list(3)-1)*skip)));...

(1/sqrt(24))*((txos_pre(k-(ntaps_listff(4))*skip:skip:k+(ntaps_list(4)-1)*skip)).^4-

6*(txos_pre(k-(ntaps_listff(4))*skip:skip:k+(ntaps_list(4)-1)*skip)).^2 +3);...

(1/sqrt(120))*((txos_pre(k-ntaps_listff(6)*skipf:skipf:k+(ntaps_list(6)-1)*skipf)).^5 -

10*(txos_pre(k-ntaps_listff(6)*skipf:skipf:k+(ntaps_list(6)-1)*skipf)).^3 + 15*(txos_pre(k-

ntaps_listff(6)*skip:skip:k+(ntaps_list(6)-1)*skip)));...

end

yy=(aa2'*input_matrix)';

Appendix A: Matlab

87

A.3 Matlab Code for Capturing ADC Samples

%% ADC9625 Matlab Interface Program %%

%% Rosana V1.0 (08/31/2014) %%

%% HSC-ADC-EVALEZ + AD9625 Eval Board %%

%% FPGA configuration file must be loaded and SPI configured before running this script. %%

%% 1) Connect ADC evaluation board to HSC-ADC-EVALEZ board.

%% 2) Load SPIController software.

%% 3) Select appropriate FPGA configuration file.

%% 4) Verify that the SPI interface can read the ADC Chip ID.

%% 5) Apply clock signal and analog input signal to ADC.

%% 6) Verify that the SPI reports a PLL lock from ADC.

%% 7) Run scripts and functions as desired.

MyHadBoardApi = NET.addAssembly('C:\Program Files (x86)\Analog

Devices\HadBoardSupport\DLL\HadBoardApi.dll');

MyHadSdbSupport = NET.addAssembly('C:\Program Files (x86)\Analog

Devices\HadBoardSupport\DLL\HadSdpSupport.dll');

MysdpApi1 = NET.addAssembly('C:\Program Files (x86)\Analog

Devices\HadBoardSupport\DLL\sdpApi1.dll');

HadBoardApi.HadBoard.Compatibility;

NET.setStaticProperty('HadBoardApi.HadBoard.Compatibility',HadBoardApi.CompatibilityFlags.('HadSd

p'));

%% Begin Script

% Search for HAD Board:

HadBoardApi.HadBoard.FindBoards();

if (HadBoardApi.HadBoard.BoardCount)

disp('Board Found!')

else

disp('Board NOT Found!')

end

% Program FPGA:

HadBoardApi.HadBoard.Board.ConfigureFpga('C:\Program Files (x86)\Analog

Devices\VisualAnalog\Hardware\HADv6\AD9625_hadv6fmc.mcs');

disp('FPGA Programmed!')

%% Configure ADC/FPGA SPI Registers:

[reg_addrs,

reg_values]=AD9625_parseXML('C:\Users\Rosanah\Desktop\Rosanah\AD9625_Rosanah_V1_offsetBinary.cal'

);

HadBoardApi.HadBoard.Board.SpiInitInterface(1,HadBoardApi.HadSpiParameters(1,0,0));

HadBoardApi.HadBoard.Board.SpiWrite(reg_addrs, reg_values);

HadBoardApi.HadBoard.Board.SpiWrite(int16(255), uint8(1));

HadBoardApi.HadBoard.Board.FpgaSpiWrite(uint16([288;289;292]),uint16([135;7;31]));

if (HadBoardApi.HadBoard.Board.SpiRead(int16(10)))

disp('PLL Locked');

else

disp('PLL NOT Locked');

end

Appendix A: Matlab

88

if (HadBoardApi.HadBoard.Board.SpiRead(int16(20)))

disp('Twos Complement');

else

disp('offset binary')

end %% Get Data From ADC:

DataLength = int32(2^17);

HadBoardApi.HadBoard.Board.FillFifos (DataLength, 30);

if (uint16(HadBoardApi.HadBoard.Board.FpgaSpiRead(uint16(330)))==16)

HadBoardApi.HadBoard.Board.FpgaSpiWrite(uint16(320),uint16(3));

else

ADC_Data = HadBoardApi.HadBoard.Board.CaptureFifoWords (DataLength, 0);

end

output=((double(uint16(ADC_Data))-32767)./32767);

Appendix A: Matlab

89

A.4 Matlab Code for Downloading Waveforms to DAC

%%Matlab code for downloading the waveform txos to the DAC

txos2=(2^15-1)*(0.2)*txos/rms(txos)+ (2^15-1);

F=fimath( 'ProductMode','SpecifyPrecision','SumMode','SpecifyPrecision','RoundMode','Nearest',

'OverflowMode', 'Saturate');

in_bits=fi(txos2,0, 16,1,0,F);

test=hex(in_bits);

t = tcpip('192.168.1.10', 7);

fopen(t);

for k=1:2:(size(test,1)),

fwrite(t,strcat(test(k+1,:),test(k,:)));

end

for k=1:2:((2^15)*6-size(test,1)),

fwrite(t,strcat('7fff','7fff'));

end

sample_hex=dec2hex((size(test,1)/6)-1);

fwrite(t,strcat('0000',sample_hex));

fclose(t);

Appendix B: Measurement Results

90


B.1 Results with Temperature Variations for 100MHz 69dBmV

In section 5.5.2.3, distortion measurements for the MxL235 PA at Bias 2, Bias 0 and Bias 0 with the

temperature compensated predistortion scheme are presented for two signal conditions. This section

demonstrates additional distortion measurements for other signal conditions. Figure B.1.1 illustrates

measured distortion levels for a narrow-band low-frequency OFDM signal. Figure B.1.2 depicts

measured distortion levels for a narrow-band mid-frequency OFDM signal. Finally, Figure B.1.3 shows

distortion levels for a wideband 100MHz OFDM signal centered at 55MHz.

Figure B.1.1 : Worst In-Band and Worst Out-Of-Band Distortion for 24MHz OFDM Signal at 17MHz Fc Across Temperature with MxL235 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test

Set #1

-20 -10 0 10 20 30 40 50 60 70 8045

50

55

60

65

70

34MHz 34MHz 37MHz 35MHz

39MHz58MHz

53MHz 36MHz

36MHz58MHz

32MHz

33MHz 49MHz

38MHz

53MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)


Worst In Band bias2

Worst In Band bias0






91

Figure B.1.2: Worst In-Band and Worst Out-Of-Band Distortion for 24MHz OFDM Signal at 55MHz Fc Across Temperature with MxL235 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test

Set #1

Figure B.1.3: Worst In-Band and Worst Out-Of-Band Distortion for 24MHz OFDM Signal at 55MHz Fc Across Temperature with MxL235 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test

Set #1

-20 -10 0 10 20 30 40 50 60 70 8040

45

50

55

60

65

70

159MHz159MHz

162MHz169MHz

169MHz150MHz

169MHz

159MHz162MHz 160MHz

157MHz157MHz

157MHz

157MHz 164MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)


Worst In Band bias2

Worst In Band bias0





-20 -10 0 10 20 30 40 50 60 70 8040

45

50

55

60

65

70

155MHz168MHz

155MHz

168MHz

162MHz

155MHz120MHz

162MHz135MHz

120MHz

153MHz 150MHz132MHz

145MHz

145MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)


Worst In Band bias2

Worst In Band bias0






92

B.2 Results with Process Variations for 100MHz 69dBmV

In section 5.5.2.4, distortion measurements for the MxL235-2 PA at Bias 2, Bias 0 and Bias 0 with the

temperature compensated predistortion scheme are presented for one signal condition. This section


measured distortion levels for a narrow band low frequency OFDM signal. Figure B.2.2 depicts measured

distortion levels for a narrow band mid frequency OFDM signal. Figure B.2.3 shows distortion levels for a

narrow band high frequency OFDM signal. Finally, Figure B.2.4 demonstrates distortion levels for a

100MHz OFDM signal centered at 55MHz.

Figure B.2.1: Worst In-Band and Worst Out-Of-Band Distortion for 24MHz OFDM Signal at 17MHz Fc Across Temperature with MxL235-2 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test


-20 -10 0 10 20 30 40 50 60 70 8045

50

55

60

65

70

35MHz 32MHz

36MHz

33MHz48MHz

50MHz

44MHz

50MHz53MHz

45MHz

48MHz

40MHz62MHz

58MHz 50MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)

Worst In Band and Worst Out of Band and Notch for 24MHz and 17MHz

Worst In Band bias2

Worst In Band bias0






93





-20 -10 0 10 20 30 40 50 60 70 8040

45

50

55

60

65

70

160MHz167MHz

169MHz 167MHz167MHz

158MHz 167MHz169MHz

160MHz 160MHz

157MHz164MHz

158MHz

164MHz 164MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)


Worst In Band bias2

Worst In Band bias0





-20 -10 0 10 20 30 40 50 60 70 8035

40

45

50

55

60

65

108MHz108MHz

107MHz 107MHz

107MHz

171MHz

107MHz

112MHz

107MHz107MHz

173MHz

184MHz

187MHz

187MHz 187MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)


Worst In Band bias2

Worst In Band bias0






94

Figure B.2.4: Worst In-Band and Worst Out-Of-Band Distortion for 48MHz OFDM Signal at Fc=29MHz and 81MHz Across Temperature with MxL235-2 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion

for Test Set #1 (Training with Original MxL235)

-20 -10 0 10 20 30 40 50 60 70 8038

40

42

44

46

48

50

52

54

160MHz

165MHz167MHz

164MHz 170MHz

155MHz155MHz

155MHz153MHz 153MHz

157MHz

157MHz 157MHz 156MHz147MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)

Worst In Band,Worst Out of Band and Notch for 48MHz at 29MHz and 81MHz

Worst In Band bias2

Worst In Band bias0





Notch bias2

Notch bias0

Notch predistorted


95

B.3 Results with Temperature Variations for 195MHz 65dBmV

In section 5.5.3.2, distortion measurements for the MxL235 PA at Bias 2, Bias 0 and Bias 0 with the

temperature compensated predistortion scheme are presented for two signal conditions. This section


measured distortion levels for a narrow-band mid-frequency OFDM signal. Figure B.3.2 depicts

measured distortion levels for a narrow-band high-frequency OFDM signal. Finally, Figure B.3.3 shows

distortion levels for a wideband 195MHz OFDM signal with a center 3MHz notch at 102.5MHz.

Figure B.3.1: Worst In-Band and Worst Out-Of-Band Distortion for 24MHz OFDM Signal at Fc=93MHz Across Temperature with MxL235 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test

Set #2

Figure B.3.2: Worst In-Band and Worst Out-Of-Band Distortion for 24MHz OFDM Signal at Fc=93MHz Across

Temperature with MxL235 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for Test Set #2

-20 -10 0 10 20 30 40 50 60 70 8045

50

55

60

65

70

7MHz

108MHz

109MHz

108MHz111MHz

108MHz108MHz 108MHz

108MHz

189MHz7MHz

8MHz

7MHz 7MHz6MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)


Worst In Band bias2

Worst In Band bias0





-20 -10 0 10 20 30 40 50 60 70 8042

44

46

48

50

52

54

56

58

203MHz

203MHz

8MHz204MHz

171MHz

203MHz

204MHz 204MHz 203MHz

204MHz

170MHz

172MHz

170MHz

170MHz

167MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)


Worst In Band bias2

Worst In Band bias0






96

Figure B.3.3: Worst In-Band and Worst Out-Of-Band Distortion for 96MHz OFDM Signal at Fc=53MHz and 152MHz Across Temperature with MxL235 at Bias2, Bias 0 and Bias 0 with the Temperature Compensated Predistortion for

Test Set #2

-20 -10 0 10 20 30 40 50 60 70 8042

44

46

48

50

52

54

202MHz

202MHz

204MHz

203MHz

204MHz

203MHz

203MHz203MHz

203MHz 203MHz

203MHz 203MHz

203MHz203MHz

202MHz

Temperature (deg C)

Avera

ge P

ow

er

(dB

c)

Worst In Band, Worst Out of Band and Notch for 96MHz at 53MHz and 152MHz

Worst In Band bias2

Worst In Band bias0





Notch bias2

Notch bias0

Notch predistorted

Appendix C: Test Bed Board Modifications

97


C.1 Modifications to AD9739A DAC Evaluation Board

The board schematic for the AD9739A-FMC-EBZ evaluation board from Analog Devices [79] includes the

clock circuitry shown in Figure C.1.1. The AC-coupling capacitors C99 and C102 (on the back of the

board) need to connect to the chosen DACCLK source. The switch S1 disconnects the supply voltage to

either the ADF4350 or the ADCLK914 buffer which is connected to the external clock SMA connector.

However, when the switch is configured to select the external clock, the supply voltage to the ADF4350

on-board clock is pulled to ground. The solution is to short the S1 switch such that the supply voltage is

present for both the ADCLK914 buffer and the ADF4350 clock, and then program the ADF4350 clock to a

power down state in order to use an external clock.

Figure C.1.1: Clock Circuitry for AD9739A-FMC-EBC Evaluation board [76]


98

C.2 Modifications to AD9625 ADC Evaluation Board

The board schematic for the AD9625-2.5EBZ evaluation board from Analog Devices [80] includes the

clock circuitry shown in Figure C.2.1. The goal is to configure the board to use the CVC055BE-2430-2585

Voltage Controlled Oscillator (VCO) from Crystek Microwave as a clock source. First, the Y602 pad is

populated with the CVC055BE-2430-2585 Voltage Controlled Oscillator (VCO) from Crystek Microwave.

Then, a potentiometer is added to the P602 header, using the center tap to tune the oscillator’s

frequency to 2.5GHz. Finally, R601 is removed.

Figure C.2.1: Clock Circuitry for AD9625-2.5EBZ evaluation board [77]

Appendix D: Data Sheets and Product Briefs

99



100


101


102


103

References

104

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