NXP PowerPoint template (Title) Template for presentations ...

32
The PSP compact MOSFET model An update Gert-Jan Smit , Andries Scholten, D.B.M. Klaassen — NXP Semiconductors Ronald van Langevelde — Philips Research Europe Gennady Gildenblat, Weimin Wu, Xin Li, Amit Jha, Hailing Wang* Arizona State University; *now at IBM MOS-AK, Montreux, September 22, 2006

Transcript of NXP PowerPoint template (Title) Template for presentations ...

Page 1: NXP PowerPoint template (Title) Template for presentations ...

The PSP compact MOSFET modelAn updateGert-Jan Smit, Andries Scholten, D.B.M. Klaassen — NXP Semiconductors

Ronald van Langevelde — Philips Research Europe

Gennady Gildenblat, Weimin Wu, Xin Li, Amit Jha, Hailing Wang*

— Arizona State University; *now at IBM

MOS-AK, Montreux, September 22, 2006

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Affiliations

Semiconductorsfounded by Philips

http://pspmodel.asu.eduhttp://www.nxp.com/Philips_Models/mos_models/psp/

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Outline

History & overview

DC verification on 65nm technology

Symmetry and distortion

Non-quasi static effects

Summary & references

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Outline

History & overview

DC verification on 65nm technology

Symmetry and distortion

Non-quasi static effects

Summary & references

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History

April 2005: First PSP version (100.0) released. Created from– MOS Model 11 (Philips)– SP (Penn State)

December 2005: CMC elects PSP as “next generation compact MOSFET model” (i.e. successor of BSIM3/4)

June 2006: First CMC-standardized version (PSP 102.0) was released

Future: PSP extended to complete family of models– Bulk CMOS– Varactor– PD-SOI– FD-SOI– FinFETs– …

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Model overview

PSP is a surface potential basedcompact MOSFET model, suitable for digital, analog and RF design

– non-uniform lateral/vertical doping– field-dependent mobility– velocity saturation– conductance effects (CLM, DIBL,

etc.)– series-resistance– short-channel effects (incl. RSCE)– narrow-width effects– gate poly-depletion– quantum-mechanical corrections

– overlap capacitances (ψs-based)– impact ionization current– gate leakage current– gate-induced drain/source leakage

(GIDL, GISL)– junction diode I-V and C-V (forward

and reverse)– diode reverse breakdown– noise (1/f, thermal, induced gate and

shot noise)– non-quasi-static effects– gate and bulk resistances– STI stress effect

See also MOS-AK 2005

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Update PSP 102.0

Changes PSP 100.0 102.0– Binning– Improved Gummel symmetry (modified CLM-model and VB-clamping)– Replaced lateral gradient factor– More flexible geometry scaling– Improved mobility model (CS, FETA, scaling)– Improved forward bulk-bias behavior– BSIM-like instance parameters for JUNCAP2 (AS, AD, PS, PD)– Several minor improvements, bug fixes, and maintenance– October 2006: PSP 102.1 includes first C-implementation of NQS-model

Partly based on useful feedback by Jazz, Infineon, Freescale, STm, RFMD, Analog Devices, …

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Outline

History & overview

DC verification on 65nm technology

Symmetry and distortion

Non-quasi static effects

Summary & references

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Long channel (65nm technology)

Drain current and output conductance

W/L = 10/1µm, VGS = 0…1V

0.0 0.2 0.4 0.6 0.8 1.0 0.0

0.2

0.4

0.6

0.8

1.0

V DS (V)

I D (

mA

)

0.0 0.2 0.4 0.6 0.8 1.0 10 -910 -8

10 -7

10 -6

10 -5

10 -4

10 -3

10 -2

V DS (V)

g DS

(A/V

)

measurementPSP

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Short channel (65nm technology)

Drain current and output conductance

W/L = 10/0.04µm (poly length = 40nm), VGS = 0…1V

0.0 0.2 0.4 0.6 0.8 1.0 0

2

4

6

8

V DS (V)

I D (

mA

)

0.0 0.2 0.4 0.6 0.8 1.0 10 -7

10 -6

10 -5

10 -4

10 -3

10 -2

10 -1

V DS (V)

g DS

(A/V

)

measurementPSP

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Gate current (65nm technology)

Gate current

W/L = 10/1µm, VDS = 0…1V

PSP model has been verified to successfully describe various 90nm, 65nm and 45nm processes

-1.0 -0.5 0.0 0.5 1.0 10 -10

10 -9

10 -8

10 -7

10 -6

V GS (V)

I G (

A)

measurementPSP

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R2R-circuit

Benchmark test for quality of integral along channel

Ideal long channel model

10 -1 10 0 10 1 10 2 0.00

0.05

0.10

0.15

I fs ( µ A)

rel.

erro

r (%

)

1

2

36

fs

fs12error rel.I

IInn −⋅=

∫ ⋅⋅−=DB

SB

dinvDS

V

V

VqL

WI µ

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Outline

History & overview

DC verification on 65nm technology

Symmetry and distortion

Non-quasi static effects

Summary & references

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Gummel symmetry (i)

CMOS devices are symmetric w.r.t. source/drain

Imposed on the model by applying source/drain interchange

Guaranteeing a smooth connection at VDS=0 is nontrivial

)V,V,V,V(I)V,V,V,V(I:V BSGDDSBSGDDSDS+=≥ 0

)V,V,V,V(I)V,V,V,V(I:V BDGSDSBSGDDSDS+−=< 0

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Gummel symmetry (ii)

Why is Gummel symmetry nontrivial to achieve?

0.0 0.5 1.0 1.5 2.0 0.0

0.1

0.2

0.3

0.4

0.5

0.6

V DS (V)

I D (

mA

)

• velocity saturation• VDSAT calculation• VDS VDSAT transition• channel length modulation (CLM)•….

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Gummel symmetry (iii)

source

oxide

gate

drain

-VX VXVB

VGSymmetry testID(VX) smooth at VX=0?

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Gummel symmetry (iv)

-0.3-0.2 -0.1 0.0 0.1 0.2 0.3 -4

-3

-2

-1

0

1

2

V X (V)

∂ 3

I D /∂

V 3 X

-0.10 -0.05 0.00 0.05 0.10-3.50

-3.25

-3.00

-2.75

-2.50

V X (V)

∂ 3 I D

/∂V

3 X

improved CLM model (PSP102)

old model(PSP < 101)

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Distortion (i)

Gummel symmetry is important for RF-CMOS circuit design (distortion)

PSP gives excellent description up to at least 3rd order derivatives

0.0 0.3 0.6 0.9

10-3

10-2

10-1

V DS (V)

g DS

i (A

/Vi )

NMOS10/0.12

gDS1

gDS2

gDS3

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50Ω 50Ω

Distortion (ii)

Two-tone intermodulation distortion simulation (1.8 and 1.9 GHz)

VGS=1V, VDS=VSB=0V, W/L=5/0.3µm NMOS, 90nm technology)

-60 -50 -40 -30 -20 -10

-150

-100

-50

P in (dbm)

P out

(db

m)

theoretical slope PSP simulation

-60 -50 -40 -30 -20 -10

-150

-100

-50

P in (dbm)

P out

(db

m)

theoretical slope BSIM4 simulation

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Outline

History & overview

DC verification on 65nm technology

Symmetry and distortion

Non-quasi static effects

Summary & references

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PSP NQS model (i)

Non-quasi static effects:it takes time for charge tomove trough the channel

– distributed effect– “memory” effect– continuity equation: dQ/dt ∝ dI/dx

Previously: channel segmentation (still good benchmark!)

PSP: spline collocation method (adopted from SP model)

No parameter fitting!

DS

Gate

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PSP NQS model (ii)

Same physics as segmentation model, but much faster:

0

2

4

6

8

10

12

14

0 2 4 6 8 10

no. collocation points

rela

tive

sim

ulat

ion

time

segmentation

spline collocation method

3x faster!

QS reference

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PSP NQS model (iii)

implemented as sub-circuits, solved by circuit simulator:

example:(N = 2)

( )211 Q,QfC ⋅

C

11 QV =

( )212 Q,QfC ⋅

C

22 QV =

current continuity equation + spline approximation

system of (coupled) ordinary differential equations

( )N1kk ,, QQf

dtdQ

K−= Qk: charge densities along channel

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PSP NQS model (iii)

Does model preserve basic physics?

NQS model sanity check– Important for varactor modeling!

Basic NQS physics– strong inversion– VDS=0– f 0

DSin 12

1g

R⋅

=

DSin 12

1g

R⋅

=

PSP-NQSno para

meter fi

tting!

SWNQS=9

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10 0 10 1 10 2 10 -4

10 -3

10 -2

10 -1

10 0

f (GHz)

Re(

Y 11

) (S)

10 0 10 1 10 2 10 -5

10 -4

10 -3

10 -2

10 -1

f (GHz)

Re(

Y 21

) (S)

10 0 10 1 10 2 10 -4

10 -3

10 -2

10 -1

10 0

f (GHz)

Re(

Y 11

) (S)

10 0 10 1 10 2 10 -5

10 -4

10 -3

10 -2

10 -1

f (GHz)

Re(

Y 21

) (S)

10 0 10 1 10 2 10 -4

10 -3

10 -2

10 -1

10 0

f (GHz)

Re(

Y 11

) (S)

10 0 10 1 10 2 10 -5

10 -4

10 -3

10 -2

10 -1

f (GHz)

Re(

Y 21

) (S)

PSP NQS model (v)

Y-parameter measurements

NMOS W/L=120/3µm, VDS = 1.5V, VGS = 0.5, 1.0, 1.5V

measurementPSP quasi-staticPSP NQS

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10 0 10 1 10 2 10 1

10 2

10 3

10 4

f (GHz)

C GG

(fF)

10 0 10 1 10 2 10 1

10 2

10 3

10 4

f (GHz)

C DG

(fF)

10 0 10 1 10 2 10 1

10 2

10 3

10 4

f (GHz)

C GG

(fF)

10 0 10 1 10 2 10 1

10 2

10 3

10 4

f (GHz)

C DG

(fF)

10 0 10 1 10 2 10 1

10 2

10 3

10 4

f (GHz)

C GG

(fF)

10 0 10 1 10 2 10 1

10 2

10 3

10 4

f (GHz)

C DG

(fF)

PSP NQS model (vi)

Y-parameter measurements

NMOS W/L=120/3µm, VDS = 1.5V, VGS = 0.5, 1.0, 1.5V

measurementPSP quasi-staticPSP NQS

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“Killer” NOR circuit (i)

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“Killer” NOR circuit (ii)

0 50 100 150 200 -0.5

0.0

0.5

1.0

1.5

t (ns)

V (V

)

0 50 100 150 200 -2

-1

0

1

t (ns)

V (V

)

V(A) in1V(B) in2V(Q) out

V(X) QSV(X) NQS

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Outline

History & overview

DC verification on 65nm technology

Symmetry and distortion

Non-quasi static effects

Summary & references

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Summary

Affiliation change:– Philips NXP– Penn State Arizona State

PSP is the new CMC industrial standard MOSFET model

PSP has an excellent description of distortion

PSP has a unique physics based NQS-extension

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References

website http://pspmodel.asu.edu

PSP general– TED 53(9), p. 1979 (2006)– Chapter 2 of “Transistor Level Modeling for Analog/RF IC Design”,

W. Grabinski, B. Nauwelaers and D. Schreurs (Eds.),Springer-SBM, February 2006

PSP NQS– TED 53(9), p. 2035 (2006)

JUNCAP2– TED 53(9), p. 2098 (2006)

FinFETs– IEDM 2006

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