1

18-322 Fall 2003 Lecture 27

FUTURE TRENDS IN VLSI/ULSI TECHNOLOGY

•Trends in Semiconductor Manufacturing

•Technology Status and Roadmap

•VLSIC Yield

•Design for Manufacturability

-2-

Current Technology - Manufacturing

Silicon Technology in 2003:

° minimum dimensions: 0.13 µm (.09 µm – pilot production)• 1 gigabit DRAM• 256 megabit SRAM• logic: up to 50 million transistors/IC

° chip area: • DRAM: >3 cm2

• logic: >2 cm2

• defect density < .01/cm2 (yield > 90%)

° Silicon wafer diameter: 200mm (dominant), 300 mm ramping up

° Production cycle: 30 - 60 days

Source: SIA Technology Roadmap

2

-3-

State-of-the-art volume manufacturing: 0.18 µm Technology

Al/SiO2 w/Ti/TiN HDP CVD SiOF Ti/TiN diff. barriers W plugs

Silicides STI High CurrentImplantation

35 A oxide

n+/p+

gates

RetrogradewellsBuried

layer

-4-

ACTIVE DEVICES

° Technologies: CMOS, BiCMOS, SOI

° MOSFET’s:• new structures• shallow source/drain junctions (25-30 nm)• hot electron immunity• thin gate oxides (< 15 nm)

° New fabrication processes:• Low Energy Ion Implantation• Rapid Thermal Processing (RTP)

° Bipolar devices:• double poly• SiGe

3

-5-

Interconnect Technology

Cross-section: 5+ interconnect layers

-6-

INTERCONNECT TECHNOLOGY

° Metalization:• Cu ---> ?• Double damascene Cu process

° Dielectric Layers:• low dielectric constant materials

° Plasma etching

° Planarization:• global (CMP - chemical mechanical polishing)

4

-7-

Trends in Semiconductor Manufacturing

Trend Yield and Performance Implication Mfg technologyroadmapaccelerating

Need to reduce cycle time by learningoutside of silicon

Product marketwindows arenarrowing

Rapid yield ramp imperative Delays potentially catastrophic

System on a chipaccelerating

Complex process optimization required Comprehensive characterization of

design and process interactionsrequired

Foundries gainingmarket share

Gap between design and manufacturingis exacerbated

Gap between design and manufacturing is compounded by increased time pressure and manufacturing complexity

-8-

Roadmap

• Challenges:lithography• cost of masks (especially with Phase Shifting Masks)• what’s beyond 157nm (for <70nm technologies)

interconnect• Cu/low-k integration• Interconnect dominance in signal delays

new device structures: • high k dielectrics for gate oxides• new doping techniques for shallow S/D junctions

increased relative variability (both within die and across wafer):• patterning variations (litho, etch)• layer thickness variations (CMP)• atomic level fluctuations in Vt

5

-9-

Technology: New ProcessesDeep-submicron technologies require new materials

• Need twice the manufacturing efficiency with new materials as we achieved with old materials, for same yield

•• Need twice the manufacturing efficiency with new materials Need twice the manufacturing efficiency with new materials as we achieved with old materials, for same yieldas we achieved with old materials, for same yield

HiKSiO/SiN stackHiK (for LV)

SiO2SiON

SiO2SiO2SiO2Gate Dielectric

Ni-Si/Pt-SiNi/Co-SiCo-SiCo-SiCo-SiTi-SiSalicideSOI/Strained silicon-SiGe

SOI/Strained silicon-SiGe

Epi/SOIP-EpiP-EpiP-EpiSubstrate

SiGe/MetalPoly/SiGe/Poly

stack

Dual Poly/SiGe

Dual PolyDual PolyDual Poly

Gate Electrode

Porous LowK

LowKLowKFSGFSGTEOSInterconnect Dielectric

Cu

193nm + OPC/PSM

90nm

Cu

193nm + OPC/PSM

65nm

Cu alloyCuAl-CuAl-CuInterconnect

157nm + OPC/PSM

248nm + OPC

248nm + OPC

248nmLitho45nm130nm180nm250nm

ProcessModule

-10-

Escalating Development CostsAverage $4.48 Mil

13.1

9.7

7.9 6.8 6.7 5.94.4 4.2 4.0 4.0 3.8 3.5 3.5 3.3 2.9 2.8 2.5 2.1 1.3 0.9 0.8

02468

101214

S D F Q R H G N B O E P T V L A C K I M J

Design Costs for Digital ASSPs

Deve

lopme

nt Co

st ($

MM)

Average $4.48MMAverage $4.48MM

Cost Mode: Salary & OverheadEDA Methodology

LibrariesEDA SW/HW/Support

Outside ExpensesPrototypes

Cost Mode: Salary & OverheadEDA Methodology

LibrariesEDA SW/HW/Support

Outside ExpensesPrototypes

Source: Collett International Research

6

-11-

Number of Silicon Spins in Current IC/ASIC Designs

53%

28%

15%

3% 2%0%

15%

30%

45%

60%

First Silicon 2 3 4 5 or More

Perc

ent o

f Tea

ms

Spins of Silicon

n=329

Half of the designs have multiple spinsHalf of the designs have multiple spinsHalf of the designs have multiple spins

Source: Collett International Research 2000

Percent of Total Flaws Fixed inIC/ASIC Designs Having Two or More Silicon Spins

3%3%4%

5%5%

6%7%

9%14%

43%

0% 10% 20% 30% 40% 50%

PowerClockingIR Drops

Other FlawsMixed-Signal Interface

Race ConditionYield

NoiseSlow Path

Logical or Functional

Percent of FlawsSource: Collett International Research 2000

Half of the problems are Si relatedHalf of the problems are Half of the problems are Si relatedSi related

High Re-spin RateHalf of the designs have at least 2 spins

-12-

Time #1 Concern of Designers2 of Top 3 concerns are schedule time

Current Design Concerns Among IC/ASIC Teams

1.91.9

2.83.03.03.03.1

3.33.33.4

3.43.83.8

4.04.24.2

1 2 3 4 5Degree of Concern GREATEST

1.91.9

2.83.03.03.03.1

3.33.33.4

3.43.83.8

4.04.24.2

1 2 3 4 5

OPCPhase Shifting

Die SizeCrosstalk

Power Grid/IR DropPower Consumption/Dissipation

Tool/Flow IntegrationTechnology Files

Synthesis and Place & RouteClock Distribution

Timing/Synthesis PhaseSimulation/Analysis Tools

Timing/Layout PhaseFirst Tapeout Deadline

Target PerformanceProject Completion Deadline

LEASTSource: Collett International Research 2000

7

-13-

Much of the Design Occurs after the DesignIt’s not done when people think it’s done!

Percent of Current Design Cycle Spent on Design Tasks

15% 28% 15% 12% 30%30%

0% 25% 50% 75% 100%

Curre

nt D

esig

n

Percent of Design Cycle

SpecificationRTL Design & SynthesisChip LayoutTiming & Layout VerficationDebug & Final Qualification

•Post GDS-2•Pre-Production Release

Source: Collett International Research 2000

-14-

TechnologyEscalating Complexity

•Complexity/cm2 of chip area doubles each generation•Manufacturing tolerances for features (e.g., contacts, vias, transistors) get twice as tight as previous generation

••Complexity/cmComplexity/cm22 of chip area doubles each generationof chip area doubles each generation••Manufacturing tolerances for features (e.g., contacts, vias, Manufacturing tolerances for features (e.g., contacts, vias, transistors) get twice as tight as previous generationtransistors) get twice as tight as previous generation

Design-to-Silicon

Yield Gap

Design-to-Silicon

Yield Gap

60%

70%

80%

90%

100%

0.8 µm 0.5 µm 0.35 µm 0.25 µm 0.18 µm 0.13 µm 0.1 µmTechnology Node

Product Yield

Traditional defect-limited yieldFeature-limited yield

Note: Featur e-li mited yield ass umes the feature failure rate i mproves by approxi mately 50% each generati on

Design-to-Silicon

Yield Gap

Design-to-Silicon

Yield Gap

60%

70%

80%

90%

100%

0.8 µm 0.5 µm 0.35 µm 0.25 µm 0.18 µm 0.13 µm 0.1 µmTechnology Node

Product Yield

Traditional defect-limited yieldFeature-limited yield

Note: Featur e-li mited yield ass umes the feature failure rate i mproves by approxi mately 50% each generati on

Design-to-Silicon

Yield Gap

Design-to-Silicon

Yield Gap

60%

70%

80%

90%

100%

0.8 µm 0.5 µm 0.35 µm 0.25 µm 0.18 µm 0.13 µm 0.1 µmTechnology Node

Product Yield

Traditional defect-limited yieldFeature-limited yield

Design-to-Silicon

Yield Gap

Design-to-Silicon

Yield Gap

60%

70%

80%

90%

100%

0.8 µm 0.5 µm 0.35 µm 0.25 µm 0.18 µm 0.13 µm 0.1 µmTechnology Node

Product Yield

Traditional defect-limited yieldFeature-limited yield

Note: Featur e-li mited yield ass umes the feature failure rate i mproves by approxi mately 50% each generati on

Major Material ChangesMajor Material Changes Cu, Low KNone

42.0 M# of Transistors# of Transistors5.5 M

Est. Feature CountEst. Feature Count 105 M15 M

0.35 µm0.35 µm 0.13 µm0.13 µm

Major Material ChangesMajor Material Changes Cu, Low KNone

42.0 M# of Transistors# of Transistors5.5 M

Est. Feature CountEst. Feature Count 105 M15 M

0.35 µm0.35 µm 0.13 µm0.13 µm

Major Material ChangesMajor Material Changes Cu, Low KNone Major Material ChangesMajor Material Changes Cu, Low KNone

42.0 M# of Transistors# of Transistors5.5 M 42.0 M# of Transistors# of Transistors5.5 M

Est. Feature CountEst. Feature Count 105 M15 M Est. Feature CountEst. Feature Count 105 M15 M

0.35 µm0.35 µm 0.13 µm0.13 µm0.35 µm0.35 µm 0.13 µm0.13 µm

8

-15-

Problems

• Design marginalityIC design not robust enough, too sensitive to process fluctuations or environmental factors (supply voltage, temperature)

• Process-related yield losses:misprocessing (e.g., equipment-related)systematic effectsrandom defects

• Testing issues:insufficient fault coverage in testing (test escapes)incomplete testing (does not fully represent IC operation in thefield - e.g., simultaneous switching in the system not taken into account)test-related yield losses (incorrect testing)

• Reliability:transistorsinterconnect

-16-

Die X (mm

)

Die X (mm

)Die Y (mm)

Die Y (mm)

Die

lect

ric th

ickn

ess

(um

)

CMP causes layout dependent dielectric

variation which causes yield loss

Dummy fill improves uniformity

But capacitance can go up!

CACA

CB

CB

(b) CC

CD

Optimal solution depends on both design and Optimal solution depends on both design and process considerationsprocess considerations

B. Stine et al, Transactions on Electron Devices, Vol 45 No. 3

Both!Design or Manufacturing Problem?

9

-17-

Via problems: Metal Voids

Metal voids

Could be yield or reliability problems

-18-

Random Defects

M1 Defect Wafer MapM1 Defect Size Distribution

10

-19-

SOC Integration Roadmap

-20-

Technology Choice

DSP core

RAM/ROM

analog

RISCcore

ADC

PLL

high performance

logic

BUS

random logic

or

Medium performance logic

?memory

analog high performance logic

RISC core

• Key decision criteria: cost based upon manufacturability assessment

• Example: SOC vs. 2.5D Integration

Source: W. Maly , CMU

11

-21-

Traditional Top-Down Design Flow

• Any top-down flow requires some predictive capabilities

LogicSynthesis

Placement

Routing

• Traditional top-down flows are effective when performance can be predicted via wireloadmodels during synthesis

Source: L. Pileggi, GSRC Constructive Fabrics Presentation

-22-

The DSM Prediction Problem

• But as we move toward DSM technologies, the interconnect parasitics are no longer small compared to device parasitics ---wireload models break down

Interconnect capacitance dominates

Interconnect resistance begins to play a role for “global” nets

Source: L. Pileggi, GSRC Constructive Fabrics Presentation

12

-23-

Design Flows

• The evolutionary response to this problem has been to more tightly integrate the synthesis and place/route processes

Routing

Placement

LogicRe-Synthesis

• But revolutionary breakthroughs will be required to achieve our push-button giga-scale goals

Source: L. Pileggi, GSRC Constructive Fabrics Presentation

-24-

SOC Design Perspective

• Platform-specific push-button flows for silicon implementationPlatform: A single IC or multichip package comprising a partially customizable architecture with a defined communication protocol and specific components that are generally associated with a particular application domain

• Platform design via optimal trade-off of performance vs. design timeComplex component interactions are made correct-by-platform-constructionExample: Impractical to anticipate and automate correction for all possible noise interactions – e.g. DRAM refresh causing noise spike to a PLL

• Required volume and yield (cost) is obtained via manufacturing of highly similar, regular ICs (common platform)

Manufacturability issues for VDSM partially characterize the platform Regularized platform components (e.g. RF) are manufacturable-by-construction

• Modular EDA tools and algorithms to support platform-specific design flows

13

-25-

Manufacturing Reality

• New Circuit Fabrics and tools must consider manufacturing reality for high yielding designs

• Parameters do not scale with shrinking feature sizes

• Economic factors (equipment costs) will force us to design with much larger variations than ever before

• New models and simulation capabilities are required to facilitate robust design

-26-

Interconnect Dominance

14

-27-

Robust Design• With models that capture manufacturing variations we can explore and

push the technologies to the fullest extent• One particular area of interest is IC clock distribution

Contour plotof IBM GHzµP clock skew

• New adaptable fabrics required for robust design of clock distribution and control of skew

-28-

Component Level Verification• We must also enable verification of the lowest level effects in a

hierarchical manner• Interconnect parasitics must be modeled hierarchically

Source: M. Beattie & L. Pileggi

15

-29-

Full Chip Optical Proximity Correction

Mask(Layout)

Full Chip Simulator

Calibrated Parameters

(Optics,threshold,etching)

Simulated CDObject CD

Error

-30-

OPC Example: Hammerhead correction

Uncorrected

CD linearity

improved line shortening

Hammerheadmode

simulation

16

-31-

TraditionalTraditional

Isolated Approach

DesignDesignDesign

ProcessProcessProcess

ManufacturingManufacturingManufacturing

IntegratedIntegrated

ManufacturingManufacturingManufacturing

ProcessProcessProcess

DesignDesignDesign

Integrated Solution

Conclusion: Integrated approach to DFM is required

-32-

DD DD DD

Decompose to Component Level

PP PP PP

Integrated Approach

DesignDesignDesign

ProcessProcessProcess

Start with Aggregate

Level

Yield Loss Components

Reliability

PP

PP

DD

DDModel, Simulate, Experiment to Analyze

Interactions

DD

DD

DD

PP PPPP

DD

PP

Modify Process

Modify Design

OverallChip 85.7% 58.0% 49.8%

Block A 95.0% 93.0% 88.4%Block B 95.0% 65.0% 61.8%Virgin Cache 80.0% 80.0% 64.0%Cache w/ Repair 95.0% 96.0% 91.2%

Yield Impact Matrix

Pro

duct

A

DefectivityDesign

Dependent