Emitter Coupled Logic & BiCMOScourse.ece.cmu.edu/~ece322/LECTURES/Lecture22/Lecture22.pdf · BiCMOS...
Transcript of Emitter Coupled Logic & BiCMOScourse.ece.cmu.edu/~ece322/LECTURES/Lecture22/Lecture22.pdf · BiCMOS...
Slide 1
18 - 322 Fall 2003 Lecture 22
Emitter Coupled Logic & BiCMOS
Slide 2
Emitter Coupled Logic
• ECL Inverter• Voltage Transfer Characteristics• ECL NOR Gate
Slide 3
ECL
• Ultra-high speed (GHz performance)– All fabled supercomputers used ECL
• CRAY• NEC, Fujitsu
• Lower device count per gate than TTL• Symmetric noise margins• Low noise sources
Slide 4
The Differential PairVccVcc
RcRc
Vout2Vout1
VEE
VrefVin
VccVcc
RcRc
Vout2Vout1
VEE
VrefVin
IEE
Vx
• Vref: Reference Voltage• Symmetric Design:
– Transistors, Resistors, Voltage Supplies
Slide 5
Differential Pair
Ic = β Is (e VBE/ΦT - 1)
Ic1/Ic2 = (e (Vin-Vx)/ΦT - 1)/(e (Vref-Vx)/ΦT - 1)
≈ e (Vin-Vref)/ΦT
ΦT= 26mV
Vin - Vref = 60mV -> 10x changeVin - Vref = 120mV -> 100x change!
Slide 6
Logic Levels
Assume Vin “high”
Output Levels:Vout1 = Vcc - IEERC (VOL)Vout2 = Vcc (VOH)
Input Levels:VIL = Vref - 120mVVOL = Vref + 120mV
Slide 7
Differential Pair Characteristics
• Differential Outputs– No time differential between complements
• Steep Transition region– 240 mV!– Centered around Vref
• Constant Current Drawn– High static power dissipation
• No Saturation Mode
Slide 8
Output Stage
• Problem: Output Loading Sensitivity• Problem: Logic Level Alignment• Solution: Output stage (emitter-follower)
VccVcc
RcRc
Vout2Vout1
VEE
VrefVin
IEE
Vx
VEE VEE
RB RB
Slide 9
Logic Levels and VTCVcc=5V5V
300Ω300Ω
Vout2Vout1
VEE=0V
VrefVin
IEE=3mA
Vx
0V 0V
1.5kΩ 1.5kΩ
Slide 10
Logic LevelsAssume Vin >> Vref
Vcc=5V5V
300Ω300Ω
Vout2Vout1
VEE=0V
IEE=3mA
0V 0V
1.5kΩ 1.5kΩ
Vout1 = 1.5kΩ (β+1) IB1300Ω (IB1 + 3mA) + .7V + Vout1 = 5V
Vout1 = (VOL)
Vout2 = 1.5kΩ (β+1) IB2300Ω IB2 + .7V + Vout2 = 5V
Vout2 = (VOH)
Slide 11
Choosing Vref
To Maximize Noise Margins:
Choose Vref mid-way between VOL and VOH
Vref = (VOL and VOH ) / 2 =
VOL
VOH
Vout
VinVOL VOHVIL VIH
Trans. Region
NMH
NML
Slide 12
Voltage Transfer CharacteristicVTC ECL Inverter
0
1
2
3
4
5
0 1 2 3 4 5
Vin
Vou
t Vout2Vout1
Slide 13
Current SourceIn reality, usually a resistor:
Vcc=5V5V
300Ω300Ω
Vout2Vout1
VEE=0V
VrefVin
1.2kΩ
Vx
0V 0V
1.5kΩ 1.5kΩ
Q1
Q1 CAN saturate with high Vin!
Slide 14
Current Source Resistor
5V
300Ω
VEE=0V
Vin
1.2kΩ
Vx
Q1
IC = IE = (Vin - .7V)/1.2kΩ
Vout = 4.825V - .25Vin
Saturation:
300Ω IC + 1.3kΩ IE = 4.9V
VTC ECL Inverter
3
4
5
3 3.5 4 4.5 5
Vin
Vout Vout2
Vout1
Saturationof Q1
Slide 15
ECL OR-NOR GateVcc=5V5V
300Ω300Ω
ORNOR
VEE=0V
VrefV1
1.2kΩ
0V 0V
1.5kΩ 1.5kΩ
V2
Is this logically adequate?
Slide 16
Wired-Or LogicVcc=5V
0V
1.5kΩ
Vcc=5V
0V
1.5kΩ
Vcc=5V
0V
1.5kΩ
If any base voltage is high, the net is high
What happens if more than one base is high?
Slide 17
Wired-ORAB
CD
_____A + B + C + D
• Construct large input gates• In negative logic, Wired-AND
Slide 18
ECL FanoutVcc=5V
300Ω
0V
3mA
300Ω
N-1gates
1.5kΩ
Vout (β+1) IB = 3mA N/(β+1) + Vout/ 1.5kΩ300Ω IB + .7V + Vout = 5V
• When does Vout = VIH?– Typical values ≈ 30
Slide 19
Negative Supply Voltage
• Noise on VCC shows up on signal nets• VEE much more noise tolerant.
– Common mode noise to Vin, Vref, etc• Output shorted to ground
Vcc=5V
0V
1.5kΩ
Slide 20
Power Dissipation
• Dynamic Power:– 10% of the voltage swing of CMOS
• 100x less power• Static Power:
– All gates consume static power• 3mA x 5V = 15mW!
• High Power• Low noise
Slide 21
BiCMOS
• Introduction• System Requirements• Circuit Technology• Device Technology• Process Technology• Manufacturing Issues• BiCMOS Projections
Slide 22
INTRODUCTION
BiCMOS Advantages:• Improved speed & robustness over CMOS• Lower power dissipation than bipolar• Flexible I/O’s• Higher performance analog IC’s• Latchup robustness
BiCMOS Disadvantages:• Higher costs• Longer fabrication cycle time
Slide 23
BiCMOS Role
For µP:
° Reduced delays through critical paths
° Reduced clock skews
° Increased I/O throughput
° Larger, faster on-chip memory
Slide 24
BiCMOS Inverter #1
V
P
N
N
N
1
1
2
3
NPN 1
NPN 2
V = 5 V
Vinout
CC
VOH = VCC - Vbe(on) VOL = VSS + Vce(sat)
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BiCMOS Inverter #2
VOH = VCC VOL = VSS
V
N
N1
P1
N2
3
NPN 1
NPN 2
V = 5 V
Vinout
CC
P2
8/1
8/1
8/1
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BiCMOS NAND Gate
N
N1
P1
N2
3
NPN 1
NPN 2
V = 5 V
Vout
CC
P2
A
B
Slide 27
BiCMOS DEVICES
BJT in p-well CMOS process
Slide 28
BiCMOS Technology
Slide 29
Manufacturing Issues
Main disadvantage of BiCMOS: COST
Cost adders:
° manufacturing cycle time
° defect density
° process control
° design verification