Nanometer-Scale III-V Electronics
Transcript of Nanometer-Scale III-V Electronics
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Nanometer-Scale III-V Electronics
J. A. del Alamo
Microsystems Technology Laboratories, MIT
Acknowledgements:• D. Antoniadis, A. Guo, D.-H. Kim, T.-W. Kim, D. Jin, J. Lin, W. Lu, A. Vardi,
N. Waldron, L. Xia, X. Zhao• Sponsors: Intel, FCRP-MSD, ARL, SRC, NSF, Sematech, Samsung• Labs at MIT: MTL, NSL, SEBL
The Age of Silicon SymposiumMIT, July 25, 2014
Moore’s Law
Moore’s Law = exponential increase in transistor density
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Intel microprocessors
What if Moore’s Law had stopped in 1990?
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Cell phone circa 1990GPS handheld device circa 1990
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What if Moore’s Law had stopped in 1980?
Laptop computer circa 1981
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What if Moore’s Law had stopped in 1970?
Desktop calculator 1970
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What if Moore’s Law had never happened?
Insulin pump circa 1960 “Personal calculator” circa 1960
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Moore’s Law
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How far can Si support Moore’s Law?
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Supp
ly voltage (V
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Year of introduction
Intel microprocessors
Transistor scaling Voltage scaling
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Power management demands reduction in supply voltage.
Supply voltage reduction saturating in recent years
Voltage scaling Si transistor performance suffers
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Transistor current density:
Transistor performance saturated in recent years
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NMOS: GaAs, InGaAs, InP
PMOS: Ge, InGaSb
Options for post-Si CMOS
~2x Si
~2x Si
Different lattice constant for n-FETs and p-FETs
del Alamo, Nature 2011
Measurements in High Electron Mobility Transistors (HEMTs):
• vinj(InGaAs) increases with InAs fraction in channel• vinj(InGaAs) > 2vinj(Si) at less than half VDD
• ~100% ballistic transport at Lg~30 nm
Electron injection velocity: InGaAs vs. Si
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del Alamo, Nature 2011
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f T(GHz)
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InGaAs HEMT: high-frequency record vs. time
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Best high-frequency performance of any transistor on any material system
Teledyne/MIT: fT=688 GHz
MIT devices
on GaAssubstrate
on InP substrate
fT=710 GHz(NCTU)
Kim, EDL 2010
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Bipolar/E-D PHEMT process
Henderson, Mantech 2007
40 Gb/s modulator driverTessmann, GaAs IC 1999
77 GHz transceiverCarroll, MTT-S 2002
UMTS-LTE PA moduleChow, MTT-S 2008
Single-chip WLAN MMIC, Morkner, RFIC 2007
InGaAs Electronics Today
InGaAs HEMT vs. MOSFET
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MOSFET incorporates gate oxide gate leakage suppressed
HEMT not suitable for logic: too much gate leakage current
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InGaAs MOSFETs vs. HEMTs: historical evolution
Lin, IEDM 2013
Progress reflects improvements in oxide/III-V interface
**inversion-mode
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Huang, APL 2005
ALD eliminates surface oxides that pin Fermi level “Self cleaning”
Clean, smooth interface without surface oxides
What made the difference?Atomic Layer Deposition (ALD) of oxide
• First observed with Al2O3, then with other high-K dielectrics• First seen in GaAs, then in other III-Vs
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InGaAs MOSFET: possible designs
Enhanced gate control enhanced scalability
Self-Aligned InGaAs Quantum-Well MOSFETs
• Channel: In0.7Ga0.3As/InAs/In0.7Ga0.3As (1/2/5 nm)• Gate oxide: HfO2 (2.5 nm, EOT~0.5 nm)• Self-aligned contacts (Lside~5 nm)• Si compatible process (RIE, metals)
Lin, IEDM 2013
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5 nm
0.0 0.1 0.2 0.3 0.4 0.50.00.20.40.60.81.0 Lg=20 nm
Ron=224 m0.4 V
I d (mA
/m
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Vds (V)
Vgs-Vt= 0.5 V
InGaAs double-gate Fin-MOSFET
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Key enabling technologies: • BCl3/SiCl4/Ar RIE • digital etch
Vardi, DRC 2014
40 nm 30 nm
Zhao, EDL 2014
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Vertical nanowire InGaAs MOSFETs
• Nanowire MOSFET: ultimate scalable transistor• Vertical NW: uncouples footprint scaling from Lg scaling• Top-down approach based on RIE + digital etch
Zhao, IEDM 2013 Zhao, EDL 2014
30 nm diameterInGaAs NW-MOSFET
Si integration: InGaAs SOI MOSFETs
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InGaAs channel
BOX: Al2O3
1. MBE growth 2. ALD Al2O3 3. Wafer bonding 4. InP etch back
InP donor wafer
n+ cap
BOXp-Si
BOXp-Si
III‐V bonded SOI process of IBM Zurich:Czornomaz, IEDM 2012
Mo
InGaAs channeln+ cap
BOXp-Si
InP donor wafer
InPdonor wafer
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Conclusions: exciting future for InGaAs electronics on Silicon
• Most promising material for ultra-high frequency and ultra-high speed applications first THz transistor?
• Most promising material for n-MOSFET in a post-Si CMOS logic technology first sub-10 nm CMOS logic?
• InGaAs + Si integration: THz + CMOS + optics integrated systems?