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volume 10, issue 1, 2012
• Thin-Channel Transistors
• Enabling Spin-Transfer Torque Magnetic Memory
• Enhanced Defect of Interest Monitoring
In This Issue
NANOCHIPTechnology Journal
Albert Einstein once commented that “to raise new questions, new possibilities,
to regard old problems from a new angle…marks real advance in science.”
In this age of mobile consumer electronic devices and “smart” systems for
almost every sector of the economy, semiconductor fabrication exemplifies
this drive to inquire, experiment, and innovate to anticipate and enable real
advances in our technologies.
This issue of Nanochip illustrates the variety of these technical advances as
anticipated limitations to planar scaling beyond the 2x nanometer node spur
us to introduce new materials, new integration schemes, lower-temperature
processing, and tighter process controls, enabling our customers to achieve
greater device speed and energy efficiency, longer service life, and more
compact form factors.
In transistors, where leakage poses a key challenge as the gate length scales, the limits on thinning the transistor
channel are driving our customers to explore alternative designs, such as FinFETs and ultra-thin body silicon-on-
insulator structures. We review the processing challenges unique to each, from new channel materials to novel
doping and etch techniques. We also present a new CVD gap-fill process that will be a key enabler of FinFET
fabrication and of emerging 3D memory designs, using a fluid-like, profile-insensitive fill capable of liner-free
integration with the metal films used in logic and memory devices.
More scalable alternatives to DRAM and Flash are driving such new designs as spin-transfer torque magneto-
resistive memory. Recent technology advances have addressed the need for atomic-scale control of deposition,
etch, and CMP processes, facilitating development of this new memory technology.
Endpoint metrology and dynamic profile control are transforming CMP into an important technology enabler for
advanced transistor fabrication and expanding its role in interconnect applications.
We introduce defect review technology that is able to “learn” inspection recipes autonomously while greatly reducing
the rate of nuisance defects and improving excursion identification for rapid root-cause determination.
Cover Photo: Design Concept – Harry Whitesell, Photographer – Richard Lewington
A MESSAGE FROM KATHRYN TA TABLE OF CONTENTS
3 Thin-Channel Transistors—
The Dawn of a New Era
9 Scaling Dielectric Gap Fill
With Flowable Chemical Vapor Deposition
13 CMP Applications Arrive at the Gate Stack
Enabling Advanced Transistors
18 Enabling Spin-Transfer Torque Magnetic Memory
for the 2x nm Node and Beyond
24 Through-Silicon Via Technology
Enroute to Manufacturing
29 Enhanced Defect of Interest Monitoring
With Sensitive Inspection and “Intelligent” SEM Review
Senior Director,
SSG Marketing
Silicon Systems Group
Albert Einstein once commented that “to raise new questions, new possibilities,
to regard old problems from a new angle…marks real advance in science.”
In this age of mobile consumer electronic devices and “smart” systems for
almost every sector of the economy, semiconductor fabrication exemplifies
this drive to inquire, experiment, and innovate to anticipate and enable real
advances in our technologies.
This issue of Nanochip illustrates the variety of these technical advances as
anticipated limitations to planar scaling beyond the 2x nanometer node spur
us to introduce new materials, new integration schemes, lower-temperature
processing, and tighter process controls, enabling our customers to achieve
greater device speed and energy efficiency, longer service life, and more
compact form factors.
In transistors, where leakage poses a key challenge as the gate length scales, the limits on thinning the transistor
channel are driving our customers to explore alternative designs, such as FinFETs and ultra-thin body silicon-on-
insulator structures. We review the processing challenges unique to each, from new channel materials to novel
doping and etch techniques. We also present a new CVD gap-fill process that will be a key enabler of FinFET
fabrication and of emerging 3D memory designs, using a fluid-like, profile-insensitive fill capable of liner-free
integration with the metal films used in logic and memory devices.
More scalable alternatives to DRAM and Flash are driving such new designs as spin-transfer torque magneto-
resistive memory. Recent technology advances have addressed the need for atomic-scale control of deposition,
etch, and CMP processes, facilitating development of this new memory technology.
Endpoint metrology and dynamic profile control are transforming CMP into an important technology enabler for
advanced transistor fabrication and expanding its role in interconnect applications.
We introduce defect review technology that is able to “learn” inspection recipes autonomously while greatly reducing
the rate of nuisance defects and improving excursion identification for rapid root-cause determination.
Cover Photo: Design Concept – Harry Whitesell, Photographer – Richard Lewington
A MESSAGE FROM KATHRYN TA TABLE OF CONTENTS
3 Thin-Channel Transistors—
The Dawn of a New Era
9 Scaling Dielectric Gap Fill
With Flowable Chemical Vapor Deposition
13 CMP Applications Arrive at the Gate Stack
Enabling Advanced Transistors
18 Enabling Spin-Transfer Torque Magnetic Memory
for the 2x nm Node and Beyond
24 Through-Silicon Via Technology
Enroute to Manufacturing
29 Enhanced Defect of Interest Monitoring
With Sensitive Inspection and “Intelligent” SEM Review
3 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc.
THIN-CHANNEL TRANSISTORSThe Dawn of a New Era
KEYWORDS
Transistors
Thin-Channel Transistors
FinFETs
SOI
3D Transistors
THIN-CHANNEL TRANSISTOR ARCHITECTURES DEMYSTIFIED A transistor serves as an on-off switch. An ideal switch
should have high current in its on-state and zero current
in its off-state. In reality, a transistor does leak current in its
off-state. As the size of the transistor shrinks, the current
Leakage power continues to be the single biggest challenge
to sustaining Moore’s Law, driving the need for new
transistor architectures. FinFETs or tri-gate transistors are
a new three-dimensional (3D) approach to the problem,
while ultra-thin body silicon-on-insulator (UTB-SOI)
extends conventional planar transistor scaling by
dramatically shrinking the thickness of the silicon layer.
Each approach poses significant challenges that are
stimulating advances throughout the fabrication sequence
from the types of materials used to patterning, doping,
deposition, and etching technologies. Whether FinFETs or
UTB-SOI will become the more widely adopted transistor
architecture is dependent upon the industry’s preference
for revolutionary versus evolutionary change.
Moore’s Law has served as a beacon for the
semiconductor industry, predicting device density
and performance improvements for over 40 years.
Complementary metal-oxide semiconductor (CMOS)
logic, invented in the 1960s, entered into high-volume
production in the 1980s because it enabled lower-power
circuits while keeping to the cadence of Moore’s Law.
CMOS transistor features scaled following simple rules
proposed by IBM’s Robert Dennard to predict changes
in physical properties, such as gate length, gate oxide
thickness, and junction depth needed to achieve higher
transistor density and performance.[1] During the
1990-era personal computing (PC) boom, demand
for increased device performance was such that gate
length was actually scaled faster than called for by
Dennard’s rules. Further, operating voltage reductions
specified by Dennard were not followed for system
considerations. Taken together, at the turn of the
century, these two deviations resulted in the alarming
forecast that high levels of integrated circuit power
consumption would place a fundamental constraint
on the further progression of Moore’s Law.
In response, new circuit and transistor technologies were invented to keep power consumption in check at a system level. The introduction of new materials into the transistor represented a major breakthrough. In 2003, Intel adopted strain engineering in high-volume manufacturing at the 90nm node to increase electron and hole mobility. To keep transistor off-state leakage within acceptable limits, gate length scaling slowed at subsequent nodes while progressively increasing strain levels enabled continuing increases in device performance. Similarly, the silicon dioxide gate dielectric had reached a thickness at which tunneling leakage currents were unacceptably high. In 2007, Intel replaced the 40-year-old silicon dioxide gate dielectric with a new insulator containing hafnium oxide and thereby started upon a new trajectory that allows for gate dielectric thickness scaling without compromise to leakage.
Today, leakage power continues to be the single biggest
challenge to sustaining Moore’s Law. Here, we discuss
the need for new transistor architectures that will
enable tomorrow’s lower-power smartphones, tablets,
and mobile PCs.
This roadblock would have stalled on-state drive current advances, if not for major technological breakthroughs in strain engineering and high-κ metal gates (HKMG). However, increasing device packing density according to Moore’s Law places renewed pressure on a means of scaling gate lengths below 25nm. For such short channel lengths, low off-state leakage current can be achieved only if the electric field applied to the transistor gate almost completely controls the electrons or holes moving in the channel. This can be achieved if the silicon body of the transistor channel is thin enough (<12nm).
The challenge of thinning the transistor channel has sparked distinct approaches amongst semiconductor
Figure 2
Planar CMOS FinFET UTB-SOI
Silicon Substrate
Gate
FinFET
Silicon Substrate
Gate
Fin
STI OxideSilicon Substrate
Buried Oxide
RaisedSource
RaisedDrain
Gate
Figure 1
Gat
e Le
ngth
(nm
)
Node (nm)
4 3 2 1.5 0.8 0.5 0.35 0.25 0.18 0.13 90 65 45 32 22 14 10 71
1000
100
10
Conventional Planar TransistorThin Channel TransistorDennard Rule
Gate LengthScaling Stalled
Thin ChannelSolution Path
4Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc. Applied Materials, Inc.
Thin-Channel Transistors
THIN-CHANNEL TRANSISTORSThe Dawn of a New Era
THIN-CHANNEL TRANSISTOR ARCHITECTURES DEMYSTIFIED A transistor serves as an on-off switch. An ideal switch
should have high current in its on-state and zero current
in its off-state. In reality, a transistor does leak current in its
off-state. As the size of the transistor shrinks, the current
in the off-state increases exponentially as does power
consumption. In 2001, transistor off-state current was
almost the same as on-state current, which prevented
scaling the channel length in accordance with Dennard’s
rule. Moore’s Law proceeded through gate pitch scaling,
but transistor length scaling had stalled (Figure 1).
CMOS transistor features scaled following simple rules
proposed by IBM’s Robert Dennard to predict changes
in physical properties, such as gate length, gate oxide
thickness, and junction depth needed to achieve higher
transistor density and performance.[1] During the
1990-era personal computing (PC) boom, demand
for increased device performance was such that gate
length was actually scaled faster than called for by
Dennard’s rules. Further, operating voltage reductions
specified by Dennard were not followed for system
considerations. Taken together, at the turn of the
century, these two deviations resulted in the alarming
forecast that high levels of integrated circuit power
consumption would place a fundamental constraint
on the further progression of Moore’s Law.
In response, new circuit and transistor technologies were invented to keep power consumption in check at a system level. The introduction of new materials into the transistor represented a major breakthrough. In 2003, Intel adopted strain engineering in high-volume manufacturing at the 90nm node to increase electron and hole mobility. To keep transistor off-state leakage within acceptable limits, gate length scaling slowed at subsequent nodes while progressively increasing strain levels enabled continuing increases in device performance. Similarly, the silicon dioxide gate dielectric had reached a thickness at which tunneling leakage currents were unacceptably high. In 2007, Intel replaced the 40-year-old silicon dioxide gate dielectric with a new insulator containing hafnium oxide and thereby started upon a new trajectory that allows for gate dielectric thickness scaling without compromise to leakage.
Today, leakage power continues to be the single biggest
challenge to sustaining Moore’s Law. Here, we discuss
the need for new transistor architectures that will
enable tomorrow’s lower-power smartphones, tablets,
and mobile PCs.
Figure 2. Comparison of
industry-standard planar
CMOS architecture with
new FinFET and UTB-SOI
architectures.
Figure 1. New transistor
designs are needed to make
possible continued gate
length scaling.
This roadblock would have stalled on-state drive current advances, if not for major technological breakthroughs in strain engineering and high-κ metal gates (HKMG). However, increasing device packing density according to Moore’s Law places renewed pressure on a means of scaling gate lengths below 25nm. For such short channel lengths, low off-state leakage current can be achieved only if the electric field applied to the transistor gate almost completely controls the electrons or holes moving in the channel. This can be achieved if the silicon body of the transistor channel is thin enough (<12nm).
The challenge of thinning the transistor channel has sparked distinct approaches amongst semiconductor
chip makers (Figure 2). One is to build a 3D FinFET (tri-
gate transistor) in which the channel is a “fin” of silicon
surrounded on three sides by a gate. A second extends
conventional planar scaling, but employs an ultra-thin
silicon channel that sits on an insulator, called an ultra-
thin body silicon-on-insulator or UTB-SOI.
In the late 1990s, Professor Chenming Hu of the
University of California at Berkeley led an ambitious
study to determine pathways forward.[2,3] This pioneering
study demonstrated the feasibility of both UTB-SOI and
FinFET structures at gate lengths less than 20nm and,
later, less than 10nm for FinFETs.
Figure 2
Planar CMOS FinFET UTB-SOI
Silicon Substrate
Gate
FinFET
Silicon Substrate
Gate
Fin
STI OxideSilicon Substrate
Buried Oxide
RaisedSource
RaisedDrain
Gate
Figure 1
Gat
e Le
ngth
(nm
)
Node (nm)
4 3 2 1.5 0.8 0.5 0.35 0.25 0.18 0.13 90 65 45 32 22 14 10 71
1000
100
10
Conventional Planar TransistorThin Channel TransistorDennard Rule
Gate LengthScaling Stalled
Thin ChannelSolution Path
5 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc.
Thin-Channel Transistors
The FinFET Approach
In May 2011, Intel announced a production-worthy
tri-gate solution for the 22nm technology node, which
had proved to have been a formidable manufacturing
challenge requiring a robust manufacturing process,
the ability to pattern the fins (width and height) with
extreme precision, and the process repeatability
and stability to do so for billions of transistors.[4]
Nevertheless, the effort proved worthwhile, yielding
dramatic low-voltage and low-power benefits.
FinFET architecture provides greater electrostatic
control of the conduction channel through the gate
electrode. The current flows in a small silicon fin having
an approximately rectangular cross-section with three
sides that are covered by the gate. Design estimates
call for 12nm fin widths and 24nm fin heights for a
channel length of 25nm. The multiple surface channels
(that carry on-state current) and all sub-surface leakage
paths (that carry off-state current) are in optimally close
proximity to a gate. A high on-state current results
from the cumulative contribution of multiple channel
surfaces. The undesired off-state power consumption
is greatly reduced because of effective control from
close-proximity gates. The FinFET design thereby
enables chips to serve the computing continuum from
high-speed servers to ultra-low-power smartphones.
The UTB-SOI Approach
Proponents of the UTB-SOI school of thought often
highlight the relative simplicity of this technology in
retaining existing planar structure, minimizing changes
needed in the manufacturing process flow.
UTB-SOI architecture consists of a thin silicon channel
held by an insulator on a silicon substrate. Design
estimates call for a silicon body thickness of 6nm for a
channel length of 25nm. This thickness requirement is
half the fin width of the FinFET architecture (Figure 3).
Here the current-carrying surface is along one plane only
due to the continuation of planar CMOS technology
(unlike the cumulative contribution seen from multiple
surfaces on FinFETs). The sub-surface leakage paths
(off-state current) are in close proximity to the gate
and are under its strong electrostatic control, greatly
reducing undesired off-state power consumption. The
UTB-SOI design thereby enables chips that are ideally
suited for ultra-low-power devices.
Figure 3. Comparison of
estimated channel length,
required thickness of FinFET
fins, and SOI thickness in
UTB-SOI at future technology
nodes.
MANUFACTURING FINFET ARCHITECTUREHere we highlight eight key challenges among the many
that arise when implementing FinFETs in production
schemes.
Forming Narrow, Uniform Fins
For acceptable performance and leakage characteristics
of a 20nm transistor, a fin will need to be 10nm wide
with a width uniformity of 1nm. Double patterning can
be employed to precisely define these thin, tall silicon
fins. Two approaches are being pursued in double
patterning: a litho-etch-litho-etch scheme and a self-
aligned double patterning scheme. In the latter, the
wafer is exposed to two different reticles offset from
one another to achieve a net effect of a smaller feature
size. It is desired that the etching process produce
vertical (90˚ angle) and smooth, void-free surfaces to
optimize electron transport in on-state current.
Figure 3
Dim
ensi
on (
nm)
Node (nm)
22 14 10 7
40
20
1086
4
2
1
Channel LengthFin Thickness in FinFETSOI Thickness in UTB-SOI
Preserving Narrow Fins
The precisely formed fins undergo many subsequent
thermal treatment, doping, film deposition, and film
removal process steps. It is critical that fin dimensions
remain unchanged throughout these steps, because any
deviation can adversely affect final device performance.
Low-temperature processing will be required to prevent
oxidation of fin surfaces. Doping of the fins should be
done in such a way that no crystal structure damage
occurs. Additionally, etching processes should precisely
and uniformly remove target materials along all surfaces
of the fin body without consuming the underlying
silicon fin.
Gate Stack Deposition
The layered material stack that includes gate insulator
and gate electrode is known as the gate stack. The gate
insulator and metal gate must almost perfectly conform
to the 3D body of the fin. Atomic layer deposition (ALD)
technology will likely be required to deposit such thin
and highly conformal film layers. Also, metals used
for nMOS and pMOS must be different to realize the
performance benefit of the “gate-last” HKMG integration
scheme employed today. For future technology nodes,
the fin pitch will need to be scaled down considerably
such that little space is left for insulator and metal film
deposition. It is conceivable that on an advanced 7nm
node transistor with a fin pitch of 30nm, the combined
thickness of gate insulator and gate metal layers will be
in the range of 12nm.
Capacitance Reduction
Given the thinness of the fins, inadequate silicon is
present to permit formation of a recessed structure;
hence the source drain contacts must be raised. Raised
structures are highly doped to lower their intrinsic
resistance and are located in close proximity to the
gate, creating unwanted capacitive coupling and power
drain. New materials that reduce coupling through
use of a lower dielectric constant layer between them
(e.g., a low-κ spacer) will be needed.
Forming Channel Extensions
The extension regions are part of the fin with the same
3D morphology. Doping processes normally performed
to lower the resistance of these regions now must
provide conformal coverage across all three surfaces of
6Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc. Applied Materials, Inc.
Thin-Channel Transistors
close-proximity gates. The FinFET design thereby
enables chips to serve the computing continuum from
high-speed servers to ultra-low-power smartphones.
The UTB-SOI Approach
Proponents of the UTB-SOI school of thought often
highlight the relative simplicity of this technology in
retaining existing planar structure, minimizing changes
needed in the manufacturing process flow.
UTB-SOI architecture consists of a thin silicon channel
held by an insulator on a silicon substrate. Design
estimates call for a silicon body thickness of 6nm for a
channel length of 25nm. This thickness requirement is
half the fin width of the FinFET architecture (Figure 3).
Here the current-carrying surface is along one plane only
due to the continuation of planar CMOS technology
(unlike the cumulative contribution seen from multiple
surfaces on FinFETs). The sub-surface leakage paths
(off-state current) are in close proximity to the gate
and are under its strong electrostatic control, greatly
reducing undesired off-state power consumption. The
UTB-SOI design thereby enables chips that are ideally
suited for ultra-low-power devices.
be employed to precisely define these thin, tall silicon
fins. Two approaches are being pursued in double
patterning: a litho-etch-litho-etch scheme and a self-
aligned double patterning scheme. In the latter, the
wafer is exposed to two different reticles offset from
one another to achieve a net effect of a smaller feature
size. It is desired that the etching process produce
vertical (90˚ angle) and smooth, void-free surfaces to
optimize electron transport in on-state current.
Figure 3
Dim
ensi
on (
nm)
Node (nm)
22 14 10 7
40
20
1086
4
2
1
Channel LengthFin Thickness in FinFETSOI Thickness in UTB-SOI
Preserving Narrow Fins
The precisely formed fins undergo many subsequent
thermal treatment, doping, film deposition, and film
removal process steps. It is critical that fin dimensions
remain unchanged throughout these steps, because any
deviation can adversely affect final device performance.
Low-temperature processing will be required to prevent
oxidation of fin surfaces. Doping of the fins should be
done in such a way that no crystal structure damage
occurs. Additionally, etching processes should precisely
and uniformly remove target materials along all surfaces
of the fin body without consuming the underlying
silicon fin.
Gate Stack Deposition
The layered material stack that includes gate insulator
and gate electrode is known as the gate stack. The gate
insulator and metal gate must almost perfectly conform
to the 3D body of the fin. Atomic layer deposition (ALD)
technology will likely be required to deposit such thin
and highly conformal film layers. Also, metals used
for nMOS and pMOS must be different to realize the
performance benefit of the “gate-last” HKMG integration
scheme employed today. For future technology nodes,
the fin pitch will need to be scaled down considerably
such that little space is left for insulator and metal film
deposition. It is conceivable that on an advanced 7nm
node transistor with a fin pitch of 30nm, the combined
thickness of gate insulator and gate metal layers will be
in the range of 12nm.
Capacitance Reduction
Given the thinness of the fins, inadequate silicon is
present to permit formation of a recessed structure;
hence the source drain contacts must be raised. Raised
structures are highly doped to lower their intrinsic
resistance and are located in close proximity to the
gate, creating unwanted capacitive coupling and power
drain. New materials that reduce coupling through
use of a lower dielectric constant layer between them
(e.g., a low-κ spacer) will be needed.
Forming Channel Extensions
The extension regions are part of the fin with the same
3D morphology. Doping processes normally performed
to lower the resistance of these regions now must
provide conformal coverage across all three surfaces of
the fins. If the doping is non-conformal, electrons tend
to accumulate in the highly doped region (path of least
resistance), leading to carrier crowding that results in
low on-state current. Current beam-line implantation
techniques are non-conformal as the sidewalls of the
fins receive a single dose while the top surface can
receive double the dose in the same time. New
technologies, such as plasma-based doping, vapor
phase deposition, or atomic layer doping will be needed
to provide the desired conformal doping.
Spacer Formation and Removal
A spacer is a dielectric layer located on the sides of
the gate stack serving multiple roles of electrical
isolation, chemical isolation, and dopant implant
protection for underlayers during transistor formation.
A silicon nitride film is commonly used for the spacer
material, and a lower-temperature process must be
developed than the current state-of-the-art. Etching of
the nitride spacer, an essential process step, now faces
a whole new level of complexity in the transition to
3D architecture. The nitride film must be removed
completely along all three sides of the fin (in one area),
but must remain on all three sides of the gate stack (in
an adjacent area) to mask the silicon gate for forming
the raised source and drain contacts using epitaxy.
Strain Engineering for Higher Mobility
Virtually all advanced planar transistors today employ
some form of strain engineering to enhance carrier
mobility. In FinFETs, strain-inducing capping layers have
been attempted using silicon nitride films deposited by
chemical vapor deposition (CVD). The magnitude and
type of strain (e.g., tensile versus compressive) may
be adjusted by modulating the deposition conditions,
especially temperature. However, the tight gate and fin
pitch dimensions limit the amount of strain that can be
induced by this approach. A second method involves
the use of a silicon-rich solid solution, such as silicon-
germanium (pMOS) or silicon-carbon (nMOS) as
source drain regions on the two ends of the channel to
induce a channel strain. The 3D nature of the fin makes
this strain transfer from source drain regions to the
channel less efficient than in planar devices. To continue
scaling, radical approaches in new channel materials,
such as indium-gallium-arsenide, silicon-germanium,
and pure germanium are actively being researched.
7 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc.
Thin-Channel Transistors
Figure 4. On-state current
for transistors with different
architectures based on best
research data published in
the literature.
Forming Silicide Contact for Source and Drain
Silicide materials are deposited at the interface between
the metal contacts and silicon source drain structures.
They are vital to lowering the interface resistance. The
3D fin requires that the silicide be conformally deposited
to form a good electrical connection.
MANUFACTURING UTB-SOI ARCHITECTUREFour key technology challenges must be overcome for
UTB-SOI architectures to be adopted in mainstream
production.
Thickness Control of the Thin Silicon Channel
For a 14nm device, the required silicon thickness is
approximately 5nm and any variation greater than 0.5nm
will negatively affect on-state current (performance)
and off-state current (power consumption). A 1nm
deviation towards thicker silicon channels can result in
as much as a tenfold increase in power consumption.
Capacitance Reduction
As in the case of finFET architecture, source drain
terminal contacts now have to be raised and are generally
highly doped to lower their intrinsic resistance. Being
raised, they lie in close proximity to the gate, leading
to undesired capacitive coupling between the two and
related power drain. New materials that reduce the
coupling through use of a lower dielectric constant layer
between them, such as a low-κ spacer, will be needed.
Forming Extension Regions for Source-Drain Structures
The extension regions are small areas at the tips of
the channel that are in contact with source and drain
terminals. They extract current from the channel and
pass it to the source and drain. They need to have
low electrical resistance to minimize power losses
and to retain a good on-state channel current for high
performance. Higher doping can lower the resistance;
however, ion beam implantation can cause crystalline
damage to these thin regions, worsening the resistance
problem. Novel doping techniques based on epitaxial
growth and controlled diffusion will be enabling
solutions for future nodes.
Gate Stack Deposition
The gate insulator electrical thickness required will be
extremely small, approximately 0.5nm for a 7nm device.
Precise control with minimal variability in thickness will
be a big challenge to overcome. ALD technology is likely
to be required to deliver the needed precision. The metal
gate electrodes must also be precisely manufactured,
requiring CVD or ALD technologies in addition to
physical vapor deposition technologies, to fill small
gaps and maintain good transistor performance.
REVOLUTION VERSUS EVOLUTION IN ADVANCED TRANSISTOR ARCHITECTURESFinFET and UTB-SOI were conceived a decade ago and
both effectively address the long-term quest for low off-
state current. Both have demonstrated the ability to scale
down the channel length to less than 25nm (Figure 4).
Implementing FinFET in high-volume manufacturing
requires chip makers to integrate complex process
technology solutions in patterning, new materials,
ultra-thin deposition of films, and conformal doping.
SOI technology has been in production for many years
at IBM and its alliance partners. UTB-SOI is an evolution
of this technology in which the silicon body thickness
will radically shrink from 30nm today to a possible
5nm in the future. The UTB-SOI approach continues
Figure 4
On
Cur
rent
(m
A/µ
m)
Channel Length (nm)
10 100
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
nFET
Planar (Production)FinFET (R&D)UTB-SOI (R&D)
On
Cur
rent
(m
A/µ
m)
Channel Length (nm)
10 100
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
pFET
Planar (Production)FinFET (R&D)UTB-SOI (R&D)
the planar CMOS architecture with minimal change in
manufacturing flow. A significant challenge, however,
lies in manufacturing the substrate as thickness variation
must be in the vanishingly small range of 0.5nm. This is
a key reason that UTB-SOI technology has not yet been
adopted for high-volume manufacturing.
A key difference between FinFET and UTB-SOI designs
is in the thickness of thin silicon body. The UTB-SOI
requires a silicon body two times thinner than that of the
FinFET, which leaves FinFET more flexibility to continue
scaling. One possible work-around for this issue is
for UTB-SOI to employ back-gate biasing, in which a
second gate is built below the buried oxide for greater
electrostatic control and reduced off-state current.
CONCLUSIONThe industry debate between FinFET and UTB-SOI
approaches is an example of the classic dilemma of
choosing revolution or evolution. Both approaches can
be excellent strategies. A revolutionary approach
requires large-scale investment, with greater risks by
radically changing the transistor design and process
flow, but it can also bring longer-term yield, performance,
and extendibility advantages. An evolutionary approach
reduces risk, required investment, and time-to-market.
REFERENCES[1] R. Dennard, et al., “Design of Ion-Implanted MOSFETs
with Very Small Physical Dimensions,” IEEE Journal
of Solid State Circuits, Vol. SC-9, No. 5, pp. 256-268,
October 1974.
[2] C. Hu, “Silicon Nanoelectronics for the 21st Century,”
Nanotechnology, pp. 113-116, June 1999.
[3] D. Hisamoto, et al., “FinFET—A Self-Aligned Double-
Gate MOSFET Scalable to 20nm,” IEEE Transactions
on Electron Devices, Vol. 47, No. 12, pp. 2320-2325,
December 2000.
[4] “Intel Reinvents Transistors Using New 3-D
Structure,” retrieved 5/4/2011,
http://newsroom.intel.com/community/intel_
newsroom/blog/2011/05/04/intel-reinvents-
transistors-using-new-3-d-structure.
8Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc. Applied Materials, Inc.
Thin-Channel Transistors
and to retain a good on-state channel current for high
performance. Higher doping can lower the resistance;
however, ion beam implantation can cause crystalline
damage to these thin regions, worsening the resistance
problem. Novel doping techniques based on epitaxial
growth and controlled diffusion will be enabling
solutions for future nodes.
Gate Stack Deposition
The gate insulator electrical thickness required will be
extremely small, approximately 0.5nm for a 7nm device.
Precise control with minimal variability in thickness will
be a big challenge to overcome. ALD technology is likely
to be required to deliver the needed precision. The metal
gate electrodes must also be precisely manufactured,
requiring CVD or ALD technologies in addition to
physical vapor deposition technologies, to fill small
gaps and maintain good transistor performance.
REVOLUTION VERSUS EVOLUTION IN ADVANCED TRANSISTOR ARCHITECTURESFinFET and UTB-SOI were conceived a decade ago and
both effectively address the long-term quest for low off-
state current. Both have demonstrated the ability to scale
down the channel length to less than 25nm (Figure 4).
Implementing FinFET in high-volume manufacturing
requires chip makers to integrate complex process
technology solutions in patterning, new materials,
ultra-thin deposition of films, and conformal doping.
SOI technology has been in production for many years
at IBM and its alliance partners. UTB-SOI is an evolution
of this technology in which the silicon body thickness
will radically shrink from 30nm today to a possible
5nm in the future. The UTB-SOI approach continues
Figure 4
On
Cur
rent
(m
A/µ
m)
Channel Length (nm)
10 100
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
nFET
Planar (Production)FinFET (R&D)UTB-SOI (R&D)
On
Cur
rent
(m
A/µ
m)
Channel Length (nm)
10 100
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
pFET
Planar (Production)FinFET (R&D)UTB-SOI (R&D)
the planar CMOS architecture with minimal change in
manufacturing flow. A significant challenge, however,
lies in manufacturing the substrate as thickness variation
must be in the vanishingly small range of 0.5nm. This is
a key reason that UTB-SOI technology has not yet been
adopted for high-volume manufacturing.
A key difference between FinFET and UTB-SOI designs
is in the thickness of thin silicon body. The UTB-SOI
requires a silicon body two times thinner than that of the
FinFET, which leaves FinFET more flexibility to continue
scaling. One possible work-around for this issue is
for UTB-SOI to employ back-gate biasing, in which a
second gate is built below the buried oxide for greater
electrostatic control and reduced off-state current.
CONCLUSIONThe industry debate between FinFET and UTB-SOI
approaches is an example of the classic dilemma of
choosing revolution or evolution. Both approaches can
be excellent strategies. A revolutionary approach
requires large-scale investment, with greater risks by
radically changing the transistor design and process
flow, but it can also bring longer-term yield, performance,
and extendibility advantages. An evolutionary approach
reduces risk, required investment, and time-to-market.
REFERENCES[1] R. Dennard, et al., “Design of Ion-Implanted MOSFETs
with Very Small Physical Dimensions,” IEEE Journal
of Solid State Circuits, Vol. SC-9, No. 5, pp. 256-268,
October 1974.
[2] C. Hu, “Silicon Nanoelectronics for the 21st Century,”
Nanotechnology, pp. 113-116, June 1999.
[3] D. Hisamoto, et al., “FinFET—A Self-Aligned Double-
Gate MOSFET Scalable to 20nm,” IEEE Transactions
on Electron Devices, Vol. 47, No. 12, pp. 2320-2325,
December 2000.
[4] “Intel Reinvents Transistors Using New 3-D
Structure,” retrieved 5/4/2011,
http://newsroom.intel.com/community/intel_
newsroom/blog/2011/05/04/intel-reinvents-
transistors-using-new-3-d-structure.
AUTHORSKhaled Ahmed is a distinguished member of technical
staff in the Silicon Systems Group at Applied Materials.
He holds his Ph.D. in electrical engineering from North
Carolina State University.
Balaji Chandrasekaran is a marketing programs manager
in the Silicon Systems Group at Applied Materials. He
earned his M.S. in materials science and engineering
from Northwestern University and an MBA from the
University of California at Berkeley.
Kathryn Ta is a senior director and head of marketing
for the Silicon Systems Group at Applied Materials.
She received her Ph.D. in chemical engineering from
the University of California at Berkeley.
Klaus Schuegraf is a corporate vice president and chief
technology officer of the Silicon Systems Group at
Applied Materials. He holds his Ph.D. in electrical
engineering from the University of California at Berkeley.
ARTICLE [email protected]
9 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc.
These challenges are at the forefront of the pursuit of
an ultimate gap-fill solution offering good film quality
at low thermal budgets. Similar requirements apply to
logic FinFET ILD, slit fill for vertical NAND, and DRAM
4F2 buried bit line (Figure 1). A recently developed fluid-
like, profile-insensitive CVD oxide is showing excellent
promise in satisfying these requirements in a variety of
applications.
FLOWABLE CVD DEPOSITIONFlowable CVD deposition occurs through the reaction
of a carbon-free silicon precursor and inorganic reactant
gas, resulting in condensation of a low-viscosity film
upon the wafer substrate. During deposition, the film
flows to the bottom of the gap, producing true bottom-
up, profile-insensitive film growth. This behavior was
tested using a re-entrant structure shape with a gap
width of 7nm and total height of 420nm created by
depositing silicon dioxide atop a 40nm shallow trench
isolation structure (Figure 2). The carbon-free chemistry
used creates high-density, non-porous silicon dioxide
and ensures the absence of fixed charge.
BLANKET FILM QUALITY STUDIESFilm composition of flowable CVD was assessed by
Fourier transform infra-red spectroscopy (FTIR) and
atomic emission spectroscopy (AES), while dielectric
breakdown (Vbd) was assessed with a mercury
probe (Figure 3). All measurements were performed
after <150˚C oxidative and additional inert ambient
thermal treatments.
SCALING DIELECTRIC GAP FILLWith Flowable Chemical Vapor Deposition
At the 2X nm node and beyond, gap fill becomes a
daunting challenge for conventional chemical vapor
deposition (CVD) given the combination of smaller feature
size, aggressive aspect ratios, re-entrant profiles, and
reduced tolerance for thermal and oxidative treatments.
A new low-temperature process clears these hurdles
by creating a fluid-like film capable of true bottom-up,
profile-insensitive, void-free fill. A high-quality film that
compares favorably with industry-standard high-density
plasma CVD silicon dioxide, it offers the additional
compelling advantage of enabling liner-free integration with
metal films commonly used in logic and memory devices.
Dielectric gap fill is a critical step in manufacturing
semiconductor devices. Chemical vapor deposition (CVD)
has historically enabled the void-free fill of pure, dense
oxides for metal isolation in semiconductors. CVD’s
excellent oxide quality, high breakdown voltage, and
good substrate adhesion have ensured low leakage and
the absence of parasitic capacitance. These properties
also preclude the integration challenges of alternative
solutions, including mobile and fixed charge. CVD
oxides have proven robust in post-processing steps,
including contact etch, chemical mechanical
planarization (CMP), and wet cleans, securing their
role in critical gap-fill applications.
With continued scaling of memory and logic devices, though, the combined challenge of smaller feature size and reduced tolerance for thermal and oxidative treatments must be addressed. These challenges are most evident in interlayer dielectric (ILD) in logic and dynamic random access memory (DRAM) for which a novel dielectric gap-fill approach is required by the 2x nm node.
In logic, the drive for optimal transistor performance motivates the continued use of nitride strain films that create a re-entrant gap between adjacent gates. Logic ILD0 has traditionally been filled with high-density plasma CVD (HDP-CVD) or sub-atmospheric CVD (SACVD). In the case of HDP-CVD, a high-density, inductively coupled plasma enhances the chemical deposition process while chemical and physical etch with high bias maintain an open gap for continued fill. While HDP-CVD remains a workhorse of the industry for both blanket and gap-fill applications, its dependence on line-of-sight for the physical etch restricts its use in high aspect ratio straight and re-entrant structures. SACVD employs a high partial pressure of ozone to achieve thermal deposition of conformal silicon-dioxide at low temperature (<550˚C). Void-free gap fill with a conformal film, however, requires a constant taper of the sidewall. In the case of sidewall angles exceeding 89˚ or a re-entrant structure profile, void-free fill cannot be achieved with this approach. Spin-on dielectrics have also been considered for the ILD0 application; however poor film quality, lack of film purity, and severe leakage issues after contact etch have restricted its adoption.
In DRAM, by the 2x nm node, gate pitch scaling in the periphery forms narrow gaps (<20nm) and high aspect ratios (>10:1) for ILD1. While reflow of boron- and phosphorous-doped SACVD glass (BPSG) films has ensured void-free fill at previous nodes, lower thermal budget (<700˚C) to address junction leakage challenges elsewhere on the device limits the continued use of BPSG films.
KEYWORDS
Gap Fill
Interlayer Dielectric
Flowable CVD
Low-Viscosity Film
Re-Entrant Profiles
Liner-Free Integration
Figure 3
Cur
rent
(A
)
1E-02
1E-04
1E-06
1E-08
1E-10
1E-12
1E-14
FCVDHDP Oxide
Field (MV/cm)
0 1 2 3 4 5 6 7 8 9 10
Vbd
Inte
nsit
y (a
u)
Wavelength (cm-1)
4000 3500 3000 2500 2000 1500 1000 500 0
(a) (b)
Si-O Bending(812 cm-1)
Si-O Rocking(477 cm-1)
Si-O Stretching(1085 cm-1)
10Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc. Applied Materials, Inc.
Flowable Gap Fill
These challenges are at the forefront of the pursuit of
an ultimate gap-fill solution offering good film quality
at low thermal budgets. Similar requirements apply to
logic FinFET ILD, slit fill for vertical NAND, and DRAM
4F2 buried bit line (Figure 1). A recently developed fluid-
like, profile-insensitive CVD oxide is showing excellent
promise in satisfying these requirements in a variety of
applications.
FLOWABLE CVD DEPOSITIONFlowable CVD deposition occurs through the reaction
of a carbon-free silicon precursor and inorganic reactant
gas, resulting in condensation of a low-viscosity film
upon the wafer substrate. During deposition, the film
flows to the bottom of the gap, producing true bottom-
up, profile-insensitive film growth. This behavior was
tested using a re-entrant structure shape with a gap
width of 7nm and total height of 420nm created by
depositing silicon dioxide atop a 40nm shallow trench
isolation structure (Figure 2). The carbon-free chemistry
used creates high-density, non-porous silicon dioxide
and ensures the absence of fixed charge.
BLANKET FILM QUALITY STUDIESFilm composition of flowable CVD was assessed by
Fourier transform infra-red spectroscopy (FTIR) and
atomic emission spectroscopy (AES), while dielectric
breakdown (Vbd) was assessed with a mercury
probe (Figure 3). All measurements were performed
after <150˚C oxidative and additional inert ambient
thermal treatments.
FTIR and AES studies were performed on 5000Å
deposits while dielectric breakdown was assessed on
2000Å films. The AES and FTIR demonstrate a pure,
stoichiometric Si-O film without detectable carbon or
nitrogen impurities. A dielectric breakdown test was
performed on 2000Å blanket wafers and demonstrated
high breakdown voltage (Vbd >8MV) with low
leakage (<1nA @ 1MV/cm). These results closely
matched industry-standard, high-quality HDP-CVD
silicon dioxide films that were used as a reference.
Figure 1
(a) (b) (c)
Figure 2
Applied Materials internal data(a) (b)
SCALING DIELECTRIC GAP FILLWith Flowable Chemical Vapor Deposition
With continued scaling of memory and logic devices, though, the combined challenge of smaller feature size and reduced tolerance for thermal and oxidative treatments must be addressed. These challenges are most evident in interlayer dielectric (ILD) in logic and dynamic random access memory (DRAM) for which a novel dielectric gap-fill approach is required by the 2x nm node.
In logic, the drive for optimal transistor performance motivates the continued use of nitride strain films that create a re-entrant gap between adjacent gates. Logic ILD0 has traditionally been filled with high-density plasma CVD (HDP-CVD) or sub-atmospheric CVD (SACVD). In the case of HDP-CVD, a high-density, inductively coupled plasma enhances the chemical deposition process while chemical and physical etch with high bias maintain an open gap for continued fill. While HDP-CVD remains a workhorse of the industry for both blanket and gap-fill applications, its dependence on line-of-sight for the physical etch restricts its use in high aspect ratio straight and re-entrant structures. SACVD employs a high partial pressure of ozone to achieve thermal deposition of conformal silicon-dioxide at low temperature (<550˚C). Void-free gap fill with a conformal film, however, requires a constant taper of the sidewall. In the case of sidewall angles exceeding 89˚ or a re-entrant structure profile, void-free fill cannot be achieved with this approach. Spin-on dielectrics have also been considered for the ILD0 application; however poor film quality, lack of film purity, and severe leakage issues after contact etch have restricted its adoption.
In DRAM, by the 2x nm node, gate pitch scaling in the periphery forms narrow gaps (<20nm) and high aspect ratios (>10:1) for ILD1. While reflow of boron- and phosphorous-doped SACVD glass (BPSG) films has ensured void-free fill at previous nodes, lower thermal budget (<700˚C) to address junction leakage challenges elsewhere on the device limits the continued use of BPSG films.
Figure 1. Dielectric
gap-fill technology faces
unprecedented challenges in
(a) logic FinFET ILD,
(b) slit fill for vertical NAND,
and (c) DRAM 4F2 buried
bit line.
Figure 2. (a) Flowable CVD
deposition enables partial fill
and (b) complete fill of features
with re-entrant profiles and
aggressive aspect ratios.
Figure 3. (a) FTIR spectroscopy
confirms the purity of the
flowable CVD oxide;
(b) high breakdown voltage
demonstrates superior
electrical performance.
Figure 3
Cur
rent
(A
)
1E-02
1E-04
1E-06
1E-08
1E-10
1E-12
1E-14
FCVDHDP Oxide
Field (MV/cm)
0 1 2 3 4 5 6 7 8 9 10
Vbd
Inte
nsit
y (a
u)
Wavelength (cm-1)
4000 3500 3000 2500 2000 1500 1000 500 0
(a) (b)
Si-O Bending(812 cm-1)
Si-O Rocking(477 cm-1)
Si-O Stretching(1085 cm-1)
11 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc.
Flowable Gap Fill
hydrofluoric acid diluted 100:1 in de-ionized water for
exposure times ranging from 1 minute to 8 minutes.
SEM cross-sections were generated for each sample
and the height of remaining oxide within the trench was
measured from the silicon-pad nitride interface and
plotted. A constant recess rate was measured (Figure 5),
confirming uniform film properties as a function of depth.
MATERIAL COMPATIBILITYTitanium-nitride (TiN) and tungsten (W) are metals
commonly used in logic and memory as electrodes,
contacts, and conductive lines. Both exhibit metal
oxide growth with low-temperature steam anneal. For
electrodes and narrow conductive lines, such as buried
bit and word lines employed in advanced DRAM, the
resistance change resulting from oxidation must be
restricted to ensure proper device function. The ability
to deposit an oxide film directly on a metal surface
without a nitride liner offers great freedom to reduce
integration complexity, implement novel device
architectures, and scale devices to narrower pitch.
The ability to integrate flowable CVD film without
nitride liner was assessed through high-resolution
transmission electron microscope (TEM) studies of
metal oxidation, using a 200kV FEI/Phillips W source
TEM with samples prepared by focused ion beam milling.
Physical vapor deposition was used to generate 400Å
TiN substrates and 400Å W substrates were generated
using metal oxide CVD on TiN substrates. Flowable
CVD was deposited and <150˚C oxidative and <600˚C
thermal treatments in inert ambient were applied.
Both TiN and W images demonstrate no change in
appearance following flowable CVD deposition and
post-treatment (Figure 6). For reference, an additional
W sample was subjected to a 400˚C, 60-minute steam
anneal; oxide formation appears clearly on the image
(Figure 6), demonstrating the sensitivity of TEM
methodology to the presence of oxide.
IN-TRENCH FILM QUALITY STUDIESWhile blanket properties of deposited films are useful, the blanket material is typically removed during CMP, hence it is important to confirm oxide formation and uniform film quality within structures as well. The in-trench film quality for flowable CVD was assessed using side-decorated SEMs, scanning transmission electron microscope electron energy loss spectroscopy (STEM-EELS), and analysis of the recess rate within the structures after CMP removal of the overburden. Before analysis, all deposits were subjected to <150˚C oxidative and <600˚C thermal treatment in inert ambient. Deposition was tuned to achieve completely void-free gap fill with an overburden of 1500Å or more.
The flowable CVD film was first characterized by SEM on 35nm x 250nm shallow trench isolation structures. Decoration with aggressive wet etchant (BOE 6:1, 6”) was applied following wafer cleave to highlight density variations within the film. As results showed reasonable in-trench film quality comparable to SACVD oxides of
similar thermal budget used in production today, analysis focused on STEM-EELS for detailed characterization.
STEM-EELS line scan analysis was performed at 0.5nm intervals from the substrate up through narrow (20nm wide, 200nm deep) trench structures to the top of the film. TEM samples were prepared by focused ion beam milling to a target thickness of 50nm. The areal density and relative atomic concentrations of the targeted elements (carbon, nitrogen, oxygen, and silicon) were extracted from the EELS data at each point and recorded in the profile measurements. Results demonstrate a pure silicon dioxide film to within detection limits of the test methodology, estimated to be on the order of two atomic percent for impurities (Figure 4).
To further test the film quality uniformity as a function of depth, flowable CVD was deposited and post-treated on shallow trench isolation structure wafers after which the overburden was removed by CMP, stopping on pad nitride. Samples were placed in a circulating bath of
Figure 4. STEM-EELS line
scan analysis reveals pure
silicon dioxide film within
the structure.
Figure 5. A constant recess
rate of oxide remaining within
shallow trench isolation
structures confirmed uniform
film properties as a function
of depth.
Figure 6
Applied Materials internal data
No W Oxidation
<200°C Oxide
W Oxide
PostPre
No TiN OxidationW W
<200°C Oxide Steam Anneals
TiN
SiO2
Figure 4
EELS Atomic Concentration ProfileScan Direction
SubstrateR
elat
ive
Com
posi
tion
(%
)
100
90
80
70
60
50
40
30
20
10
0
µm
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65
Nitride on Substrate No N Detected
OSiN
20nm, >10:1
Figure 5
CD45
CD70
0min 2min 4min 6min 8min
Rece
ss P
ositi
on (
nm) 100
0
-100
-200
-300
Etch Time (min)0 2 4 6 8
CD = 45nmCD = 70nm
Applied Materials internal data
12Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc. Applied Materials, Inc.
Flowable Gap Fill
hydrofluoric acid diluted 100:1 in de-ionized water for
exposure times ranging from 1 minute to 8 minutes.
SEM cross-sections were generated for each sample
and the height of remaining oxide within the trench was
measured from the silicon-pad nitride interface and
plotted. A constant recess rate was measured (Figure 5),
confirming uniform film properties as a function of depth.
MATERIAL COMPATIBILITYTitanium-nitride (TiN) and tungsten (W) are metals
commonly used in logic and memory as electrodes,
contacts, and conductive lines. Both exhibit metal
oxide growth with low-temperature steam anneal. For
electrodes and narrow conductive lines, such as buried
bit and word lines employed in advanced DRAM, the
resistance change resulting from oxidation must be
restricted to ensure proper device function. The ability
to deposit an oxide film directly on a metal surface
without a nitride liner offers great freedom to reduce
integration complexity, implement novel device
architectures, and scale devices to narrower pitch.
The ability to integrate flowable CVD film without
nitride liner was assessed through high-resolution
transmission electron microscope (TEM) studies of
metal oxidation, using a 200kV FEI/Phillips W source
TEM with samples prepared by focused ion beam milling.
Physical vapor deposition was used to generate 400Å
TiN substrates and 400Å W substrates were generated
using metal oxide CVD on TiN substrates. Flowable
CVD was deposited and <150˚C oxidative and <600˚C
thermal treatments in inert ambient were applied.
Both TiN and W images demonstrate no change in
appearance following flowable CVD deposition and
post-treatment (Figure 6). For reference, an additional
W sample was subjected to a 400˚C, 60-minute steam
anneal; oxide formation appears clearly on the image
(Figure 6), demonstrating the sensitivity of TEM
methodology to the presence of oxide.
CONCLUSIONFlowable CVD is a material that answers the need for profile-insensitive, void-free dielectric gap-fill oxide of re-entrant gaps of <7nm width and aspect ratios >50:1. Carbon-free chemistry creates a pure silicon dioxide whose properties compare favorably with industry-standard, high-quality HDP-CVD silicon dioxide. The low oxidative budget (<150˚C) process flow gives flowable CVD the compelling advantage of liner-free integration compatibility with W and TiN metal films.
ACKNOWLEDGEMENTSThe authors wish to acknowledge the support and guidance of Ajay Bhatnagar and Shankar Venkataraman of the Gap Fill division of the Dielectric Systems and Modules business unit at Applied Materials.
AUTHORS Tushar Mandrekar is a global product manager in the Silicon Systems Group at Applied Materials. He holds masters degrees in physics and materials science from the University of Illinois at Urbana-Champaign.
Jingmei Liang is a senior engineering manager in the Silicon Systems Group at Applied Materials. She earned her Ph.D. in chemical engineering and materials science from the University of Minnesota.
Abhijit Basu Mallick is a process engineer in the Silicon Systems Group at Applied Materials. He received his Ph.D. in chemistry from Cornell University and was a post-doctorate scholar at Stanford University.
Nitin Ingle is a technology director in the Silicon Systems Group at Applied Materials. He holds his Ph.D. in chemical engineering from the State University of New York in Buffalo.
ARTICLE [email protected]
PROCESS SYSTEM USED IN STUDYApplied Producer® Eterna™ CVD
similar thermal budget used in production today, analysis focused on STEM-EELS for detailed characterization.
STEM-EELS line scan analysis was performed at 0.5nm intervals from the substrate up through narrow (20nm wide, 200nm deep) trench structures to the top of the film. TEM samples were prepared by focused ion beam milling to a target thickness of 50nm. The areal density and relative atomic concentrations of the targeted elements (carbon, nitrogen, oxygen, and silicon) were extracted from the EELS data at each point and recorded in the profile measurements. Results demonstrate a pure silicon dioxide film to within detection limits of the test methodology, estimated to be on the order of two atomic percent for impurities (Figure 4).
To further test the film quality uniformity as a function of depth, flowable CVD was deposited and post-treated on shallow trench isolation structure wafers after which the overburden was removed by CMP, stopping on pad nitride. Samples were placed in a circulating bath of
Figure 6. Flowable CVD
offers potential for liner-free
integration with W and TiN
films.
Figure 6
Applied Materials internal data
No W Oxidation
<200°C Oxide
W Oxide
PostPre
No TiN OxidationW W
<200°C Oxide Steam Anneals
TiN
SiO2
Figure 4
EELS Atomic Concentration ProfileScan Direction
Substrate
Rel
ativ
e C
ompo
siti
on (
%)
100
90
80
70
60
50
40
30
20
10
0
µm
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65
Nitride on Substrate No N Detected
OSiN
20nm, >10:1
Figure 5
CD45
CD70
0min 2min 4min 6min 8min
Rece
ss P
ositi
on (
nm) 100
0
-100
-200
-300
Etch Time (min)0 2 4 6 8
CD = 45nmCD = 70nm
Applied Materials internal data
13 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc.
KEYWORDS
Chemical Mechanical Planarization
Process Control
Multi-Zone Polishing
Gate CMP
FinFETs
Contact CMP
CMP APPLICATIONS ARRIVE AT THE GATE STACKEnabling Advanced Transistors
shows the progression of CMP and the resultant gate
stack change in a three-platen polishing tool.
Polishing of the incoming oxide film begins on the first
platen as the uneven surface topography is planed
down to reach a desired remaining stop-in-film thickness
determined by a targeted incoming burden for the next
platen polish. On the second platen, the film becomes
more planar and the oxide film is removed, exposing
the nitride film surface, where the process stops owing
to the selective nature of the chemistry. Both a highly
selective ceria slurry process or a fixed-abrasive platen
process provide the desired oxide-to-nitride rate
selectivity; however, the latter also offers the inherent
advantage of avoiding dishing in larger trenches.[9] On
the third platen, the films are non-selectively polished
until the surface of the poly gate is exposed and the
nitride film is fully removed.
The stop-in-film and stop-on-film processes of the first
two platens are more established in comparison to the
process on the third platen, which is relatively new and
challenging in terms of its process requirements. The
third process requires an almost 1:1 removal rate between
oxide and nitride, a very low removal rate for poly (almost
stop-on-poly), and simultaneously optimizing multiple
parameters for the different materials. In addition, it
must result in very shallow field-oxide dishing and
minimal poly loss across various gate widths throughout
the die and the wafer.
From a device standpoint, the process on the third
platen determines the transistor gate height and thus
warrants extreme control of process variation. But the
two previous steps require the same degree of control,
because the variation originating from them compounds
the variability of the entire process. The thickness
uniformity variation in incoming lots (within die, within
wafer, and wafer to wafer) must be tightly controlled at
each platen.
A growing number of chemical mechanical planarization (CMP) applications are arriving at the transistor gate. They play a crucial technology-enabling role in sustaining Moore’s Law, first in creating flat reference planes for lithography depth-of-focus resolution and second in polish-back of materials in a damascene mode to form the patterned gate stack structures. Accompanying their growing adoption is the heightened requirement for extremely controlled process performance in terms of film thickness and uniformity that is being addressed by a portfolio of process control and multi-zone polishing-head technologies.
Since its introduction in the planarization of multi-level inter-layer dielectric (ILD) films for isolating aluminum wiring in the back end of line (BEOL), CMP has steadily expanded into multiple processes over the last two decades. The adoption of shallow trench isolation (STI) structures in place of local oxidation of silicon (LOCOS) gave rise to STI CMP, which was soon followed by CMP of tungsten films in transistor contacts for higher device yield.
Table 1
Then Now and Future
STI CMP STI CMP
ILD 1 (PMD) CMP High-Mobility Channels CMP*
Tungsten CMP Dummy Gate CMP (FinFET)*
Copper Damascene CMP
Dummy Gate-Open CMP (HKMG)*
Replacement Metal Gate CMP (HKMG)*
Tungsten CMP for Advanced Contacts*
Copper Damascene CMP
*Applications coming to the transistor gate stack
The transition from aluminum to copper wiring in BEOL
starting at the 130nm node effected a major change
when damascene copper CMP was introduced, soon
becoming the industry standard for multi-level inter-
connect fabrication. Today, CMP is seeing the
next big change as it becomes a transistor-enabling
technology. CMP processes now stop directly on the
gate stack, control its height, and play a more defining
role in transistor fabrication (Table 1).
Starting at 45nm, Intel introduced high-κ metal gate
structures (HKMG) in their transistors to sustain
Moore’s Law.[1] Two key planarization applications were
introduced at that time, namely the dummy gate-open
CMP and replacement metal gate CMP processes.[2]
The advent of FinFETs starting at 22nm[3] will add
a dummy gate planarization step that will be a key
technology enabler for the subsequent etching of the
3D structures.[4] Advanced DRAM memory devices are
employing a planarization process for the gate metal prior
to a recess etch step to form the buried gate structures.[5]
In addition, CMP applications in tungsten contact for
local interconnects also stop at the transistor gate. In
the future, high-mobility channel materials such as III-V
materials for nFET and germanium for pFET are likely
to be introduced and their incorporation into silicon will
require a damascene-style process to polish back these
novel materials.[6] This article reviews these new CMP
applications and their process challenges. As the
industry converges on the gate-last HKMG scheme,[7,8]
the first two of these applications appear poised to
become industry standards in the next few years.
DUMMY GATE-OPEN CMP FOR GATE-LAST HKMGWith the introduction of the gate-last scheme for
HKMG, the conventional ILD layer 1 CMP changes
from a single material (oxide) stop-in-film removal
to a multi-material removal process, resulting in the
opening of the dummy poly gate structure. Figure 1
Table 1. CMP applications
are multiplying as
the process takes on
a technology-enabling role.
Figure 1
Spac
er
SpacerPolyMask
S D
PMD
Spac
er
SpacerPolyMask
S D
PMD
Spac
er
SpacerPolyMask
S D
PMD
Incoming Stop in Oxide Stop on Nitride Poly Open
Stress LinerStress LinerStress LinerStress Liner
Poly
S D
PMD
SpacerSpac
er
14Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc. Applied Materials, Inc.
CMP APPLICATIONS ARRIVE AT THE GATE STACKEnabling Advanced Transistors
Expanding CMP Applications
shows the progression of CMP and the resultant gate
stack change in a three-platen polishing tool.
Polishing of the incoming oxide film begins on the first
platen as the uneven surface topography is planed
down to reach a desired remaining stop-in-film thickness
determined by a targeted incoming burden for the next
platen polish. On the second platen, the film becomes
more planar and the oxide film is removed, exposing
the nitride film surface, where the process stops owing
to the selective nature of the chemistry. Both a highly
selective ceria slurry process or a fixed-abrasive platen
process provide the desired oxide-to-nitride rate
selectivity; however, the latter also offers the inherent
advantage of avoiding dishing in larger trenches.[9] On
the third platen, the films are non-selectively polished
until the surface of the poly gate is exposed and the
nitride film is fully removed.
The stop-in-film and stop-on-film processes of the first
two platens are more established in comparison to the
process on the third platen, which is relatively new and
challenging in terms of its process requirements. The
third process requires an almost 1:1 removal rate between
oxide and nitride, a very low removal rate for poly (almost
stop-on-poly), and simultaneously optimizing multiple
parameters for the different materials. In addition, it
must result in very shallow field-oxide dishing and
minimal poly loss across various gate widths throughout
the die and the wafer.
From a device standpoint, the process on the third
platen determines the transistor gate height and thus
warrants extreme control of process variation. But the
two previous steps require the same degree of control,
because the variation originating from them compounds
the variability of the entire process. The thickness
uniformity variation in incoming lots (within die, within
wafer, and wafer to wafer) must be tightly controlled at
each platen.
On the first and third platens, in-situ endpoint
technology using broadband white light enables real-
time monitoring and endpoint control of the remaining
film thickness. In combination with real-time feedback
to the polishing heads, in-situ profile control technology
on the first and third platens can control within-wafer
uniformity. Motor torque endpoint (friction-based
sensing) on the second platen for accurate stop-on-
nitride can minimize over-polish and reduce dishing.
Within the dies, performance is determined by the
slurry, pads, or fixed-abrasive web used. Multi-zone
polishing-head technology achieves the required
center-to-edge wafer uniformity tuning and control.
The combination of endpoint capabilities, process
monitoring and control, and multi-zone polishing
pressure control is crucial for achieving the necessary
precision.
REPLACEMENT METAL GATE CMP FOR GATE-LAST HKMGA second CMP step needed in HKMG fabrication is
the metal gate process in which the dummy poly gate
material is replaced by aluminum. Here CMP is an
enabling technology in a damascene mode in which
the deposited metal is fully polished back to isolate
the individual transistor gates. Aluminum metal is
employed as the gate electrode and has an incoming
topography from the PVD metal gap-fill process into
the gate trenches. The films are planarized and polished
back to remove the work function metals and barrier
materials from the field-oxide areas, leaving the
aluminum metal fill in the trenches (Figure 2).
From a device standpoint, aluminum CMP stops on
the gate and determines the gate height. Therefore,
extreme control of process variation for thickness and
uniformity is needed within die, within wafer, and wafer
to wafer. Real-time profile control can be employed to
govern the polishing process at each platen. For the
metal removal, an in-pad eddy-current sensor that
senses a signal proportional to the amount of metal
The transition from aluminum to copper wiring in BEOL
starting at the 130nm node effected a major change
when damascene copper CMP was introduced, soon
becoming the industry standard for multi-level inter-
connect fabrication. Today, CMP is seeing the
next big change as it becomes a transistor-enabling
technology. CMP processes now stop directly on the
gate stack, control its height, and play a more defining
role in transistor fabrication (Table 1).
Starting at 45nm, Intel introduced high-κ metal gate
structures (HKMG) in their transistors to sustain
Moore’s Law.[1] Two key planarization applications were
introduced at that time, namely the dummy gate-open
CMP and replacement metal gate CMP processes.[2]
The advent of FinFETs starting at 22nm[3] will add
a dummy gate planarization step that will be a key
technology enabler for the subsequent etching of the
3D structures.[4] Advanced DRAM memory devices are
employing a planarization process for the gate metal prior
to a recess etch step to form the buried gate structures.[5]
In addition, CMP applications in tungsten contact for
local interconnects also stop at the transistor gate. In
the future, high-mobility channel materials such as III-V
materials for nFET and germanium for pFET are likely
to be introduced and their incorporation into silicon will
require a damascene-style process to polish back these
novel materials.[6] This article reviews these new CMP
applications and their process challenges. As the
industry converges on the gate-last HKMG scheme,[7,8]
the first two of these applications appear poised to
become industry standards in the next few years.
DUMMY GATE-OPEN CMP FOR GATE-LAST HKMGWith the introduction of the gate-last scheme for
HKMG, the conventional ILD layer 1 CMP changes
from a single material (oxide) stop-in-film removal
to a multi-material removal process, resulting in the
opening of the dummy poly gate structure. Figure 1
Figure 1. Dummy gate-open
CMP sequence through
polysilicon gate open, ready
for polysilicon removal.
Figure 1
Spac
er
SpacerPolyMask
S D
PMD
Spac
er
SpacerPolyMask
S D
PMD
Spac
erSpacerPoly
Mask
S D
PMD
Incoming Stop in Oxide Stop on Nitride Poly Open
Stress LinerStress LinerStress LinerStress Liner
Poly
S D
PMD
SpacerSpac
er
15 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc.
Expanding CMP Applications
a parameter that must be tightly controlled die to die,
within wafer, and wafer to wafer for consistent
transistor performance. Hence, the post-CMP remaining
film thickness (stopping within-film) and uniformity
control is paramount and real-time profile control
technology can be an enabler.
As in the case of the gate-last HKMG application, a
novel in-pad sensor measures the eddy-current signal,
which is proportional to the amount of metal remaining.
This capability has been developed recently for
tungsten[11] and provides a high degree of resolution.
The DRAM industry is researching a transition to 4F2
cell size, which will employ a buried bit-line architecture
(BBL) in addition to BWL.[12] BBL creates an additional
application for tungsten CMP with the same set of
challenges as those noted above.
CONTACT CMP FOR LOCAL INTERCONNECTSIn 2009, Intel announced their second-generation
contacts with local interconnect technology for their
32nm node microprocessor.[13] In this device, the
tungsten contacts are polished down to the transistor
gate level, determining the gate height (Figure 5).
These trench-design contacts have lower resistance.
Similar to the gate-last HKMG application, this
application is a damascene process in which tungsten
and the barrier metals are polished back to endpoint on
oxide (Figure 5). Tight control of thickness and uniformity
variation are paramount to the manufacturability of this
application. As in the BWL application, real-time profile
control can enable the required precision of thickness
and uniformity control.
FUTURE CMP APPLICATIONS IN HIGH-MOBILITY CHANNEL MATERIALSResearch is actively being pursued in quantum well field
effect transistors (QWFET), which are seen as promising
candidates for next-generation transistors.[14] These
transistors can enable high-speed performance at very
low supply voltages, offering promise of a new era of
ultra-low-power computing.
remaining is used and adjusts polishing-head pressure
to control thickness and uniformity. Within-die uniformity
is determined by the selection of appropriate slurry and
polishing pads.
Aluminum is a softer metal than copper; consequently
defectivity (e.g., scratching) control is more challenging.
The polishing process should not leave aluminum
residue or particles in the field oxide and should also be
selective to minimize field-oxide loss. It must also
completely remove the work function and barrier
materials in the field while producing low topography
from dishing and erosion within the die. A three-platen
CMP configuration offers considerable flexibility on
consumables and process control to address these
multiple requirements.
DUMMY GATE CMP FOR FINFETSThe transition from planar CMOS transistor designs to
FinFETs creates a new CMP step in the planarization of
dummy gate polysilicon films. In the planar transistor,
the deposited polysilicon film has a flat topography
requiring no CMP, but in FinFET designs, the same
deposited film has an uneven surface topography
that must be planarized before gate etch. This uneven
topography arises from a prior process in forming the
silicon fins wherein the recesses of the STI oxide film
create an underlying topography for the subsequent
polysilicon film deposition.
The primary value of this CMP application is to create
a flat reference plane with depth-of-focus resolution
to enable critical lithography exposure and gate stack
etch (Figure 3). Because it stops on the transistor gate,
it controls the gate height. Over-polishing can cause
too short a gate and under-polishing can cause too tall
a gate, which can affect the current carrying ability of
the word line. Post-polish gate height must therefore
be stringently controlled within a range less than 50Å,
both within wafer and wafer to wafer.[3]
In-situ endpoint technology with broadband white light
can offer the necessary control. The polysilicon film
has a high refractive index and high reflected signal
intensity. The broadband light spectrum collected
from in-situ metrology can provide fine resolution to
accurately stop within the film at the targeted thickness.
The combination of endpoint metrology with multi-zone
polishing pressure can yield a tight within-wafer range
in real time. Using pads and slurries that offer high
planarization efficiency achieves the desired within-die
thickness control.
GATE CMP FOR BURIED WORD LINE DRAM MEMORYRecently, the DRAM industry has begun to migrate
to buried word line (BWL) transistors to gain the
advantages of reduced parasitic capacitance (in both
bit line and word line directions), smaller die size, and
low-power operation.[10] CMP is an enabling technology
in planarization of the metal gate film prior to the
recess etch process in BWL transistor fabrication.[5]
Tungsten or titanium nitride (TiN) films are the leading
candidates for the gate. They present an uneven surface
topography following the gap-fill process into the silicon
trenches. Forming a flat reference plane with CMP is
critical to enable a precisely controlled etch process
(Figure 4). This process has a direct impact on the final
height of the buried metal gate inside the trenches,
Figure 3. In FinFET fabrication,
CMP creates a flat reference
plane with depth-of-focus
resolution lithography
exposure and gate stack etch.
Figure 3
Poly
STI
Si
STI
Si
Poly
STI
Si
Figure 4
Source: References 5,10.
Incoming WaferCMP Stop with
Thin Tungsten RemainingTungsten Structures Etched
for BWL Formation
BarrierBarrier
Barrier
W W W
Figure 2
Spac
er
Spacer
S D
Post-Aluminum Gap Fill
PMD
Al
Stress Liner
Barrier
WorkFunctionMetal
Spac
er
Spacer
S D
Stop in Aluminum
PMDAlStress Liner
Barrier
Spac
er
Spacer
S D
Stop on Oxide
PMDAlStress Liner
WorkFunctionMetal
Figure 2. Replacement
metal gate CMP sequence
planarizing incoming
aluminum film through
gate isolation.
16Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc. Applied Materials, Inc.
Expanding CMP Applications
a parameter that must be tightly controlled die to die,
within wafer, and wafer to wafer for consistent
transistor performance. Hence, the post-CMP remaining
film thickness (stopping within-film) and uniformity
control is paramount and real-time profile control
technology can be an enabler.
As in the case of the gate-last HKMG application, a
novel in-pad sensor measures the eddy-current signal,
which is proportional to the amount of metal remaining.
This capability has been developed recently for
tungsten[11] and provides a high degree of resolution.
The DRAM industry is researching a transition to 4F2
cell size, which will employ a buried bit-line architecture
(BBL) in addition to BWL.[12] BBL creates an additional
application for tungsten CMP with the same set of
challenges as those noted above.
CONTACT CMP FOR LOCAL INTERCONNECTSIn 2009, Intel announced their second-generation
contacts with local interconnect technology for their
32nm node microprocessor.[13] In this device, the
tungsten contacts are polished down to the transistor
gate level, determining the gate height (Figure 5).
These trench-design contacts have lower resistance.
Similar to the gate-last HKMG application, this
application is a damascene process in which tungsten
and the barrier metals are polished back to endpoint on
oxide (Figure 5). Tight control of thickness and uniformity
variation are paramount to the manufacturability of this
application. As in the BWL application, real-time profile
control can enable the required precision of thickness
and uniformity control.
FUTURE CMP APPLICATIONS IN HIGH-MOBILITY CHANNEL MATERIALSResearch is actively being pursued in quantum well field
effect transistors (QWFET), which are seen as promising
candidates for next-generation transistors.[14] These
transistors can enable high-speed performance at very
low supply voltages, offering promise of a new era of
ultra-low-power computing.
QWFETs employ high-mobility materials as a
replacement for silicon in the transistor channel. III-V
group materials are being considered for n-type channel
field effect transistors (nFET) due to their exceptionally
high electron mobility and germanium is being
considered for p-type channel field effect transistors
(pFET) due to its high hole mobility relative to silicon.[15]
CMP is expected to be an enabling technology in the
heterogeneous integration of these new materials onto
silicon substrates.
Figure 5
nMOS pMOS
W WW W
Source: Reference 13.
IMEC (Interuniversity Microelectronics Centre) is
presently developing a possible pFET flow for integration
with a CMP process.[6] In pFET fabrication, the active
silicon areas formed by the STI process are recess
etched to enable epitaxial growth of germanium in its
place (the replacement channel), as shown in Figure 6.
Figure 6
Source: Reference 6.
SiO2
Si
SiO2
Si
SiO2
Ge
Si
SiO2
Ge
Si
too short a gate and under-polishing can cause too tall
a gate, which can affect the current carrying ability of
the word line. Post-polish gate height must therefore
be stringently controlled within a range less than 50Å,
both within wafer and wafer to wafer.[3]
In-situ endpoint technology with broadband white light
can offer the necessary control. The polysilicon film
has a high refractive index and high reflected signal
intensity. The broadband light spectrum collected
from in-situ metrology can provide fine resolution to
accurately stop within the film at the targeted thickness.
The combination of endpoint metrology with multi-zone
polishing pressure can yield a tight within-wafer range
in real time. Using pads and slurries that offer high
planarization efficiency achieves the desired within-die
thickness control.
GATE CMP FOR BURIED WORD LINE DRAM MEMORYRecently, the DRAM industry has begun to migrate
to buried word line (BWL) transistors to gain the
advantages of reduced parasitic capacitance (in both
bit line and word line directions), smaller die size, and
low-power operation.[10] CMP is an enabling technology
in planarization of the metal gate film prior to the
recess etch process in BWL transistor fabrication.[5]
Tungsten or titanium nitride (TiN) films are the leading
candidates for the gate. They present an uneven surface
topography following the gap-fill process into the silicon
trenches. Forming a flat reference plane with CMP is
critical to enable a precisely controlled etch process
(Figure 4). This process has a direct impact on the final
height of the buried metal gate inside the trenches,
Figure 5. Contact CMP for
local interconnects polishes
tungsten down to gate level,
setting gate height.
Figure 4. In BWL transistors,
CMP produces a flat plane
of reference and controlled
incoming film thickness for
the subsequent etch process.
Poly
STI
Si
STI
Si
Poly
STI
Si
Figure 4
Source: References 5,10.
Incoming WaferCMP Stop with
Thin Tungsten RemainingTungsten Structures Etched
for BWL Formation
BarrierBarrier
Barrier
W W WSpac
er
Spacer
S D
Post-Aluminum Gap Fill
PMD
Al
Stress Liner
Barrier
WorkFunctionMetal
Spac
er
Spacer
S D
Stop in Aluminum
PMDAlStress Liner
Barrier
Spac
er
Spacer
S D
Stop on Oxide
PMDAlStress Liner
WorkFunctionMetal
Figure 6. A CMP process is
being developed to integrate
germanium channels into
silicon.
17 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc.
Expanding CMP Applications
The overgrowth of germanium outside the trench must
be removed by CMP to maintain a flat reference plane
and define the pattern. A similar scheme is conceivable
for III-V materials grown in the nFET regions.
Requirements for this CMP application include chemistry
development for polish, selective stop-on-oxide slurry
behavior, cleaning chemistry post-polish, accurate
endpoint capability to prevent over- and under-polishing,
and extremely low defectivity. The application is at
the transistor gate stack level, requiring tight process
control as emphasized above, which will be enabled
by in-situ platen endpoint technology and multi-zone
polishing technology.
CONCLUSIONCMP now plays a pivotal role in sustaining Moore’s
Law. CMP applications enable advanced transistor
fabrication with HKMG, FinFET, advanced contacts for
local interconnect, and high-mobility channel materials
in advanced logic, and BWL structures in advanced
DRAM. In transistor fabrication, CMP must now meet
specifications for thickness and uniformity that are
notably stricter than have previously been applied to
such applications. Process control technologies that
offer real-time monitoring and control at the platen
level will therefore play a much more central role in the
coming years than ever before.
REFERENCES[1] K. Mistry, “A 45nm Logic Technology with High-κ
+ Metal Gate Transistors, Strained Silicon, 9 Cu
Interconnect Layers, 193nm Dry Patterning, and
100% Pb-free Packaging,” IEDM Technical Digest,
pp. 247–250, 2007.
[2] J.M. Steigerwald, “Chemical Mechanical Polish: The
Enabling Technology,” International Electron Devices
Meeting, IEEE International, pp. 1-4, Dec. 15-17, 2008.
[3] “Intel Reinvents Transistors Using New 3-D
Structure,” retrieved 5/4/2011,
http://newsroom.intel.com/community/intel_
newsroom/blog/2011/05/04/intel-reinvents-
transistors-using-new-3-d-structure.
[4] Y. Moon, “Chemical Mechanical Polishing for Front-
End-of-Line Integration in 22nm Technology and
Beyond,” International Conference on Planarization/
CMP Technology (ICPT), pp. 183-189, Nov. 2009.
[5] Chipworks Report, “Samsung K4B2G0846D-HCH9 32nm 2Gbit DDR3 SDRAM,” Jan. 2011.
[6] P. Ong, “CMP of Ge for High-Mobility Channels,” International Conference on Planarization/CMP Technology (ICPT), Nov. 14-17, 2010.
[7] “TSMC Adds High-κ Metal Gate Low-Power Process to 28nm Road Map,” TSMC, retrieved 08/24/2009.
[8] http://www.eetimes.com/electronics-news/4212271/IBM--fab-club--switches-high-k-camps.
[9] J. Diao, “ILD0 CMP: Technology Enabler for High-κ Metal Gate in High Performance Logic Devices,” Advanced Semiconductor Manufacturing Conference (ASMC), 2010 IEEE/SEMI, pp. 247-250, July 11-13, 2010.
[10] T. Schloesser, “6F2 Buried Word Line DRAM Cell for 40nm and Beyond,” Electron Devices Meeting, IEEE International, pp. 1-4, Dec. 15-17, 2008.
[11] Applied Materials Reflexion GT Product Launch Technical Briefing: http://www.appliedmaterials.com/sites/default/files/ReflexionGTW-tech-briefing_0.pdf.
[12] H. Chung, “Novel 4F2 DRAM Cell with Vertical Pillar Transistor (VPT),” Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European, pp. 211-214, Sept. 12-16, 2011.
[13] P. Packan, et al., “High Performance 32nm Logic Technology Featuring 2nd Generation High-κ + Metal Gate Transistors,” Electron Devices Meeting, IEEE International, slide 24, Dec. 7-9, 2009, http://download.intel.com/technology/architecture-silicon/32nm/2009_32nm_Logic_Presentation.pdf.
[14] R. Chau, “III-V on Silicon for Future High Speed and Ultra-Low-Power Digital Applications: Challenges and Opportunities,” Proceedings CS-MANTECH Dig., p. 1-4, 2008.
[15] S.M. Sze, “High-Speed Semiconductor Devices,” Wiley, New York, 1990.
AUTHORSBalaji Chandrasekaran is a marketing programs manager in the Silicon Systems Group at Applied Materials. He holds his M.S. in materials science and engineering from Northwestern University and an MBA from the University of California at Berkeley.
ARTICLE [email protected]
ENABLING SPIN-TRANSFER TORQUE MAGNETIC MEMORY for the 2x nm Node and Beyond
Satisfying evolving functionality and form factor desires
of the burgeoning mobile consumer devices market will
place challenging demands on the integrated circuits that
enable them, including demands for memory that performs
faster, has larger capacity, and uses less power. These
demands are stimulating pursuit of an “ultimate solution”
to replace current Flash and random access memory (RAM).
Among emerging technologies, spin-transfer torque (STT)
magneto-resistive RAM shows great promise. Recent
advances in processes throughout the fabrication sequence
can meet the stringent requirements imposed by the new
materials and architecture in this new technology and can
help make production-scale implementation viable.
For 40 years, integrated circuit feature geometries have
been steadily shrinking, consistent with the prediction
known as Moore’s Law. This trend has driven the
evolution of every aspect of semiconductor technology
in pursuit of faster and more sophisticated performance,
greater storage capacity and endurance, lower power,
and less cost. In memory technology, volatile dynamic
random access memory (DRAM) and non-volatile
complementary metal-oxide semiconductor (CMOS)
Flash memory devices have successfully scaled over
multiple technology nodes, with Flash proliferating
throughout consumer and commercial electronics, such
as cell phones, digital cameras, solid-state devices,
wireless communications, and medical products.
18Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc. Applied Materials, Inc.
[5] Chipworks Report, “Samsung K4B2G0846D-HCH9 32nm 2Gbit DDR3 SDRAM,” Jan. 2011.
[6] P. Ong, “CMP of Ge for High-Mobility Channels,” International Conference on Planarization/CMP Technology (ICPT), Nov. 14-17, 2010.
[7] “TSMC Adds High-κ Metal Gate Low-Power Process to 28nm Road Map,” TSMC, retrieved 08/24/2009.
[8] http://www.eetimes.com/electronics-news/4212271/IBM--fab-club--switches-high-k-camps.
[9] J. Diao, “ILD0 CMP: Technology Enabler for High-κ Metal Gate in High Performance Logic Devices,” Advanced Semiconductor Manufacturing Conference (ASMC), 2010 IEEE/SEMI, pp. 247-250, July 11-13, 2010.
[10] T. Schloesser, “6F2 Buried Word Line DRAM Cell for 40nm and Beyond,” Electron Devices Meeting, IEEE International, pp. 1-4, Dec. 15-17, 2008.
[11] Applied Materials Reflexion GT Product Launch Technical Briefing: http://www.appliedmaterials.com/sites/default/files/ReflexionGTW-tech-briefing_0.pdf.
[12] H. Chung, “Novel 4F2 DRAM Cell with Vertical Pillar Transistor (VPT),” Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European, pp. 211-214, Sept. 12-16, 2011.
[13] P. Packan, et al., “High Performance 32nm Logic Technology Featuring 2nd Generation High-κ + Metal Gate Transistors,” Electron Devices Meeting, IEEE International, slide 24, Dec. 7-9, 2009, http://download.intel.com/technology/architecture-silicon/32nm/2009_32nm_Logic_Presentation.pdf.
[14] R. Chau, “III-V on Silicon for Future High Speed and Ultra-Low-Power Digital Applications: Challenges and Opportunities,” Proceedings CS-MANTECH Dig., p. 1-4, 2008.
[15] S.M. Sze, “High-Speed Semiconductor Devices,” Wiley, New York, 1990.
AUTHORSBalaji Chandrasekaran is a marketing programs manager in the Silicon Systems Group at Applied Materials. He holds his M.S. in materials science and engineering from Northwestern University and an MBA from the University of California at Berkeley.
ARTICLE [email protected]
ENABLING SPIN-TRANSFER TORQUE MAGNETIC MEMORY for the 2x nm Node and Beyond
KEYWORDS
Magneto-Resistive RAM
STT-MRAM
Emerging Memory
Magnetic Films
Satisfying evolving functionality and form factor desires
of the burgeoning mobile consumer devices market will
place challenging demands on the integrated circuits that
enable them, including demands for memory that performs
faster, has larger capacity, and uses less power. These
demands are stimulating pursuit of an “ultimate solution”
to replace current Flash and random access memory (RAM).
Among emerging technologies, spin-transfer torque (STT)
magneto-resistive RAM shows great promise. Recent
advances in processes throughout the fabrication sequence
can meet the stringent requirements imposed by the new
materials and architecture in this new technology and can
help make production-scale implementation viable.
For 40 years, integrated circuit feature geometries have
been steadily shrinking, consistent with the prediction
known as Moore’s Law. This trend has driven the
evolution of every aspect of semiconductor technology
in pursuit of faster and more sophisticated performance,
greater storage capacity and endurance, lower power,
and less cost. In memory technology, volatile dynamic
random access memory (DRAM) and non-volatile
complementary metal-oxide semiconductor (CMOS)
Flash memory devices have successfully scaled over
multiple technology nodes, with Flash proliferating
throughout consumer and commercial electronics, such
as cell phones, digital cameras, solid-state devices,
wireless communications, and medical products.
Flash memory comes in two forms: NOR and NAND.
The former can be likened to a computer’s memory,
while the latter is similar to a hard disk. In response to
high demand for increased capacity in recent years,
NAND has scaled more aggressively as it is a simpler
structure. However, in spite of such adaptations as
multi-level cells and three-dimensional (3D) transistor
stacking, leading-edge Flash technology is facing
mounting challenges of limited endurance, high power
consumption in write mode, and slow write speed.
DRAM also faces speed and power disadvantages and,
further, is incompatible with embedded applications
that help reduce power usage and speed response time.
Static RAM (SRAM) fares even worse, with power
usage and leakage issues.[1] In addition, signal-noise
ratio, alpha-immunity, variability, and size will challenge
SRAM as it scales further. Power consumption is one
of the top issues affecting mobile and data center
applications while memory performance is becoming
the key bottleneck limiting system performance as
applications become more data-centric and less
computational.
EMERGING MEMORY TECHNOLOGYDuring the past decade, several new and more scalable
RAM technologies (e.g., ferroelectric, magnetic, phase-
change) have been under development as potential
successors to Flash, DRAM, and SRAM. Of these, a
form of magneto-resistive RAM (MRAM) known as
spin-transfer torque, or STT-MRAM, appears to have
fewer limitations than the others, offering non-volatility,
extended scalability, excellent endurance (exceeding
1015 cycles) at lower power, and fast read and write
speeds.[2-5] Further, its physical size gives it a major
advantage over current SRAM. Figure 1 is a diagrammatic
representation of an STT-MRAM cell.
Applied Materials, Inc.19 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc.
Emerging STT-MRAM
Figure 1
Silicon Substrate
Bit Line
Source Drain
MTJ
6F2
Gate
Source: Reference 1.
Figure 2
Bit Line
Source Line
Selection TransistorWord Line
Current “0”
MTJ
Bit Line
Source Line
Word Line
“1”
Free LayerBarrierFixed Layer
Source: Reference 2.
Figure 3
Wri
te C
urre
nt (
µA)
Device Area (µm2)
0.01 0.02 0.03
500
400
300
200
100
0
DMTJJc0~1.4MA/cm2
Source: Reference 1.
STT-MRAM employs electron spin associated with magnetism. An electric current from an underlying CMOS transistor is polarized by aligning the spin direction of electrons passing through the magnetic tunnel junction (MTJ) at the core of the bit cell (Figure 2). The spin transforms the state of the MTJ from anti-parallel (1) to parallel (0) and vice versa, with current flowing in opposite directions. The MTJ stack consists of a top electrode, a (ferromagnetic) free layer where information is stored, a tunneling insulator layer, fixed ferromagnetic reference layers, and a bottom electrode. Current running through the reference layer polarizes its electrons, which then affect those of the free layer, leading to the parallel and anti-parallel configurations. Writing occurs when the spin-polarized current changes the magnetic orientation of the data storage layer; the resistance difference of this layer is used for reading. Applying the spin-polarized current vertically through the MTJ overcomes a major drawback of conventional MRAM, which is the increase in switching current as the technology scales down.[6]
As the CMOS transistor has evolved from a planar structure to a 3D one, the drivability of a transistor in small geometry has exceeded 1mA/µm in a logic circuit, where µm represents the gate width of 1µm. These findings have been widely reported in the literature, especially for high-κ/metal gate CMOS. Figure 3 shows the write current as a function of STT-RAM cell area, from which one can project that if current density of 1.4MA/cm2 is scaled down to approximately 20nm, 6.4µA will be required for programming a 20nm by 20nm STT-MRAM cell. However, as memory arrays operate with random individual access and most of the inactive transistors are in the off state during the access stage, the transistor off current is also very important for array operation. For a lower off current transistor, the on current will be correspondingly reduced. Hence, reducing STT-MRAM cell programming current density further by a factor of 2-5 will increase device margin and functionality, while lowering overall cost.
Because it uses a current running through the cell, the required writing current through the smaller MTJ decreases (Figure 3), in turn reducing power consumption as the device becomes smaller. In addition, STT-MRAM uses only 1.2V internally and can therefore operate on a single 1.5V battery as opposed to DRAM and Flash that need charge pumps to satisfy their higher voltage requirements (e.g., Flash requires 10-12V for writing).
Figure 1. STT-MRAM cell
structure is simpler and
more compact than a
conventional MRAM cell.
Figure 3. STT-MRAM write
current usage demonstrates
the technology’s scalability.
Figure 2. Current running
through the fixed layer of the
MTJ polarizes the electrons,
in turn affecting those of the
free layer to produce parallel
and anti-parallel configurations.
To be viable, STT-MRAM must clearly demonstrate that
it can migrate to smaller and denser memory size with
lower power consumption as the underlying CMOS
logic technology scales down. DRAM and SRAM are on
track to scale to 20nm, with well-known device function
and cost parity. For STT-MRAM to be competitive with
these well-established technologies, it must demonstrate
functional scalability to 10nm. Research by the hard
disk drive industry and others[5] has confirmed that a
10nm-sized magnetic material can perform well as a
memory storage element from the perspectives of
signal to noise and reliability. Incorporating this
technology into next-generation memory will, however,
require pervasive innovation in integrated circuit
fabrication, including implementing perpendicular
STT-MRAM, which has been proven to operate at lower
current density.[7]
First presented by Toshiba in 2007,[8] perpendicular STT
MTJs offer significant advantages over in-plane MTJs.
Particularly important are the effective thermal energy
barrier and thermal stability created by perpendicular
anisotropy and much lower switching current that
enables smaller, circular cells that are easier to fabricate
than elongated ones. Moreover, dipole field interaction
can be reduced between adjacent cells in high-density
layouts.[9]
FABRICATION CHALLENGES STT-MRAM fabrication poses challenges ranging from
material complexity of the structure to process
integration considerations. As shown in Figure 4,
many ultra-thin layers of materials with widely varying
characteristics are present in the device. Interface
engineering will be crucial to successfully combining
these materials by achieving a satisfactory balance
between surface roughness and good magnetic
properties.[10]
Figure 4
W
Ta (10nm)
NiFe (6nm)
MgO (~1nm)
Ru (~1nm)
IrMn (10nm)
CoFeB (5nm)
CoFeB (5nm)
CoFeB (1-3nm)
Ta (30nm)
SiO
AlO/SiN (50nm)
Bit Line WireElectrode/Capping LayerFree LayerTunneling LayerFixed LayerCoupling LayerSpacer LayerFerromagnetic LayerAntiferromagnetic LayerBu�er LayerContactIsolation
W, Cu (50nm)
20Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc.Applied Materials, Inc.
Emerging STT-MRAM
STT-MRAM employs electron spin associated with magnetism. An electric current from an underlying CMOS transistor is polarized by aligning the spin direction of electrons passing through the magnetic tunnel junction (MTJ) at the core of the bit cell (Figure 2). The spin transforms the state of the MTJ from anti-parallel (1) to parallel (0) and vice versa, with current flowing in opposite directions. The MTJ stack consists of a top electrode, a (ferromagnetic) free layer where information is stored, a tunneling insulator layer, fixed ferromagnetic reference layers, and a bottom electrode. Current running through the reference layer polarizes its electrons, which then affect those of the free layer, leading to the parallel and anti-parallel configurations. Writing occurs when the spin-polarized current changes the magnetic orientation of the data storage layer; the resistance difference of this layer is used for reading. Applying the spin-polarized current vertically through the MTJ overcomes a major drawback of conventional MRAM, which is the increase in switching current as the technology scales down.[6]
As the CMOS transistor has evolved from a planar structure to a 3D one, the drivability of a transistor in small geometry has exceeded 1mA/µm in a logic circuit, where µm represents the gate width of 1µm. These findings have been widely reported in the literature, especially for high-κ/metal gate CMOS. Figure 3 shows the write current as a function of STT-RAM cell area, from which one can project that if current density of 1.4MA/cm2 is scaled down to approximately 20nm, 6.4µA will be required for programming a 20nm by 20nm STT-MRAM cell. However, as memory arrays operate with random individual access and most of the inactive transistors are in the off state during the access stage, the transistor off current is also very important for array operation. For a lower off current transistor, the on current will be correspondingly reduced. Hence, reducing STT-MRAM cell programming current density further by a factor of 2-5 will increase device margin and functionality, while lowering overall cost.
Because it uses a current running through the cell, the required writing current through the smaller MTJ decreases (Figure 3), in turn reducing power consumption as the device becomes smaller. In addition, STT-MRAM uses only 1.2V internally and can therefore operate on a single 1.5V battery as opposed to DRAM and Flash that need charge pumps to satisfy their higher voltage requirements (e.g., Flash requires 10-12V for writing).
To be viable, STT-MRAM must clearly demonstrate that
it can migrate to smaller and denser memory size with
lower power consumption as the underlying CMOS
logic technology scales down. DRAM and SRAM are on
track to scale to 20nm, with well-known device function
and cost parity. For STT-MRAM to be competitive with
these well-established technologies, it must demonstrate
functional scalability to 10nm. Research by the hard
disk drive industry and others[5] has confirmed that a
10nm-sized magnetic material can perform well as a
memory storage element from the perspectives of
signal to noise and reliability. Incorporating this
technology into next-generation memory will, however,
require pervasive innovation in integrated circuit
fabrication, including implementing perpendicular
STT-MRAM, which has been proven to operate at lower
current density.[7]
First presented by Toshiba in 2007,[8] perpendicular STT
MTJs offer significant advantages over in-plane MTJs.
Particularly important are the effective thermal energy
barrier and thermal stability created by perpendicular
anisotropy and much lower switching current that
enables smaller, circular cells that are easier to fabricate
than elongated ones. Moreover, dipole field interaction
can be reduced between adjacent cells in high-density
layouts.[9]
FABRICATION CHALLENGES STT-MRAM fabrication poses challenges ranging from
material complexity of the structure to process
integration considerations. As shown in Figure 4,
many ultra-thin layers of materials with widely varying
characteristics are present in the device. Interface
engineering will be crucial to successfully combining
these materials by achieving a satisfactory balance
between surface roughness and good magnetic
properties.[10]
Deposition and etching processes will have to achieve
virtually atomic-scale process control to ensure
extreme uniformity and negligible surface roughness.
For example, tunneling barrier uniformity is crucial for
high tunnel magneto-resistance (MR) and depends
primarily on the roughness of the bottom electrode.[11]
Given the extreme thinness of the layers, etching must
employ ultra-clean processes to avoid re-deposition of
by-products or residue as this could lead to shorting.
Cell profile control must be extremely exact to achieve
consistency across large arrays.
Several characteristics of the magnetic films in the
stack pose further challenges. They are thin and
susceptible to corrosion; hence effective passivation
is of great importance to protect them from penetra-
tion or diffusion of such process chemicals as oxygen,
chlorine, and bromine, which can alter the structure
and properties of the films to reduce the MR effect. The
magnetic moments of magnetic films depend strongly
on the domains (grains) and grain boundaries of these
materials, as these factors affect programing current.
In addition, magnetic switching (or coupling) between
the fixed layer and the free layer through the tunneling
oxide separating them is greatly reduced by the bound-
aries of the grains. Signal-to-noise ratio also degrades
as grain boundary increases or the number of grains in
a given area decreases below a certain threshold. As
STT-MRAM cell size scales down, noise levels or signal
inconsistency across the array increases, with these
variations becoming relatively larger.
From the integration standpoint, STT-MRAM processes
(typically <350˚C) have the advantage over other
embedded memory technologies employing relatively
low temperatures and hence are compatible with CMOS
back-end-of-line (BEOL) thermal budgets.[12] However,
a holistic approach should be adopted, taking into
Figure 4. SST-RAM
comprises a complicated
materials system.
Figure 4
W
Ta (10nm)
NiFe (6nm)
MgO (~1nm)
Ru (~1nm)
IrMn (10nm)
CoFeB (5nm)
CoFeB (5nm)
CoFeB (1-3nm)
Ta (30nm)
SiO
AlO/SiN (50nm)
Bit Line WireElectrode/Capping LayerFree LayerTunneling LayerFixed LayerCoupling LayerSpacer LayerFerromagnetic LayerAntiferromagnetic LayerBu�er LayerContactIsolation
W, Cu (50nm)
21 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc.
Emerging STT-MRAM
account the total thermal budget allocated to post-MTJ
processing, to protect against adverse effects. For
example, thermal fluctuation of magnetization can be
caused by subsequent high-temperature processing;
exposing the wafer to physical stresses can also induce
altered magnetic properties as a result of changes in
grain boundaries and interface properties.
While beyond the scope of this article, broader
challenges involve achieving low current density and
high reliability in array operation. Besides increasing
power consumption for large arrays, high current
density exacerbates electrical stress and reduces
transistor lifetime. Another consideration will be
provision of magnetic shielding during assembly and
testing to protect pre-magnetized cells from external
magnetic fields.
APPLICABLE PROCESS TECHNOLOGIESFortunately, recent advances in unit and integration
processes, as well as ongoing development work,
address many of the challenges cited above.
Figure 5
Source: Reference 1.
20nm
Ultra-thin deposition of ultra-pure metals as well as
metal oxides, metal nitrides, binary alloys, and magnetic
materials has been made possible by RF sputtering, an
adaptation of conventional physical vapor deposition (PVD)
that enables virtually damage-free processing. RFPVD
employs lower power levels than conventional PVD,
which reduces the risk of plasma damage while enabling
exacting control of thickness, stoichiometry, and
deposition rate (on the order of 0.1-2Å/sec) for layers
less than 10Å thick. Low-temperature deposition also
offers the advantage of producing smoother surface
morphology. Rotating the wafer during deposition
can improve within-wafer uniformity to the required
0.5 percent range. Surface roughness can be further
reduced by rotating the wafer while exposing it to
a mild argon sputter.
With its ability to create highly uniform and
conformal films with atomic level control, atomic layer
deposition (ALD) has become an important thin films
deposition process. This method uses pulses of gas to
deposit material one atomic layer at a time. ALD can
be enhanced with the application of plasma energy
that promotes attraction of the required species to the
wafer surface and accelerates the reaction (deposition
cycle) while also improving film uniformity and quality.
In STT-MRAM, plasma-enhanced ALD (PE-ALD) offers
a good low-temperature approach for depositing thin
spacer and passivation layers without adverse reactions
to underlying metals. In-situ annealing of the ALD film
to achieve proper crystalline structure complements
the uniformity of the deposition process in achieving
the uniformity requirement for thin (<1nm) films in the
STT-RAM cell stack.
As features become more densely packed, the gaps
between electrical components become narrower,
aspect ratios greater, and re-entrant profiles more
common (Figure 5). This continuous challenge for
scaling dielectric gap fill from each node to the next has
driven innovation in chemical vapor deposition (CVD)
to produce a fluid-like, profile-insensitive film that can
be deposited at low temperatures, consistent with
reduced thermal budgets at advanced nodes. Beyond
achieving complete gap fill, dielectric films must satisfy
additional requirements to be integrated into a device.
They must have a high breakdown voltage to ensure
electrical robustness. They must also possess good film
Figure 5. A prototype
STT-MRAM chip exhibits
the re-entrant profile for
which flowable CVD film
offers void-free, complete
bottom-up gap fill.
density to ensure strong performance after chemical
mechanical planarization (CMP), reactive ion etch, and
wet cleans. And, lastly, they must be extremely pure
to ensure that no fixed charges are created, which are
detrimental to device reliability. The new flowable CVD
film is comparable in these respects to high-quality,
industry-standard high-density plasma CVD silicon
dioxide.
High-temperature etching (150-250˚C), developed
and proven for high-κ/metal gate applications, is also
being applied to such materials as magnesium oxide,
ruthenium, cobalt-iron-boron, palladium, and platinum-
manganese used in STT-MRAM structures. Non-halide-
based chemistries generally used in high-temperature
etching do not adversely affect magnetic films and
the tunneling dielectric as do the chlorine and fluorine
chemistries typical of lower-temperature etch regimes.
These high-temperature chemistries combined with
precise plasma energy control throughout the entire
stack etching sequence can create a smooth-walled and
residue-free STT-MRAM cell. Plasma pulsing is also
being studied as a means of refining this performance.
Low-temperature annealing processes are also required.
Minimizing the thermal budget while sustaining
minimum reaction temperatures for quality interfaces
and proper material crystalline structures, in particular,
necessitates low-temperature (<400˚C) processes
with fast and accurate control. Rapid thermal processing
technology now accommodates processes at
temperatures as low as 150˚C, with transmission
pyrometry enabling closed-loop monitoring of wafer
temperatures as low as 75˚C and multi-point
measurement capability helping to improve die-to-die
and wafer-to-wafer repeatability.
CMP is becoming a more frequent and challenging
process in advanced integrations, such as FinFETs and
STT-MRAM, where devices are directly exposed to the
CMP process. As features become smaller and more
fragile, preservation of device topography through
precision planarization end-pointing is crucial to
successful device performance. Addressing this
requirement, in-situ, high-resolution sensors now enable
closed-loop, real-time thickness control during
planarization by means of incremental changes to
polishing conditions in multiple zones of the polishing
head.
22Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc. Applied Materials, Inc.
Emerging STT-MRAM
Ultra-thin deposition of ultra-pure metals as well as
metal oxides, metal nitrides, binary alloys, and magnetic
materials has been made possible by RF sputtering, an
adaptation of conventional physical vapor deposition (PVD)
that enables virtually damage-free processing. RFPVD
employs lower power levels than conventional PVD,
which reduces the risk of plasma damage while enabling
exacting control of thickness, stoichiometry, and
deposition rate (on the order of 0.1-2Å/sec) for layers
less than 10Å thick. Low-temperature deposition also
offers the advantage of producing smoother surface
morphology. Rotating the wafer during deposition
can improve within-wafer uniformity to the required
0.5 percent range. Surface roughness can be further
reduced by rotating the wafer while exposing it to
a mild argon sputter.
With its ability to create highly uniform and
conformal films with atomic level control, atomic layer
deposition (ALD) has become an important thin films
deposition process. This method uses pulses of gas to
deposit material one atomic layer at a time. ALD can
be enhanced with the application of plasma energy
that promotes attraction of the required species to the
wafer surface and accelerates the reaction (deposition
cycle) while also improving film uniformity and quality.
In STT-MRAM, plasma-enhanced ALD (PE-ALD) offers
a good low-temperature approach for depositing thin
spacer and passivation layers without adverse reactions
to underlying metals. In-situ annealing of the ALD film
to achieve proper crystalline structure complements
the uniformity of the deposition process in achieving
the uniformity requirement for thin (<1nm) films in the
STT-RAM cell stack.
As features become more densely packed, the gaps
between electrical components become narrower,
aspect ratios greater, and re-entrant profiles more
common (Figure 5). This continuous challenge for
scaling dielectric gap fill from each node to the next has
driven innovation in chemical vapor deposition (CVD)
to produce a fluid-like, profile-insensitive film that can
be deposited at low temperatures, consistent with
reduced thermal budgets at advanced nodes. Beyond
achieving complete gap fill, dielectric films must satisfy
additional requirements to be integrated into a device.
They must have a high breakdown voltage to ensure
electrical robustness. They must also possess good film
density to ensure strong performance after chemical
mechanical planarization (CMP), reactive ion etch, and
wet cleans. And, lastly, they must be extremely pure
to ensure that no fixed charges are created, which are
detrimental to device reliability. The new flowable CVD
film is comparable in these respects to high-quality,
industry-standard high-density plasma CVD silicon
dioxide.
High-temperature etching (150-250˚C), developed
and proven for high-κ/metal gate applications, is also
being applied to such materials as magnesium oxide,
ruthenium, cobalt-iron-boron, palladium, and platinum-
manganese used in STT-MRAM structures. Non-halide-
based chemistries generally used in high-temperature
etching do not adversely affect magnetic films and
the tunneling dielectric as do the chlorine and fluorine
chemistries typical of lower-temperature etch regimes.
These high-temperature chemistries combined with
precise plasma energy control throughout the entire
stack etching sequence can create a smooth-walled and
residue-free STT-MRAM cell. Plasma pulsing is also
being studied as a means of refining this performance.
Low-temperature annealing processes are also required.
Minimizing the thermal budget while sustaining
minimum reaction temperatures for quality interfaces
and proper material crystalline structures, in particular,
necessitates low-temperature (<400˚C) processes
with fast and accurate control. Rapid thermal processing
technology now accommodates processes at
temperatures as low as 150˚C, with transmission
pyrometry enabling closed-loop monitoring of wafer
temperatures as low as 75˚C and multi-point
measurement capability helping to improve die-to-die
and wafer-to-wafer repeatability.
CMP is becoming a more frequent and challenging
process in advanced integrations, such as FinFETs and
STT-MRAM, where devices are directly exposed to the
CMP process. As features become smaller and more
fragile, preservation of device topography through
precision planarization end-pointing is crucial to
successful device performance. Addressing this
requirement, in-situ, high-resolution sensors now enable
closed-loop, real-time thickness control during
planarization by means of incremental changes to
polishing conditions in multiple zones of the polishing
head.
IMPLEMENTING FABRICATIONDepositing the SST-MRAM film stack and creating
the memory cell structure can be readily adapted to
process clustering. Using Figure 4 as a reference, it
would be possible to integrate on one platform the
complete deposition sequence for the entire stack with
a pre-treatment process for reducing surface roughness
on the incoming wafer, as well as between successive
depositions. In addition, process monitoring, such
as optical spectroscopy and wafer surface particle
inspection, can be integrated into the system to
enhance manufacturing quality.
As for cell formation, similar clustering could combine
low-temperature spacer/passivation PE-ALD with
high-temperature etching. Multiple etch technologies,
as described above, can be integrated onto the same
platform for etching complicated stacks with accurate
control and high productivity. Here also, integration of
monitoring technologies optimizes process performance.
Besides end-pointing of etch processes, in-situ
monitoring of critical dimensions and devices after
etching and passivation layer deposition can be
installed directly on the chambers.
CONCLUSIONDRAM and Flash are facing serious limitations beyond
the 20nm technology node, prompting new approaches
to memory design, such as STT-MRAM. While the
material complexity and 3D architecture of this new
structure pose challenges, many recent advances in
deposition, etch, and related integration processes offer
device manufacturers the means by which to bring this
technology to production using proven cluster-tool
platforms.
Applied Materials, Inc.23 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc.
THROUGH-SILICON VIA TECHNOLOGYEnroute to Manufacturing
Emerging STT-MRAM
REFERENCES[1] A. Driskill-Smith, “Latest Advances and Future
Prospects of STT-RAM,” Non-Volatile Memories
Workshop, University of California, San Diego,
April 11–13, 2010.
[2] F. Tabrizi, “The Future of Scalable STT-RAM as a
Universal Embedded Memory,” retrieved October 7,
2011,
http://www.eetimes.com/design/embedded/
4026000/The-future-of-scalable-STT-RAM-as-a-
universal-embedded-memory.
[3] X. Dong, et al., “Circuit and Microarchitecture
Evaluation of 3D Stacking Magnetic RAM (MRAM)
as a Universal Memory Replacement,” Proceedings
of the 45th Annual Design Automation Conference,
Anaheim, California, June 2008.
[4] X. Dong, et al., “Leveraging 3D PCRAM Technologies
to Reduce Checkpoint Overhead for Future Exascale
Systems,” Proceedings of the Conference on High
Performance and Analysis, Portland, Oregon,
November 2009.
[5] C.J. Lin, et al., “45nm Low-Power CMOS
Logic-Compatible Embedded STT-MRAM Utilizing
a Reverse-Connection 1T/1MTJ Cell,” International
Electron Devices Meeting, IEEE International,
pp. 279-282, Dec. 2009.
[6] S.A. Wolf, et al., “The Promise of Nanomagnetics
and Spintronics for Future Logic and Universal
Memory,” Proceedings of the IEEE, Vol. 98, No. 12,
pp. 2155-2168, 2010.
[7] D.C. Worledge, et al., “Switching Distributions
and Write Reliability of Perpendicular Spin Torque
MRAM,” International Electron Devices Meeting,
IEEE International, pp. 296-299, Dec. 2010.
[8] M. Nakayama, et al., “Spin Transfer Switching in
TbCoFe/CoFeB/MgO/ CoFeB/TbCoFe Magnetic
Tunnel Junctions with Perpendicular Magnetic
Anisotropy,” Proceedings of the 52nd Annual
Conference on Magnetism and Magnetic Materials,
Journal of Applied Physics, Vol. 103, Issue 7,
pp. A710-1-A710-3, 2008.
[9] Y. Huai, “Spin-Transfer Torque MRAM (STT-MRAM):
Challenges and Prospects,” AAPPS Bulletin, Vol. 18,
No. 6, pp. 33-40, Dec. 2008.
[10] C.S. Kim, et al., “Thickness and Temperature Effects
on Magnetic Properties and Roughness of L10-ordered
FePt Films,” IEEE Transactions on Magnetics, Vol. 46,
No. 6, pp. 2282-2285, 2010.
[11] M. Yoshikawa, et al., “Tunnel Magnetoresistance
Over 100% in MgO-Based Magnetic Tunnel Junction
Films with Perpendicular Magnetic L10-FePt
Electrodes,” IEEE Transactions on Magnetics, Vol. 44,
No. 11, pp. 2573–2576, 2008.
[12] K. Lee and S.H. Kang, “Development of Embedded
STT-MRAM for Mobile System-on-Chips,”
IEEE Transactions on Magnetics, Vol. 47, No. 1,
pp. 131-136, January 2011.
[13] F. Tang, et al., “Atomic Layer Deposition of MgO
for High-κ Capping Layers,” 11th International
Conference on Atomic Layer Deposition, Cambridge,
MA, June 26-29, 2011.
AUTHORSEr-Xuan Ping is a managing director in the Silicon
Systems Group at Applied Materials. He holds his Ph.D.
in electrical engineering from Iowa State University.
Gill Lee is a principal member of technical staff in the
Silicon Systems Group at Applied Materials. He earned
his M.S. in materials science from Pohang University of
Science and Technology, Korea.
ARTICLE [email protected]
In recent years, semiconductor devices have been under
intensifying pressure to deliver more functionality at lower
power and greater speed in smaller dimensions as consumer
electronics have become increasingly complex and more
compact. Through-silicon via (TSV) technology has been
under development to satisfy these demands by offering
designers more freedom, and improved power and form
factor efficiencies through three-dimensional (3D)
interconnect (IC) stacking. Characterized and optimized
TSV unit processes and integration schemes are now
demonstrating their readiness for manufacturing.
The basic principle behind 3D ICs using TSVs is that the
vias replace off-chip, two-dimensional peripheral buses
that are millimeters in length with micron-scale vertical
buses. The full potential of this advance is realized when
chip designers implement new design architectures that
use 3D IC with TSVs for routing power, ground, and signal
24Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc.Applied Materials, Inc.
KEYWORDS
Through-Silicon Via
3D Interconnect
Via-Middle
Via-Reveal
THROUGH-SILICON VIA TECHNOLOGYEnroute to Manufacturing
[9] Y. Huai, “Spin-Transfer Torque MRAM (STT-MRAM):
Challenges and Prospects,” AAPPS Bulletin, Vol. 18,
No. 6, pp. 33-40, Dec. 2008.
[10] C.S. Kim, et al., “Thickness and Temperature Effects
on Magnetic Properties and Roughness of L10-ordered
FePt Films,” IEEE Transactions on Magnetics, Vol. 46,
No. 6, pp. 2282-2285, 2010.
[11] M. Yoshikawa, et al., “Tunnel Magnetoresistance
Over 100% in MgO-Based Magnetic Tunnel Junction
Films with Perpendicular Magnetic L10-FePt
Electrodes,” IEEE Transactions on Magnetics, Vol. 44,
No. 11, pp. 2573–2576, 2008.
[12] K. Lee and S.H. Kang, “Development of Embedded
STT-MRAM for Mobile System-on-Chips,”
IEEE Transactions on Magnetics, Vol. 47, No. 1,
pp. 131-136, January 2011.
[13] F. Tang, et al., “Atomic Layer Deposition of MgO
for High-κ Capping Layers,” 11th International
Conference on Atomic Layer Deposition, Cambridge,
MA, June 26-29, 2011.
AUTHORSEr-Xuan Ping is a managing director in the Silicon
Systems Group at Applied Materials. He holds his Ph.D.
in electrical engineering from Iowa State University.
Gill Lee is a principal member of technical staff in the
Silicon Systems Group at Applied Materials. He earned
his M.S. in materials science from Pohang University of
Science and Technology, Korea.
ARTICLE [email protected]
In recent years, semiconductor devices have been under
intensifying pressure to deliver more functionality at lower
power and greater speed in smaller dimensions as consumer
electronics have become increasingly complex and more
compact. Through-silicon via (TSV) technology has been
under development to satisfy these demands by offering
designers more freedom, and improved power and form
factor efficiencies through three-dimensional (3D)
interconnect (IC) stacking. Characterized and optimized
TSV unit processes and integration schemes are now
demonstrating their readiness for manufacturing.
The basic principle behind 3D ICs using TSVs is that the
vias replace off-chip, two-dimensional peripheral buses
that are millimeters in length with micron-scale vertical
buses. The full potential of this advance is realized when
chip designers implement new design architectures that
use 3D IC with TSVs for routing power, ground, and signal
lines. Micron-scale TSVs enable high-density inter-die
connectivity, leading to high-bandwidth operation. The
first few TSV applications are in dynamic random access
memory (DRAM) memory stacks, logic-memory stacks,
and field-programmable gate arrays (FPGAs)—shipment
of the world’s first interposer-based highest capacity
FPGA was announced in September 2011.[1] In memory
devices, for example, flash memories show steady density
increases aligned with Moore’s Law,[2] enabled by double
patterning of lithographic features. DRAM devices are
more challenging to scale than flash memories, and
greater density is obtained not only by lithography
scaling, but by 3D stacking of memory die. This 3D
approach satisfies both performance and form factor
needs for future end products.[3,4]
In microprocessors, the drive to continuously increase
frequency has been tempered by practical issues arising
from the need to manage leakage, stand-by current, and
power dissipation at the chip and system levels. The
enhanced performance of computers with multi-core
processors is often hobbled by memory latency and
bandwidth.[5] 3D integration can dramatically improve
power loss and inductance by creating a denser, lower
latency, higher bandwidth bus between memory and
processor.
In scaling device node from 45nm to 28nm to 20nm
to 14nm, not all functional blocks need to be scaled.
Instead of scaling the entire chip, the portion that needs
to be scaled can be manufactured as a separate chip,
leaving other functional blocks relatively untouched.
These dis-integrated functional blocks can then span
across multiple smaller die interconnected with TSVs.
TSV SCHEMESCurrently, via-middle and via-last TSV schemes are
being widely adopted at logic/foundry and memory
makers. The choice between the two is driven largely
by device design considerations. In general, devices
Applied Materials, Inc.25 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc.
Manufacture-Ready TSV
necessitating high TSV interconnection require smaller
TSV dimension. Such applications are better served
by the via-middle flow in which the TSVs are created
right after contact formation. The via-middle scheme
described in this article for 3D IC stacking is also used
for TSVs in 2.5D interposer applications.
In the via-last process scheme, front-end-of-line device
processing can proceed as usual. TSVs are created in the
back-end wafer line at a wafer fab or at an outsourced
assembly and test facility.
Figure 1 shows the typical process steps involved in
the via-middle, via-reveal, and via-last TSV flows. This
article presents an overview of the via-middle and
companion via-reveal processes. Via-last uses modified
processes on wafers temporarily bonded to carriers.
Hence, the process temperature must not exceed 200˚C
to preserve adhesion of temporary bonding materials.
VIA-MIDDLE TSVIn the via-middle flow, TSVs are created from the
device side of a full-thickness wafer during processing
in a wafer fab immediately following transistor and
contact formation and before the formation of back-
end-of-line (BEOL) damascene interconnects. Typically,
the vias are 5-10µm in diameter and 50-100µm deep,
with a nominal aspect ratio of 8-10:1. The International
Technology Roadmap for Semiconductors calls for vias
with a 2-3µm diameter, 20-50µm depth in a few years.
Maintaining an aspect ratio less than 12:1 allows a wider
and more robust process window. The wafer temperature
is in the same range as that of BEOL films, typically
350-400˚C. Via-middle TSVs offer the most flexibility
in layout, design, and via density. Provided post-TSV
processing planarity is good, interconnect wires from
M1 through Mx may be permitted to go above them.
Table 1 details the processes in the via-middle flow.
Table 1. Process steps
comprising the via-middle
TSV scheme.
Figure 1. TSV process flows
for via-middle, via-reveal,
and via-last schemes.
Table 1
Process Step Purpose Key Requirements
Resist Coat and Lithography Exposure Create pattern. Resist thickness, exposure quality.
TSV EtchDielectric and silicon etch to create vias.
Etch rate, profile/depth, selectivity (resist to dielectric and silicon), undercut, non-uniformity across wafer. All-in-one etch.
Resist Strip and Wet Clean Clean vias. Post-etch residue removal.
Dielectric Oxide Liner DepositionElectrical isolation.Cu to bulk Si capacitance.
Step coverage, mechanical properties, leakage, breakdown voltage, and dielectric constant.Process Temperature ~400˚C.2500Å to 1.5µm based on application.
Barrier/Seed DepositionCopper diffusion barrier/seed for electroplating.
Barrier properties and step coverage.
Electrochemical Deposition (ECD) Conducting plug. Void-free fill, copper quality, and stability.
Anneal Stabilize film, control protrusions. Copper material properties.
Chemical Mechanical Planarization (CMP) Form copper plug. Flatness, topography.
Figure 1
Via-Middle Via-Last
CarrierCarrier
Part 1. Form Vias from Front Sidein MOL or BEOL Part 2. Backside Via Reveal
Form Vias from Back SideAfter Thinning
· TSV Via Etch, Strip and Clean· CVD Dielectric Liner· Barrier/Seed· ECD Cu Fill, Anneal· CMP Cu/Barrier/Dielectric
· Edge Trim· Temporary Bonding· Grinding· CMP Si· Dry Si Recess Etch (expose Cu pillar)· Low Temp Nitride/Oxide· CMP Oxide/Nitride
· Edge Trim· Temporary Bonding· Grinding· CMP Si· Low Temp Nitride/Oxide· Via Etch, Strip, Clean· Low Temp Oxide Liner· Oxide Bottom Open and Clean· Barrier/Seed· ECD Cu· CMP Cu/Barrier/Dielectric
Figures 2 and 3 illustrate performance of current
technologies for several of the steps in the process
sequence.
Early in TSV process development, post-ECD copper
overburden could be 0.5-0.75 of the TSV diameter,
i.e., several microns thick. Such added stress tended
to cause excessive wafer bowing, which could induce
breakage or create difficulties in subsequent processing,
especially for CMP. Thick copper overburden also
increases the cost of copper CMP. More recent ECD
exhibits enhanced bottom-up fill, a wide process window,
and overburden of less than 2µm on a 5µm via. This
process reduces the required thickness of the seed layer
and lowers CMP costs. Careful selection of the CMP
process and slurry is important to ensure clean copper
and barrier removal, freedom from corrosion of the
copper in the via or the barrier metal on the sidewall,
and absence of divots or attack in the oxide lining the
inner circumference of the via.
Typically between ECD and CMP steps, the copper is
annealed at approximately 400˚C in a forming gas (3%
Figure 3
(a) (b) (c)Applied Materials internal data
Barrier/Seed 25% Fill 50% Fill 75% Fill 100% Fill
26Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc.Applied Materials, Inc.
VIA-MIDDLE TSVIn the via-middle flow, TSVs are created from the
device side of a full-thickness wafer during processing
in a wafer fab immediately following transistor and
contact formation and before the formation of back-
end-of-line (BEOL) damascene interconnects. Typically,
the vias are 5-10µm in diameter and 50-100µm deep,
with a nominal aspect ratio of 8-10:1. The International
Technology Roadmap for Semiconductors calls for vias
with a 2-3µm diameter, 20-50µm depth in a few years.
Maintaining an aspect ratio less than 12:1 allows a wider
and more robust process window. The wafer temperature
is in the same range as that of BEOL films, typically
350-400˚C. Via-middle TSVs offer the most flexibility
in layout, design, and via density. Provided post-TSV
processing planarity is good, interconnect wires from
M1 through Mx may be permitted to go above them.
Table 1 details the processes in the via-middle flow.
Manufacture-Ready TSV
Table 1
Process Step Purpose Key Requirements
Resist Coat and Lithography Exposure Create pattern. Resist thickness, exposure quality.
TSV EtchDielectric and silicon etch to create vias.
Etch rate, profile/depth, selectivity (resist to dielectric and silicon), undercut, non-uniformity across wafer. All-in-one etch.
Resist Strip and Wet Clean Clean vias. Post-etch residue removal.
Dielectric Oxide Liner DepositionElectrical isolation.Cu to bulk Si capacitance.
Step coverage, mechanical properties, leakage, breakdown voltage, and dielectric constant.Process Temperature ~400˚C.2500Å to 1.5µm based on application.
Barrier/Seed DepositionCopper diffusion barrier/seed for electroplating.
Barrier properties and step coverage.
Electrochemical Deposition (ECD) Conducting plug. Void-free fill, copper quality, and stability.
Anneal Stabilize film, control protrusions. Copper material properties.
Chemical Mechanical Planarization (CMP) Form copper plug. Flatness, topography.
Figure 1
Via-Middle Via-Last
CarrierCarrier
Part 1. Form Vias from Front Sidein MOL or BEOL Part 2. Backside Via Reveal
Form Vias from Back SideAfter Thinning
· TSV Via Etch, Strip and Clean· CVD Dielectric Liner· Barrier/Seed· ECD Cu Fill, Anneal· CMP Cu/Barrier/Dielectric
· Edge Trim· Temporary Bonding· Grinding· CMP Si· Dry Si Recess Etch (expose Cu pillar)· Low Temp Nitride/Oxide· CMP Oxide/Nitride
· Edge Trim· Temporary Bonding· Grinding· CMP Si· Low Temp Nitride/Oxide· Via Etch, Strip, Clean· Low Temp Oxide Liner· Oxide Bottom Open and Clean· Barrier/Seed· ECD Cu· CMP Cu/Barrier/Dielectric
Figures 2 and 3 illustrate performance of current
technologies for several of the steps in the process
sequence.
Early in TSV process development, post-ECD copper
overburden could be 0.5-0.75 of the TSV diameter,
i.e., several microns thick. Such added stress tended
to cause excessive wafer bowing, which could induce
breakage or create difficulties in subsequent processing,
especially for CMP. Thick copper overburden also
increases the cost of copper CMP. More recent ECD
exhibits enhanced bottom-up fill, a wide process window,
and overburden of less than 2µm on a 5µm via. This
process reduces the required thickness of the seed layer
and lowers CMP costs. Careful selection of the CMP
process and slurry is important to ensure clean copper
and barrier removal, freedom from corrosion of the
copper in the via or the barrier metal on the sidewall,
and absence of divots or attack in the oxide lining the
inner circumference of the via.
Typically between ECD and CMP steps, the copper is
annealed at approximately 400˚C in a forming gas (3%
hydrogen) environment for 20-30 minutes to stabilize
its microstructure and film composition. All subsequent
processes, such as BEOL damascene processing and
final anneal, must be at or below this temperature to
minimize protrusion and avoid the risk of dielectric
cracking and inter-metal shorts.
VIA-REVEAL TSVVias created in the middle of line must be exposed from the backside in a process known as ‘via-reveal’ or ‘backside contact.’ The process takes place on a device wafer that has been bonded face down to a carrier and then thinned by a grinding process. The adhesive coating, carrier-wafer-to-device-wafer bonding, and wafer grinding introduces cross-wafer silicon thickness non-uniformity (Figure 4). Provided the post-grind thickness non-uniformity is radially symmetric, silicon CMP can improve the thickness profile. CMP polish heads with multi-zone-tuning capability can effectively reduce both total thickness variation across the wafer and surface roughness. Pre- and post-CMP silicon clean can be used to remove contamination, residue, and edge defects on the bonded wafer pair.
Figure 3
(a) (b) (c)Applied Materials internal data
Barrier/Seed 25% Fill 50% Fill 75% Fill 100% Fill
Figure 2
Applied Materials internal data
1.8µm 450nm
1.4µm
1.07µm
1.02µm 319nm
430nm
330nm
10µmx60µm
1µm 0.3µm0.2µm Sidewall
0.38µm
0.35µm
0.28µm
0.23µm
4µmx44µm
Step-Coverage onHigh Aspect Ratio TSV (11:1)
Sidewall Thickness Scaling forMedium Aspect Ratio TSV (6:1)
Figure 3. Progressive
copper ECD in 10:1 aspect
ratio TSV showing
(a) enhanced bottom-up
fill with low copper over-
burden in the field region,
(b) close-up of complete fill,
and (c) post-CMP appearance.
Figure 2. Sidewall oxide
conformality and scaling
in via-middle TSVs.
27 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc.
Figure 6
Applied Materials internal data
FOV = 5µm
FOV = 5µm
FOV = 100µm
FOV = 100µm
Post
-Etc
hPo
st-C
MP
Figure 5 details the via-reveal process sequence. The
backside grind and silicon CMP stops short of the via,
which remains encased within the thinned silicon wafer.
Silicon recess etch exposes the via, without damaging
the via-middle oxide liner that encases it (penetration
of the oxide would damage the titanium or tantalum
barrier, or the copper fill). Low-temperature nitride and
oxide dielectric layers are then deposited for isolation
and passivation. The nitride serves as a copper diffusion
barrier and etch stop for oxide CMP. Dielectric CMP
planarizes the resultant pillar structure and exposes
the copper vias. The pillars are isolated from each other
and mechanically supported by deposited dielectrics
between them, which serve as isolation for the
subsequent micro-bump process. Examples of via-
reveal on 5x50µm TSVs shown in Figure 6 demonstrate
the production-worthiness of this scheme.
Manufacture-Ready TSV
Figure 6. SEM images of
via-reveal results show
production-worthiness of
the process.
Figure 5. Via-reveal processes
with silicon recess etch.
Figure 4
Distance from Wafer Center (mm)
CMP Profile Control Improves WIW Silicon NU%
-150 -100 -50 0 50 100 150
12
10
8
6
4
2
0
Post-CMP Profile-1 (Not Optimized)Post-CMP Profile-2 (Optimized)Post-CMP Profile-3 (Optimized)
Dev
ice
Si T
hick
ness
(µm
)
Si R
emov
ed (
µm)
Distance from Wafer Center (mm)
CMP Profile Control Improves WTW Silicon NU%
-150 -100 -50 0 50 100 150
80
75
70
65
60
55
50
Pre-CMP Profile (After Grind)
Post-CMP Profile (Fine Polish)
Figure 5
Exposure(Pillar Height)
Recess Etch
OxideNitride
CVD Nitride/OxidePassivation
Si Overburden
Bump/Pillar
Adhesive
FEOL/BEOL
Oxide/Liner
CuTSV
CMP Si (Post-Grind)
Carrier (Glass or Silicon)
Silicon
CMP Oxide
Figure 4. Silicon CMP profile
control improves within-
wafer (WIW) and wafer-to-
wafer (WTW) uniformity.
CONCLUSIONVia-middle and via-last integration schemes have
proven practical in creating high-density TSVs. Process
windows have been characterized for etch, CVD, PVD,
ECD, and CMP to demonstrate successful via-middle
and backside via-reveal processes. Unit process
co-optimization and collaboration across the industry
eco-system with wafer support systems (bonding/
thinning) is transitioning this technology from
development to production as an enabler of smaller,
faster, more functionally sophisticated, and more
energy-efficient consumer and industrial electronics.[6]
ACKNOWLEDGEMENTSThe authors wish to acknowledge the contributions of
the technical staff from the etch, CVD, PVD, ECD, and
CMP business units, as well as the integration, process,
and analytical expertise of the staff of the Maydan
Technology Center in Sunnyvale, California.
REFERENCES[1] Kirk Saban, “Xilinx Stacked Silicon Interconnect
Technology Delivers Breakthrough FPGA Capacity,
Bandwidth, and Power Efficiency,” WP380 (v1.1),
Xilinx, October 21, 2011.
[2] G.E. Moore, “Cramming More Components into
Integrated Circuits,” Electronics, 38, No. 8, pp. 114-
117, 1965.
[3] M. Koyanagi, “Roadblocks in Achieving Three-
Dimensional LSI,” Proc. 8th Symposium on Future
Electron Devices, pp. 50-60, 1989.
[4] P. Ramm, et al., “Interchip-Via Technology for Vertical
System Integration,” Proc. IEEE Int. Interconnect
Technology Conference, pp. 160-162, 2001.
[5] K. Bernstein, et al., “Interconnects in the Third
Dimension: Design Challenges for 3D ICs,” Proc.
Design Automation Conference, 2007.
[6] Banqui Wu, et al., 3D IC Stacking Technology,
McGraw-Hill Companies, Inc., New York, 2011.
28Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc. Applied Materials, Inc.
Figure 5 details the via-reveal process sequence. The
backside grind and silicon CMP stops short of the via,
which remains encased within the thinned silicon wafer.
Silicon recess etch exposes the via, without damaging
the via-middle oxide liner that encases it (penetration
of the oxide would damage the titanium or tantalum
barrier, or the copper fill). Low-temperature nitride and
oxide dielectric layers are then deposited for isolation
and passivation. The nitride serves as a copper diffusion
barrier and etch stop for oxide CMP. Dielectric CMP
planarizes the resultant pillar structure and exposes
the copper vias. The pillars are isolated from each other
and mechanically supported by deposited dielectrics
between them, which serve as isolation for the
subsequent micro-bump process. Examples of via-
reveal on 5x50µm TSVs shown in Figure 6 demonstrate
the production-worthiness of this scheme.
Manufacture-Ready TSV
Figure 4
Distance from Wafer Center (mm)
CMP Profile Control Improves WIW Silicon NU%
-150 -100 -50 0 50 100 150
12
10
8
6
4
2
0
Post-CMP Profile-1 (Not Optimized)Post-CMP Profile-2 (Optimized)Post-CMP Profile-3 (Optimized)
Dev
ice
Si T
hick
ness
(µm
)
Si R
emov
ed (
µm)
Distance from Wafer Center (mm)
CMP Profile Control Improves WTW Silicon NU%
-150 -100 -50 0 50 100 150
80
75
70
65
60
55
50
Pre-CMP Profile (After Grind)
Post-CMP Profile (Fine Polish)
Figure 5
Exposure(Pillar Height)
Recess Etch
OxideNitride
CVD Nitride/OxidePassivation
Si Overburden
Bump/Pillar
Adhesive
FEOL/BEOL
Oxide/Liner
CuTSV
CMP Si (Post-Grind)
Carrier (Glass or Silicon)
Silicon
CMP Oxide
CONCLUSIONVia-middle and via-last integration schemes have
proven practical in creating high-density TSVs. Process
windows have been characterized for etch, CVD, PVD,
ECD, and CMP to demonstrate successful via-middle
and backside via-reveal processes. Unit process
co-optimization and collaboration across the industry
eco-system with wafer support systems (bonding/
thinning) is transitioning this technology from
development to production as an enabler of smaller,
faster, more functionally sophisticated, and more
energy-efficient consumer and industrial electronics.[6]
ACKNOWLEDGEMENTSThe authors wish to acknowledge the contributions of
the technical staff from the etch, CVD, PVD, ECD, and
CMP business units, as well as the integration, process,
and analytical expertise of the staff of the Maydan
Technology Center in Sunnyvale, California.
REFERENCES[1] Kirk Saban, “Xilinx Stacked Silicon Interconnect
Technology Delivers Breakthrough FPGA Capacity,
Bandwidth, and Power Efficiency,” WP380 (v1.1),
Xilinx, October 21, 2011.
[2] G.E. Moore, “Cramming More Components into
Integrated Circuits,” Electronics, 38, No. 8, pp. 114-
117, 1965.
[3] M. Koyanagi, “Roadblocks in Achieving Three-
Dimensional LSI,” Proc. 8th Symposium on Future
Electron Devices, pp. 50-60, 1989.
[4] P. Ramm, et al., “Interchip-Via Technology for Vertical
System Integration,” Proc. IEEE Int. Interconnect
Technology Conference, pp. 160-162, 2001.
[5] K. Bernstein, et al., “Interconnects in the Third
Dimension: Design Challenges for 3D ICs,” Proc.
Design Automation Conference, 2007.
[6] Banqui Wu, et al., 3D IC Stacking Technology,
McGraw-Hill Companies, Inc., New York, 2011.
AUTHORSNiranjan Kumar is a product marketing manager in
the Silicon Systems Group at Applied Materials. He
holds his bachelors of technology degree from IIT
Kanpur, India, and certificate degree coursework from
Stanford University, both in electrical engineering.
Sesh Ramaswami is senior director, strategy, in
the Silicon Systems Group at Applied Materials. He
earned his M.S. in chemical engineering from Syracuse
University and MBA from San Jose State University.
Rao Yalamanchili is the head of the TSV Etch Products
group at Applied Materials. He received his Ph.D. in
metallurgical engineering from the University of Utah.
Manuel Hernandez is a process engineering manager in
the Gap Fill division at Applied Materials. He holds his
M.S. in materials science and engineering from Stanford
University.
Nagarajan Rajagopalan is a senior member of technical
staff in the Dielectric Systems and Modules business
unit at Applied Materials. He earned his Ph.D. in
metallurgy from the Indian Institute of Science,
Bangalore, India.
Anthony C-T Chan is a TSV technology manager for
the Metal Deposition division at Applied Materials. He
received his Ph.D. in surface physics from Rensselaer
Polytechnic Institute.
Bob Linke is a process integration manager in the
Semitool business unit at Applied Materials. He holds
his B.S. in chemical engineering from the University of
Missouri – Rolla.
Zhihong Wang is a senior manager in the CMP division
at Applied Materials. He earned his Ph.D. in chemical
engineering from the Massachusetts Institute of
Technology.
John Dukovic is a distinguished member of technical
staff in the CTO office of the Silicon Systems Group at
Applied Materials. He received his Ph.D. in chemical
engineering from the University of California at Berkeley.
ARTICLE [email protected]
29 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc.
KEYWORDS
In-Line
Defectivity
Process Control
SEM
Wafer Inspection Review
ADR
ENHANCED DEFECT OF INTEREST MONITORING With Sensitive Inspection and “Intelligent” SEM Review
As semiconductor design rules shrink, optical inspection
tools are challenged to separate between true and false
defects owing to the lower signal from real defects while
noise levels remain almost constant. The resulting high rate
of false defects jeopardizes the creation of a true defect
pareto. Traditionally, inspection tool recipes were optimized
to provide defect maps with a low (~10%) false rate, but
as defects of interest (DOI) shrink this detection sensitivity
must be compromised. A new approach optimizes the
recipe for sensitivity, introducing new challenges for SEM
review tools. A complementary advance in review technology
enhances process monitoring, reveals new defect types in
the pareto, and improves the ability to identify excursions
for low magnitude DOI.
As semiconductor fabrication technology advances
below 45nm, two dominant trends make in-line wafer
inspection more challenging: an increase in the number
of nuisances (“false defects”) and a decrease in size
and signal of DOI. As a result, we see a reduction in
the number of true defect types represented in the
post-SEM review pareto, which reduces the ability to
monitor the process efficiently and influences the
statistical process control (SPC) quality. The International
Technology Roadmap for Semiconductors (ITRS)[1] has
highlighted the increasing need for detecting small,
yield-limiting defects at high capture rate and the ability
to separate these defects from nuisance at low cost
of ownership, specifically the need to find small but
yield-relevant defects under a vast amount of nuisance
defects.
Now a more comprehensive and robust wafer-level
in-line yield monitoring system enables better data
quality for further analysis. The system comprises
inspection optimized for DOI detection and automatic
SEM review (automatic defect redetection – ADR)
optimized for nuisance filtering to enable true-only
classification. This new approach employs the current
inspection fab toolset and the same amount of labor,
but results in a much richer DOI pareto and makes it
possible to identify excursions of DOI types that could
not previously be monitored.
DOI REPRESENTATION IN PARETOInspection tools are required to provide a wafer map
depicting the locations of suspected defects with the
goal of maximizing sensitivity to DOI while maintaining
low nuisance rate. This is crucial to minimize
classification effort (typically performed manually
based on SEM images). In the past, this requirement
was easily met, inspection recipes were optimized for
maximal sensitivity, and nuisance rate was maintained
at less than 10% of the suspected defects.
Figure 1
Opt
ical
Att
ribu
tes
Sepa
rati
on
Design Rule
90 65 45 32 22
False Alarm Rate
Typical NuisanceCritical DOI
However, as design rules shrink and DOI become
smaller, the capability of optical inspection tools to
separate the nuisance from true defects is limited
(Figure 1) and the fab must choose between high
sensitivity with high nuisance rates or compromised
sensitivity (Figure 2). Optimizing inspection sensitivity
will enable detection and monitoring of new DOI types;
however, the high nuisance rate will increase the volume
of defect review (Figure 3).
As part of process monitoring, inspection results are
sampled for defect review and classification by SEM
images. The objective of this review is to identify each
type of defect and to remove the nuisance. The high
inspection nuisance rate results in lower DOI count
in the classification pareto (Figure 4), which reduces
monitoring reliability. Sampling more defects improves
the number of true defects, but incurs additional manual
classification work, which will grow significantly as the
nuisance rate rises.
Figure 4
Rev
iew
ed D
efec
ts
Rev
iew
ed D
efec
ts
Design Rule
Traditional Method
OperatorClassified
Defects
NuisancePopulation
90 65 45 32 22
Nuisance
TrueDefects
Nuisance
TrueDefects
Nuisance
TrueDefects
Nuisance
True
TrueDefects
(a)
Design Rule
Alternative Option
OperatorClassified Defects
(b)
90 65 45 32 22
Nuisance
TrueDefects
Nuisance
TrueDefects
Nuisance
TrueDefects
Nuisance
TrueTrue
Defects
30Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc. Applied Materials, Inc.
ENHANCED DEFECT OF INTEREST MONITORING With Sensitive Inspection and “Intelligent” SEM Review
As semiconductor fabrication technology advances
below 45nm, two dominant trends make in-line wafer
inspection more challenging: an increase in the number
of nuisances (“false defects”) and a decrease in size
and signal of DOI. As a result, we see a reduction in
the number of true defect types represented in the
post-SEM review pareto, which reduces the ability to
monitor the process efficiently and influences the
statistical process control (SPC) quality. The International
Technology Roadmap for Semiconductors (ITRS)[1] has
highlighted the increasing need for detecting small,
yield-limiting defects at high capture rate and the ability
to separate these defects from nuisance at low cost
of ownership, specifically the need to find small but
yield-relevant defects under a vast amount of nuisance
defects.
Now a more comprehensive and robust wafer-level
in-line yield monitoring system enables better data
quality for further analysis. The system comprises
inspection optimized for DOI detection and automatic
SEM review (automatic defect redetection – ADR)
optimized for nuisance filtering to enable true-only
classification. This new approach employs the current
inspection fab toolset and the same amount of labor,
but results in a much richer DOI pareto and makes it
possible to identify excursions of DOI types that could
not previously be monitored.
DOI REPRESENTATION IN PARETOInspection tools are required to provide a wafer map
depicting the locations of suspected defects with the
goal of maximizing sensitivity to DOI while maintaining
low nuisance rate. This is crucial to minimize
classification effort (typically performed manually
based on SEM images). In the past, this requirement
was easily met, inspection recipes were optimized for
maximal sensitivity, and nuisance rate was maintained
at less than 10% of the suspected defects.
Automatic Defect Redetection
Figure 1
Opt
ical
Att
ribu
tes
Sepa
rati
on
Design Rule
90 65 45 32 22
False Alarm Rate
Typical NuisanceCritical DOI
However, as design rules shrink and DOI become
smaller, the capability of optical inspection tools to
separate the nuisance from true defects is limited
(Figure 1) and the fab must choose between high
sensitivity with high nuisance rates or compromised
sensitivity (Figure 2). Optimizing inspection sensitivity
will enable detection and monitoring of new DOI types;
however, the high nuisance rate will increase the volume
of defect review (Figure 3).
As part of process monitoring, inspection results are
sampled for defect review and classification by SEM
images. The objective of this review is to identify each
type of defect and to remove the nuisance. The high
inspection nuisance rate results in lower DOI count
in the classification pareto (Figure 4), which reduces
monitoring reliability. Sampling more defects improves
the number of true defects, but incurs additional manual
classification work, which will grow significantly as the
nuisance rate rises.
Figure 2
NuisanceDOI
Inspection ThresholdTo Maintain 10% Nuisance
Inspection ThresholdTo Maintain 10% Nuisance
Technology
Figure 3
Optimized for DOI DetectionOptimized for Low Nuisance Rate
ShallowExtra
Pattern
ExtraPattern
Pitting Scratch Hole Defocus SEM NV
Sensitivity − Nuisance Trade-O�
Figure 1. DOI and nuisance
signal trends and their effect
on inspection nuisance.
Figure 2. As technology
progresses, inspection must
choose between sensitivity
and nuisance rate.
Figure 4
Rev
iew
ed D
efec
ts
Rev
iew
ed D
efec
ts
Design Rule
Traditional Method
OperatorClassified
Defects
NuisancePopulation
90 65 45 32 22
Nuisance
TrueDefects
Nuisance
TrueDefects
Nuisance
TrueDefects
Nuisance
True
TrueDefects
(a)
Design Rule
Alternative Option
OperatorClassified Defects
(b)
90 65 45 32 22
Nuisance
TrueDefects
Nuisance
TrueDefects
Nuisance
TrueDefects
Nuisance
TrueTrue
Defects
Figure 3. Inspection results
show a trade-off between
maximal sensitivity and
low nuisance rate. When
the recipe is optimized for
maximal sensitivity, several
defect types are detected
that are missed when the
recipe is optimized for low
nuisance rate.
Figure 4. (a) High nuisance
rate reduces the number
of true defects in the
classification pareto.
(b) Maintaining a constant
number of true defects
requires additional review
and classification manual
work.
31 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc. Applied Materials, Inc.
Automatic Defect Redetection
Figure 6
True
Def
ects
Wafers
ADR Set to Stop at 60 True
W1 W3 W5 W7 W9 W11 W13 W15 W17 W19
60
50
40
30
20
10
0
NuisanceDOI
Table 1
MethodDefect Reviewed by SEM
Defect Manually Classified
DOI Types
Traditional 60 (fixed per wafer) 60 3
New 180 (average) 60 6
Figure 6 demonstrates the enhanced results and labor-saving effectiveness of the SEM ADR when the SEM was set to review defects until it reached a constant, predefined number (60) of true defects in each run (versus the traditional fixed number of total reviewed defects).
ResultsAnalysis was performed on <45nm node features using 19 wafers from different lots. Each wafer was inspected and reviewed twice, first using the “traditional” approach (inspection recipe optimized for low nuisance, review of 60 locations) and then using the new approach (inspection recipe optimized for maximum sensitivity, automatic review until 60 true defects were detected by SEM). DOI were manually classified (60 images for each method). Table 1 summarizes the comparative results.
The results demonstrate that the new method improves SPC for different DOI types by making available to the fab an enhanced data set on which to base the monitoring process. DOI types that could not be monitored before now appear in numbers that allows stable monitoring (Figure 7).
AUTOMATIC SEM REVIEW CONCEPTTraditionally, SEM review is performed on a sample of
the inspection results. The images are then manually
classified for DOI/nuisance and for the different DOI
types. When the inspection nuisance rate is high,
a major part of the classification work is spent on
nuisances. SEM automatic defect redetection (ADR)
can filter out most of the nuisances, allowing manual
classification effort to be devoted to true defects,
binning them according to different DOI types.
A greater number of defects can thus be reviewed for
the same investment of labor (Figure 5).
Two inherent advantages of the SEM over optical
inspection tools enable this filtering:
• Higher resolution—SEM pixel size is significantly
smaller
• Reduced underlayer visibility—contrary to the
optical tool, only the top layers are visible by
SEM imaging, which efficiently separates top
layer defects from lower layer defects (usually
considered nuisance and detected when the
top layer is transparent to the inspection tool
wavelength)
Table 1. Comparison of
traditional and new
approaches for types of
DOI that can be monitored.
Figure 5
Def
ects
Insp
ecte
d
Wafers
Post-Inspection Results
W1 W3 W5 W7 W9 W11 W13 W15 W17 W19
250
200
150
100
50
0
NuisanceDOI
Def
ects
Insp
ecte
d
Wafers
Post-Filtering Results
W1 W3 W5 W7 W9 W11 W13 W15 W17 W19
250
200
150
100
50
0
NuisanceDOI
Figure 5. True and nuisance
distribution per wafer before
and after SEM ADR filtering.
Figure 6. New ADR method
set to 60 true defects keeps
classification effort constant.
The ability to monitor excursions for each DOI type was
also tested by examining SPC charts of each defect type
over the 19 wafers. Results demonstrate a dramatic
improvement in the ability to monitor excursions,
especially for rarely occurring DOI (Figure 8). Early
excursion detection enables the fab to react promptly
before the source of the excursion significantly affects
yield.
Figure 8
# o
f D
efec
ts
Lot/Wafer
Defocus
(a)
Lot1W1
Lot1W2
Lot1W3
Lot2W1
Lot2W2
Lot2W3
Lot3W1
Lot3W2
Lot3W3
Lot4W1
Lot4W2
Lot4W3
Lot5W1
Lot5W2
Lot5W3
Lot6W1
Lot6W2
Lot6W3
Lot6W6
10
5
0
TraditionalNew Flow
# o
f D
efec
ts
Lot/Wafer
Shallow Extra Pattern
(b)
Lot1W1
Lot1W2
Lot1W3
Lot2W1
Lot2W2
Lot2W3
Lot3W1
Lot3W2
Lot3W3
Lot4W1
Lot4W2
Lot4W3
Lot5W1
Lot5W2
Lot5W3
Lot6W1
Lot6W2
Lot6W3
Lot6W6
30
20
10
0
TraditionalNew Flow
CONCLUSIONShrinking design rules make separating true from nuisance defects detected by optical inspection tools ever more challenging. To address this challenge without adding to the fab burden, new inspection and review methods employ SEM-inherent advantages for automatic review and nuisance filtering. The new method revealed DOI types in the pareto that were undetected by traditional production flow. Moreover, the new method is also more sensitive to excursions in the defect type count. These two enhancements in defect monitoring can cost-effectively improve fab yield-management capabilities by using the existing toolset and not requiring additional labor.
ACKNOWLEDGEMENTSThe authors wish to acknowledge the collaboration of Remo Kirsch and Ulrich Zeiske of GLOBALFOUNDRIES in this work.
REFERENCES[1] “2010 Update, International Technology Roadmap
for Semiconductors,” Semiconductor Industry Association, http://www.itrs.net/Links/2010ITRS/Home2010.htm.
32Volume 10, Issue 1, 2012Nanochip Technology JournalApplied Materials, Inc. Applied Materials, Inc.
Automatic Defect Redetection
Figure 6 demonstrates the enhanced results and labor-saving effectiveness of the SEM ADR when the SEM was set to review defects until it reached a constant, predefined number (60) of true defects in each run (versus the traditional fixed number of total reviewed defects).
ResultsAnalysis was performed on <45nm node features using 19 wafers from different lots. Each wafer was inspected and reviewed twice, first using the “traditional” approach (inspection recipe optimized for low nuisance, review of 60 locations) and then using the new approach (inspection recipe optimized for maximum sensitivity, automatic review until 60 true defects were detected by SEM). DOI were manually classified (60 images for each method). Table 1 summarizes the comparative results.
The results demonstrate that the new method improves SPC for different DOI types by making available to the fab an enhanced data set on which to base the monitoring process. DOI types that could not be monitored before now appear in numbers that allows stable monitoring (Figure 7).
Two inherent advantages of the SEM over optical
inspection tools enable this filtering:
• Higher resolution—SEM pixel size is significantly
smaller
• Reduced underlayer visibility—contrary to the
optical tool, only the top layers are visible by
SEM imaging, which efficiently separates top
layer defects from lower layer defects (usually
considered nuisance and detected when the
top layer is transparent to the inspection tool
wavelength)
Figure 5
Def
ects
Insp
ecte
d
Wafers
Post-Inspection Results
W1 W3 W5 W7 W9 W11 W13 W15 W17 W19
250
200
150
100
50
0
NuisanceDOI
Def
ects
Insp
ecte
d
Wafers
Post-Filtering Results
W1 W3 W5 W7 W9 W11 W13 W15 W17 W19
250
200
150
100
50
0
NuisanceDOI
The ability to monitor excursions for each DOI type was
also tested by examining SPC charts of each defect type
over the 19 wafers. Results demonstrate a dramatic
improvement in the ability to monitor excursions,
especially for rarely occurring DOI (Figure 8). Early
excursion detection enables the fab to react promptly
before the source of the excursion significantly affects
yield.
Figure 7
ShallowExtra
Pattern
ExtraPattern
Pitting Scratch Hole Defocus SEM NV
Def
ects
Defect Pareto
30
25
20
15
10
5
0
TraditionalNew Flow
Figure 8
# o
f D
efec
ts
Lot/Wafer
Defocus
(a)
Lot1W1
Lot1W2
Lot1W3
Lot2W1
Lot2W2
Lot2W3
Lot3W1
Lot3W2
Lot3W3
Lot4W1
Lot4W2
Lot4W3
Lot5W1
Lot5W2
Lot5W3
Lot6W1
Lot6W2
Lot6W3
Lot6W6
10
5
0
TraditionalNew Flow
# o
f D
efec
ts
Lot/Wafer
Shallow Extra Pattern
(b)
Lot1W1
Lot1W2
Lot1W3
Lot2W1
Lot2W2
Lot2W3
Lot3W1
Lot3W2
Lot3W3
Lot4W1
Lot4W2
Lot4W3
Lot5W1
Lot5W2
Lot5W3
Lot6W1
Lot6W2
Lot6W3
Lot6W6
30
20
10
0
TraditionalNew Flow
CONCLUSIONShrinking design rules make separating true from nuisance defects detected by optical inspection tools ever more challenging. To address this challenge without adding to the fab burden, new inspection and review methods employ SEM-inherent advantages for automatic review and nuisance filtering. The new method revealed DOI types in the pareto that were undetected by traditional production flow. Moreover, the new method is also more sensitive to excursions in the defect type count. These two enhancements in defect monitoring can cost-effectively improve fab yield-management capabilities by using the existing toolset and not requiring additional labor.
ACKNOWLEDGEMENTSThe authors wish to acknowledge the collaboration of Remo Kirsch and Ulrich Zeiske of GLOBALFOUNDRIES in this work.
REFERENCES[1] “2010 Update, International Technology Roadmap
for Semiconductors,” Semiconductor Industry Association, http://www.itrs.net/Links/2010ITRS/Home2010.htm.
AUTHORSLiran Yerushalmi is a marketing manager in the PDC
Group at Applied Materials. He earned his MBA in
business management from Tel Aviv University, Israel.
Saar Shabtay is an application development manager in
the PDC Group at Applied Materials. He holds his B.S.
in physics from Ben Gurion University, Israel.
Mirko Beyer is a senior application engineer in the PDC
group at Applied Materials, supporting the Dresden
Logic Account team.
Oren Goshen is a product specialist in the PDC Group at
Applied Materials. He received his B.A. in mathematics
from Ben Gurion University, Israel.
ARTICLE [email protected]
Adapted from Metrology, Inspection and Process Control
for Microlithography XXV, Proc. of SPIE Vol. 7971 79712M-1-
79712M-8. © 2011 SPIE.
Figure 7. Traditional 60
defects review versus ADR
set to 60 true defects shows
the new DOI types revealed
by the new approach.
Figure 8. (a) SPC chart
for DOI Defocus and
(b) Shallow Extra Pattern
illustrates that the excursions
were identified only by using
the new flow.
Notes
33 Volume 10, Issue 1, 2012 Nanochip Technology Journal Applied Materials, Inc.
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